This new DMA API corrects possible cache coherency issues on chips with
D-Cache, when working with buffers at arbitrary memory locations (i.e.
supplied by Python code).
The API is used by SPI to fix an issue with corrupt data when reading from
SPI using DMA in certain cases. A regression test is included (it depends
on external hardware connection).
Explanation:
1) It's necessary to invalidate D-Cache after a DMA RX operation completes
in case the CPU reads (or speculatively reads) from the DMA RX region
during the operation. This seems to have been the root cause of issue
#13471 (only when src==dest for this case).
2) More generally, it is also necessary to temporarily mark the first and
last cache lines of a DMA RX operation as "uncached", in case the DMA
buffer shares this cache line with unrelated data. The CPU could
otherwise write the other data at any time during the DMA operation (for
example from an interrupt handler), creating a dirty cache line that's
inconsistent with the DMA result.
Fixes issue #13471.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
The existing MPU_CONFIG_DISABLE macro enables the MPU region but disables
all access to it.
The rename is necessary to support an MPU_CONFIG_DISABLE macro that
actually disables the MPU region entirely.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
Also move MICROPY_PY_PENDSV_ENTER/REENTER/EXIT to mphalport.h, for ports
where these are not already there.
This helps separate the hardware implementation of these macros from the
MicroPython configuration (eg for renesas-ra and stm32, the IRQ static
inline helper functions can now be moved to irq.h).
Signed-off-by: Damien George <damien@micropython.org>
This commit implements Ethernet support for STM32H5. Changes are:
- Add Cortex-M33 MPU code. Ethernet driver requires MPU to define cache
strategy for DMA buffers (descriptors and frames).
- Add support for STM32H5 Ethernet controller. The controller is mostly
compatible with the STM32H7. However the descriptor layout is different.
- Adapt clocking and reset for STM32H5.
Tested on NUCLEO-H563ZI and STM32H573I-DK, using ping and iperf3. TCP
rates of 80-90 Mbits/sec were achievable.
Signed-off-by: Rene Straub <rene@see5.ch>
Signed-off-by: Damien George <damien@micropython.org>
This commit adds initial support for STM32H5xx MCUs. The following
features have been confirmed to be working on an STM32H573:
- UART over REPL and USB CDC
- USB CDC and MSC
- internal flash filesystem
- machine.Pin
- machine.SPI transfers with DMA
- machine.ADC
- machine.RTC
- pyb.LED
- pyb.Switch
- pyb.rng
- mboot
Signed-off-by: Damien George <damien@micropython.org>
The Cortex-M7 CPU will do speculative loads from any memory location that
is not explicitly forbidden. This includes the QSPI memory-mapped region
starting at 0x90000000 and with size 256MiB. Speculative loads to this
QSPI region may 1) interfere with the QSPI peripheral registers (eg the
address register) if the QSPI is not in memory-mapped mode; 2) attempt to
access data outside the configured size of the QSPI flash when it is in
memory-mapped mode. Both of these scenarios will lead to issues with the
QSPI peripheral (eg Cortex bus lock up in scenario 2).
To prevent such speculative loads from interfering with the peripheral the
MPU is configured in this commit to restrict access to the QSPI mapped
region: when not memory mapped the entire region is forbidden; when memory
mapped only accesses to the valid flash size are permitted.
iabdalkader