kopia lustrzana https://github.com/micropython/micropython
stm32/eth: Add Ethernet support for H5 MCUs.
This commit implements Ethernet support for STM32H5. Changes are: - Add Cortex-M33 MPU code. Ethernet driver requires MPU to define cache strategy for DMA buffers (descriptors and frames). - Add support for STM32H5 Ethernet controller. The controller is mostly compatible with the STM32H7. However the descriptor layout is different. - Adapt clocking and reset for STM32H5. Tested on NUCLEO-H563ZI and STM32H573I-DK, using ping and iperf3. TCP rates of 80-90 Mbits/sec were achievable. Signed-off-by: Rene Straub <rene@see5.ch> Signed-off-by: Damien George <damien@micropython.org>pull/12226/head
Rene Straub
Damien George
rodzic
8b12923da2
commit
51da8cc28b
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@ -62,7 +62,19 @@
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#define PHY_SCSR_SPEED_100FULL (6 << PHY_SCSR_SPEED_Pos)
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// ETH DMA RX and TX descriptor definitions
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#if defined(STM32H7)
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#if defined(STM32H5)
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#define RX_DESCR_3_OWN_Pos (31)
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#define RX_DESCR_3_IOC_Pos (30)
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#define RX_DESCR_3_BUF1V_Pos (24)
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#define RX_DESCR_3_PL_Msk (0x7fff)
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#define TX_DESCR_3_OWN_Pos (31)
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#define TX_DESCR_3_FD_Pos (29)
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#define TX_DESCR_3_LD_Pos (28)
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#define TX_DESCR_3_CIC_Pos (16)
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#define TX_DESCR_2_B1L_Pos (0)
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#define TX_DESCR_2_B1L_Msk (0x3fff << TX_DESCR_2_B1L_Pos)
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#elif defined(STM32H7)
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#define RX_DESCR_3_OWN_Pos (31)
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#define RX_DESCR_3_IOC_Pos (30)
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#define RX_DESCR_3_BUF1V_Pos (24)
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@ -135,7 +147,7 @@ STATIC void eth_mac_deinit(eth_t *self);
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STATIC void eth_process_frame(eth_t *self, size_t len, const uint8_t *buf);
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STATIC void eth_phy_write(uint32_t reg, uint32_t val) {
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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while (ETH->MACMDIOAR & ETH_MACMDIOAR_MB) {
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}
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uint32_t ar = ETH->MACMDIOAR;
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@ -161,7 +173,7 @@ STATIC void eth_phy_write(uint32_t reg, uint32_t val) {
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}
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STATIC uint32_t eth_phy_read(uint32_t reg) {
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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while (ETH->MACMDIOAR & ETH_MACMDIOAR_MB) {
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}
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uint32_t ar = ETH->MACMDIOAR;
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@ -202,7 +214,11 @@ void eth_init(eth_t *self, int mac_idx) {
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mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RMII_TXD1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH_RMII_TXD1);
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// Enable peripheral clock
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#if defined(STM32H7)
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#if defined(STM32H5)
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__HAL_RCC_ETH_CLK_ENABLE();
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__HAL_RCC_ETHTX_CLK_ENABLE();
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__HAL_RCC_ETHRX_CLK_ENABLE();
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#elif defined(STM32H7)
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__HAL_RCC_ETH1MAC_CLK_ENABLE();
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__HAL_RCC_ETH1TX_CLK_ENABLE();
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__HAL_RCC_ETH1RX_CLK_ENABLE();
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@ -218,11 +234,20 @@ void eth_set_trace(eth_t *self, uint32_t value) {
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STATIC int eth_mac_init(eth_t *self) {
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// Configure MPU
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uint32_t irq_state = mpu_config_start();
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#if defined(STM32H5)
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mpu_config_region(MPU_REGION_ETH, (uint32_t)ð_dma, MPU_CONFIG_ETH(16 * 1024));
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#else
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mpu_config_region(MPU_REGION_ETH, (uint32_t)ð_dma, MPU_CONFIG_ETH(MPU_REGION_SIZE_16KB));
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#endif
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mpu_config_end(irq_state);
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// Enable peripheral clock
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#if defined(STM32H7)
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#if defined(STM32H5)
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__HAL_RCC_ETH_CLK_ENABLE();
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__HAL_RCC_ETHTX_CLK_ENABLE();
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__HAL_RCC_ETHRX_CLK_ENABLE();
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__HAL_RCC_ETH_FORCE_RESET();
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#elif defined(STM32H7)
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__HAL_RCC_ETH1MAC_CLK_ENABLE();
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__HAL_RCC_ETH1TX_CLK_ENABLE();
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__HAL_RCC_ETH1RX_CLK_ENABLE();
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@ -233,14 +258,23 @@ STATIC int eth_mac_init(eth_t *self) {
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#endif
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// Select RMII interface
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#if defined(STM32H7)
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#if defined(STM32H5)
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__HAL_RCC_SBS_CLK_ENABLE();
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SBS->PMCR = (SBS->PMCR & ~SBS_PMCR_ETH_SEL_PHY_Msk) | SBS_PMCR_ETH_SEL_PHY_2;
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#elif defined(STM32H7)
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SYSCFG->PMCR = (SYSCFG->PMCR & ~SYSCFG_PMCR_EPIS_SEL_Msk) | SYSCFG_PMCR_EPIS_SEL_2;
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#else
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__HAL_RCC_SYSCFG_CLK_ENABLE();
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SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;
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#endif
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#if defined(STM32H7)
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#if defined(STM32H5)
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__HAL_RCC_ETH_RELEASE_RESET();
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__HAL_RCC_ETH_CLK_SLEEP_ENABLE();
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__HAL_RCC_ETHTX_CLK_SLEEP_ENABLE();
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__HAL_RCC_ETHRX_CLK_SLEEP_ENABLE();
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#elif defined(STM32H7)
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__HAL_RCC_ETH1MAC_RELEASE_RESET();
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__HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE();
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@ -255,7 +289,7 @@ STATIC int eth_mac_init(eth_t *self) {
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#endif
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// Do a soft reset of the MAC core
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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#define ETH_SOFT_RESET(eth) do { eth->DMAMR = ETH_DMAMR_SWR; } while (0)
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#define ETH_IS_RESET(eth) (eth->DMAMR & ETH_DMAMR_SWR)
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#else
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@ -277,7 +311,23 @@ STATIC int eth_mac_init(eth_t *self) {
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// Set MII clock range
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uint32_t hclk = HAL_RCC_GetHCLKFreq();
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uint32_t cr_div;
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#if defined(STM32H7)
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#if defined(STM32H5)
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cr_div = ETH->MACMDIOAR & ~ETH_MACMDIOAR_CR;
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if (hclk < 35000000) {
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cr_div |= ETH_MACMDIOAR_CR_DIV16;
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} else if (hclk < 60000000) {
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cr_div |= ETH_MACMDIOAR_CR_DIV26;
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} else if (hclk < 100000000) {
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cr_div |= ETH_MACMDIOAR_CR_DIV42;
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} else if (hclk < 150000000) {
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cr_div |= ETH_MACMDIOAR_CR_DIV62;
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} else if (hclk < 250000000) {
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cr_div |= ETH_MACMDIOAR_CR_DIV102;
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} else {
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cr_div |= ETH_MACMDIOAR_CR_DIV124;
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}
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ETH->MACMDIOAR = cr_div;
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#elif defined(STM32H7)
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cr_div = ETH->MACMDIOAR & ~ETH_MACMDIOAR_CR;
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if (hclk < 35000000) {
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cr_div |= ETH_MACMDIOAR_CR_DIV16;
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@ -306,7 +356,7 @@ STATIC int eth_mac_init(eth_t *self) {
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ETH->MACMIIAR = cr_div;
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#endif
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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// don't skip 32bit words since our descriptors are continuous in memory
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ETH->DMACCR &= ~(ETH_DMACCR_DSL_Msk);
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#endif
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@ -351,7 +401,7 @@ STATIC int eth_mac_init(eth_t *self) {
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uint16_t phy_scsr = eth_phy_read(PHY_SCSR);
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// Burst mode configuration
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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ETH->DMASBMR = ETH->DMASBMR & ~ETH_DMASBMR_AAL & ~ETH_DMASBMR_FB;
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#else
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ETH->DMABMR = 0;
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@ -359,7 +409,7 @@ STATIC int eth_mac_init(eth_t *self) {
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mp_hal_delay_ms(2);
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// Select DMA interrupts
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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ETH->DMACIER = ETH->DMACIER
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| ETH_DMACIER_NIE // enable normal interrupts
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| ETH_DMACIER_RIE // enable RX interrupt
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@ -373,7 +423,7 @@ STATIC int eth_mac_init(eth_t *self) {
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// Configure RX descriptor lists
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for (size_t i = 0; i < RX_BUF_NUM; ++i) {
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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eth_dma.rx_descr[i].rdes3 =
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1 << RX_DESCR_3_OWN_Pos
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| (1 << RX_DESCR_3_BUF1V_Pos) // buf1 address valid
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@ -391,7 +441,7 @@ STATIC int eth_mac_init(eth_t *self) {
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#endif
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}
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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ETH->DMACRDLAR = (uint32_t)ð_dma.rx_descr[0];
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#else
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ETH->DMARDLAR = (uint32_t)ð_dma.rx_descr[0];
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@ -400,7 +450,7 @@ STATIC int eth_mac_init(eth_t *self) {
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// Configure TX descriptor lists
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for (size_t i = 0; i < TX_BUF_NUM; ++i) {
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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eth_dma.tx_descr[i].tdes0 = 0;
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eth_dma.tx_descr[i].tdes1 = 0;
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eth_dma.tx_descr[i].tdes2 = TX_BUF_SIZE & TX_DESCR_2_B1L_Msk;
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@ -413,7 +463,7 @@ STATIC int eth_mac_init(eth_t *self) {
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#endif
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}
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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// set number of descriptors and buffers
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ETH->DMACTDRLR = TX_BUF_NUM - 1;
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ETH->DMACRDRLR = RX_BUF_NUM - 1;
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@ -425,7 +475,7 @@ STATIC int eth_mac_init(eth_t *self) {
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eth_dma.tx_descr_idx = 0;
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// Configure DMA
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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// read from RX FIFO only after a full frame is written
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ETH->MTLRQOMR = ETH_MTLRQOMR_RSF;
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// transmission starts when a full packet resides in the Tx queue
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@ -439,7 +489,7 @@ STATIC int eth_mac_init(eth_t *self) {
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mp_hal_delay_ms(2);
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// Select MAC filtering options
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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ETH->MACPFR = ETH_MACPFR_RA; // pass all frames up
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#else
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ETH->MACFFR =
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@ -472,7 +522,7 @@ STATIC int eth_mac_init(eth_t *self) {
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mp_hal_delay_ms(2);
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// Start DMA layer
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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ETH->DMACRCR |= ETH_DMACRCR_SR; // start RX
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ETH->DMACTCR |= ETH_DMACTCR_ST; // start TX
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#else
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@ -493,7 +543,11 @@ STATIC int eth_mac_init(eth_t *self) {
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STATIC void eth_mac_deinit(eth_t *self) {
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(void)self;
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HAL_NVIC_DisableIRQ(ETH_IRQn);
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#if defined(STM32H7)
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#if defined(STM32H5)
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__HAL_RCC_ETH_FORCE_RESET();
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__HAL_RCC_ETH_RELEASE_RESET();
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__HAL_RCC_ETH_CLK_DISABLE();
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#elif defined(STM32H7)
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__HAL_RCC_ETH1MAC_FORCE_RESET();
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__HAL_RCC_ETH1MAC_RELEASE_RESET();
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__HAL_RCC_ETH1MAC_CLK_DISABLE();
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@ -513,7 +567,7 @@ STATIC int eth_tx_buf_get(size_t len, uint8_t **buf) {
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eth_dma_tx_descr_t *tx_descr = ð_dma.tx_descr[eth_dma.tx_descr_idx];
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uint32_t t0 = mp_hal_ticks_ms();
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for (;;) {
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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if (!(tx_descr->tdes3 & (1 << TX_DESCR_3_OWN_Pos))) {
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break;
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}
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@ -527,7 +581,7 @@ STATIC int eth_tx_buf_get(size_t len, uint8_t **buf) {
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}
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}
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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// Update TX descriptor with length and buffer pointer
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*buf = ð_dma.tx_buf[eth_dma.tx_descr_idx * TX_BUF_SIZE];
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tx_descr->tdes2 = len & TX_DESCR_2_B1L_Msk;
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@ -549,7 +603,7 @@ STATIC int eth_tx_buf_send(void) {
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eth_dma.tx_descr_idx = (eth_dma.tx_descr_idx + 1) % TX_BUF_NUM;
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// Schedule to send next outgoing frame
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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tx_descr->tdes3 =
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1 << TX_DESCR_3_OWN_Pos // owned by DMA
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| 1 << TX_DESCR_3_LD_Pos // last segment
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@ -568,7 +622,7 @@ STATIC int eth_tx_buf_send(void) {
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// Notify ETH DMA that there is a new TX descriptor for sending
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__DMB();
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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if (ETH->DMACSR & ETH_DMACSR_TBU) {
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ETH->DMACSR = ETH_DMACSR_TBU;
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}
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@ -590,7 +644,7 @@ STATIC void eth_dma_rx_free(void) {
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eth_dma.rx_descr_idx = (eth_dma.rx_descr_idx + 1) % RX_BUF_NUM;
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// Schedule to get next incoming frame
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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rx_descr->rdes0 = (uint32_t)buf;
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rx_descr->rdes3 = 1 << RX_DESCR_3_OWN_Pos; // owned by DMA
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rx_descr->rdes3 |= 1 << RX_DESCR_3_BUF1V_Pos; // buf 1 address valid
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@ -607,7 +661,7 @@ STATIC void eth_dma_rx_free(void) {
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// Notify ETH DMA that there is a new RX descriptor available
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__DMB();
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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ETH->DMACRDTPR = (uint32_t)&rx_descr[eth_dma.rx_descr_idx];
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#else
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ETH->DMARPDR = 0;
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@ -615,7 +669,7 @@ STATIC void eth_dma_rx_free(void) {
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}
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void ETH_IRQHandler(void) {
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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uint32_t sr = ETH->DMACSR;
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ETH->DMACSR = ETH_DMACSR_NIS;
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uint32_t rx_interrupt = sr & ETH_DMACSR_RI;
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@ -625,13 +679,13 @@ void ETH_IRQHandler(void) {
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uint32_t rx_interrupt = sr & ETH_DMASR_RS;
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#endif
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if (rx_interrupt) {
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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ETH->DMACSR = ETH_DMACSR_RI;
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#else
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ETH->DMASR = ETH_DMASR_RS;
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#endif
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for (;;) {
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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eth_dma_rx_descr_t *rx_descr_l = ð_dma.rx_descr[eth_dma.rx_descr_idx];
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if (rx_descr_l->rdes3 & (1 << RX_DESCR_3_OWN_Pos)) {
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// No more RX descriptors ready to read
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@ -646,13 +700,13 @@ void ETH_IRQHandler(void) {
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#endif
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// Get RX buffer containing new frame
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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size_t len = (rx_descr_l->rdes3 & RX_DESCR_3_PL_Msk);
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#else
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size_t len = (rx_descr->rdes0 & RX_DESCR_0_FL_Msk) >> RX_DESCR_0_FL_Pos;
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#endif
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len -= 4; // discard CRC at end
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#if defined(STM32H7)
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#if defined(STM32H5) || defined(STM32H7)
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uint8_t *buf = ð_dma.rx_buf[eth_dma.rx_descr_idx * RX_BUF_SIZE];
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#else
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uint8_t *buf = (uint8_t *)rx_descr->rdes2;
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@ -26,7 +26,7 @@
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#ifndef MICROPY_INCLUDED_STM32_MPU_H
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#define MICROPY_INCLUDED_STM32_MPU_H
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#if defined(STM32F7) || defined(STM32H7) || defined(MICROPY_HW_ETH_MDC)
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#if (defined(STM32F4) && defined(MICROPY_HW_ETH_MDC)) || defined(STM32F7) || defined(STM32H7)
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#define MPU_REGION_ETH (MPU_REGION_NUMBER0)
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#define MPU_REGION_QSPI1 (MPU_REGION_NUMBER1)
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@ -97,9 +97,16 @@ static inline void mpu_config_end(uint32_t irq_state) {
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#elif defined(STM32H5)
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#define MPU_REGION_SIG (MPU_REGION_NUMBER0)
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#define MPU_REGION_ETH (MPU_REGION_NUMBER1)
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#define ST_DEVICE_SIGNATURE_BASE (0x08fff800)
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#define ST_DEVICE_SIGNATURE_LIMIT (0x08ffffff)
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// STM32H5 Cortex-M33 MPU works differently from older cores.
|
||||
// Macro only takes region size in bytes, Attributes are coded in mpu_config_region().
|
||||
#define MPU_CONFIG_ETH(size) (size)
|
||||
|
||||
static inline void mpu_init(void) {
|
||||
// Configure attribute 0, inner-outer non-cacheable (=0x44).
|
||||
__DMB();
|
||||
|
|
@ -125,6 +132,49 @@ static inline void mpu_init(void) {
|
|||
__ISB();
|
||||
}
|
||||
|
||||
static inline uint32_t mpu_config_start(void) {
|
||||
return disable_irq();
|
||||
}
|
||||
|
||||
static inline void mpu_config_region(uint32_t region, uint32_t base_addr, uint32_t size) {
|
||||
if (region == MPU_REGION_ETH) {
|
||||
// Configure region 1 to make DMA memory non-cacheable.
|
||||
|
||||
__DMB();
|
||||
// Configure attribute 1, inner-outer non-cacheable (=0x44).
|
||||
MPU->MAIR0 = (MPU->MAIR0 & ~MPU_MAIR0_Attr1_Msk)
|
||||
| 0x44 << MPU_MAIR0_Attr1_Pos;
|
||||
__DMB();
|
||||
|
||||
// RBAR
|
||||
// BASE Bits [31:5] of base address
|
||||
// SH[4:3] 00 = Non-shareable
|
||||
// AP[2:1] 01 = Read/write by any privilege level
|
||||
// XN[0]: 1 = No execution
|
||||
|
||||
// RLAR
|
||||
// LIMIT Limit address. Contains bits[31:5] of the upper inclusive limit of the selected MPU memory region
|
||||
// AT[3:1] 001 = Attribute 1
|
||||
// EN[0] 1 = Enabled
|
||||
MPU->RNR = region;
|
||||
MPU->RBAR = (base_addr & MPU_RBAR_BASE_Msk)
|
||||
| MPU_ACCESS_NOT_SHAREABLE << MPU_RBAR_SH_Pos
|
||||
| MPU_REGION_ALL_RW << MPU_RBAR_AP_Pos
|
||||
| MPU_INSTRUCTION_ACCESS_DISABLE << MPU_RBAR_XN_Pos;
|
||||
MPU->RLAR = ((base_addr + size - 1) & MPU_RLAR_LIMIT_Msk)
|
||||
| MPU_ATTRIBUTES_NUMBER1 << MPU_RLAR_AttrIndx_Pos
|
||||
| MPU_REGION_ENABLE << MPU_RLAR_EN_Pos;
|
||||
}
|
||||
__DMB();
|
||||
}
|
||||
|
||||
static inline void mpu_config_end(uint32_t irq_state) {
|
||||
__ISB();
|
||||
__DSB();
|
||||
__DMB();
|
||||
enable_irq(irq_state);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static inline void mpu_init(void) {
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue