Use configuration option instead of in components not related to FreeRTOS

Mergeshttps://github.com/espressif/esp-idf/pull/12481
2023-10-30 01:23:23 -05:00 · 2023-10-30 01:23:23 -05:00 · d149c1b26f
commit d149c1b26f
--- a/components/app_trace/Kconfig
+++ b/components/app_trace/Kconfig
@ -231,7 +231,7 @@ menu "Application Level Tracing"

        choice APPTRACE_SV_CPU
            prompt "CPU to trace"
-            depends on APPTRACE_SV_DEST_UART && !FREERTOS_UNICORE
+            depends on APPTRACE_SV_DEST_UART && !ESP_SYSTEM_SINGLE_CORE_MODE
            default APPTRACE_SV_DEST_CPU_0
            help
                Define the CPU to trace by SystemView.
@ -252,8 +252,8 @@ menu "Application Level Tracing"
        choice APPTRACE_SV_TS_SOURCE
            prompt "Timer to use as timestamp source"
            depends on APPTRACE_SV_ENABLE
-            default APPTRACE_SV_TS_SOURCE_CCOUNT if FREERTOS_UNICORE && !PM_ENABLE && !IDF_TARGET_ESP32C3
-            default APPTRACE_SV_TS_SOURCE_GPTIMER if !FREERTOS_UNICORE && !PM_ENABLE && !IDF_TARGET_ESP32C3
+            default APPTRACE_SV_TS_SOURCE_CCOUNT if ESP_SYSTEM_SINGLE_CORE_MODE && !PM_ENABLE && !IDF_TARGET_ESP32C3
+            default APPTRACE_SV_TS_SOURCE_GPTIMER if !ESP_SYSTEM_SINGLE_CORE_MODE && !PM_ENABLE && !IDF_TARGET_ESP32C3
            default APPTRACE_SV_TS_SOURCE_ESP_TIMER if PM_ENABLE || IDF_TARGET_ESP32C3
            help
                SystemView needs to use a hardware timer as the source of timestamps
@ -261,7 +261,7 @@ menu "Application Level Tracing"

            config APPTRACE_SV_TS_SOURCE_CCOUNT
                bool "CPU cycle counter (CCOUNT)"
-                depends on FREERTOS_UNICORE && !PM_ENABLE && !IDF_TARGET_ESP32C3
+                depends on ESP_SYSTEM_SINGLE_CORE_MODE && !PM_ENABLE && !IDF_TARGET_ESP32C3

            config APPTRACE_SV_TS_SOURCE_GPTIMER
                bool "General Purpose Timer (Timer Group)"
--- a/components/app_trace/port/xtensa/port.c
+++ b/components/app_trace/port/xtensa/port.c
@ -298,7 +298,7 @@ static inline void esp_apptrace_trax_memory_enable(void)
 #if CONFIG_IDF_TARGET_ESP32
        /* Enable trace memory on PRO CPU */
        DPORT_WRITE_PERI_REG(DPORT_PRO_TRACEMEM_ENA_REG, DPORT_PRO_TRACEMEM_ENA_M);
-#if CONFIG_FREERTOS_UNICORE == 0
+#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE == 0
        /* Enable trace memory on APP CPU */
        DPORT_WRITE_PERI_REG(DPORT_APP_TRACEMEM_ENA_REG, DPORT_APP_TRACEMEM_ENA_M);
 #endif
--- a/components/app_trace/sys_view/esp/SEGGER_RTT_esp.c
+++ b/components/app_trace/sys_view/esp/SEGGER_RTT_esp.c
@ -35,7 +35,7 @@ static uint8_t s_down_buf[SYSVIEW_DOWN_BUF_SIZE];
 #if CONFIG_APPTRACE_SV_DEST_UART

 #define ESP_APPTRACE_DEST_SYSVIEW ESP_APPTRACE_DEST_UART
-#if CONFIG_APPTRACE_SV_DEST_CPU_0 || CONFIG_FREERTOS_UNICORE
+#if CONFIG_APPTRACE_SV_DEST_CPU_0 || CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 #define APPTRACE_SV_DEST_CPU 0
 #else
 #define APPTRACE_SV_DEST_CPU 1
--- a/components/bootloader_support/include/bootloader_memory_utils.h
+++ b/components/bootloader_support/include/bootloader_memory_utils.h
@ -39,7 +39,7 @@ inline static bool esp_dram_match_iram(void) {
 */
 __attribute__((always_inline))
 inline static bool esp_ptr_in_iram(const void *p) {
-#if CONFIG_IDF_TARGET_ESP32 && CONFIG_FREERTOS_UNICORE
+#if CONFIG_IDF_TARGET_ESP32 && CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    return ((intptr_t)p >= SOC_CACHE_APP_LOW && (intptr_t)p < SOC_IRAM_HIGH);
 #else
    return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH);
--- a/components/bootloader_support/src/bootloader_init.c
+++ b/components/bootloader_support/src/bootloader_init.c
@ -103,7 +103,7 @@ void bootloader_print_banner(void)
 #endif
    }

-#if CONFIG_FREERTOS_UNICORE
+#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 #if (SOC_CPU_CORES_NUM > 1)
    ESP_EARLY_LOGW(TAG, "Unicore bootloader");
 #endif
--- a/components/bootloader_support/src/bootloader_utility.c
+++ b/components/bootloader_support/src/bootloader_utility.c
@ -884,7 +884,7 @@ static void set_cache_and_start_app(
    bus_mask = cache_ll_l1_get_bus(0, irom_load_addr_aligned, irom_size);
    cache_ll_l1_enable_bus(0, bus_mask);

-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    bus_mask = cache_ll_l1_get_bus(1, drom_load_addr_aligned, drom_size);
    cache_ll_l1_enable_bus(1, bus_mask);
    bus_mask = cache_ll_l1_get_bus(1, irom_load_addr_aligned, irom_size);
--- a/components/bootloader_support/src/esp32/bootloader_esp32.c
+++ b/components/bootloader_support/src/esp32/bootloader_esp32.c
@ -44,15 +44,15 @@ static void bootloader_reset_mmu(void)
 {
    /* completely reset MMU in case serial bootloader was running */
    Cache_Read_Disable(0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    Cache_Read_Disable(1);
 #endif
    Cache_Flush(0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    Cache_Flush(1);
 #endif
    mmu_init(0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    /* The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are
        necessary to work around a hardware bug. */
    DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
@ -63,7 +63,7 @@ static void bootloader_reset_mmu(void)
    /* normal ROM boot exits with DROM0 cache unmasked,
        but serial bootloader exits with it masked. */
    DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
 #endif
 }
@ -104,7 +104,7 @@ static void wdt_reset_info_dump(int cpu)
        lsaddr = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG);
        lsdata = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG);
    } else {
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
        stat = DPORT_REG_READ(DPORT_APP_CPU_RECORD_STATUS_REG);
        pid = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PID_REG);
        inst = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGINST_REG);
@ -154,7 +154,7 @@ static void bootloader_check_wdt_reset(void)
    if (wdt_rst) {
        // if reset by WDT dump info from trace port
        wdt_reset_info_dump(0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
        wdt_reset_info_dump(1);
 #endif
    }
--- a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
+++ b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
@ -72,7 +72,7 @@ static void bootloader_check_wdt_reset(void)
    if (wdt_rst) {
        // if reset by WDT dump info from trace port
        wdt_reset_info_dump(0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
        wdt_reset_info_dump(1);
 #endif
    }
--- a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c
+++ b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c
@ -70,7 +70,7 @@ static void wdt_reset_info_dump(int cpu)
        lsaddr  = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_REG);
        lsdata  = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_REG);
    } else {
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
        inst    = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_REG);
        dstat   = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_REG);
        data    = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_REG);
@ -115,7 +115,7 @@ static void bootloader_check_wdt_reset(void)
    if (wdt_rst) {
        // if reset by WDT dump info from trace port
        wdt_reset_info_dump(0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
        wdt_reset_info_dump(1);
 #endif
    }
--- a/components/esp_gdbstub/src/port/riscv/gdbstub_riscv.c
+++ b/components/esp_gdbstub/src/port/riscv/gdbstub_riscv.c
@ -96,13 +96,13 @@ void esp_gdbstub_init_dports(void)

 #endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME

-#if (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
+#if (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
 static bool stall_started = false;
 #endif

 void esp_gdbstub_stall_other_cpus_start(void)
 {
-#if (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
+#if (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
    if (stall_started == false) {
        esp_ipc_isr_stall_other_cpu();
        stall_started = true;
@ -112,7 +112,7 @@ void esp_gdbstub_stall_other_cpus_start(void)

 void esp_gdbstub_stall_other_cpus_end(void)
 {
-#if (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
+#if (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
    if (stall_started == true) {
        esp_ipc_isr_release_other_cpu();
        stall_started = false;
@ -142,7 +142,7 @@ void esp_gdbstub_do_step(esp_gdbstub_frame_t *frame)

 void esp_gdbstub_trigger_cpu(void)
 {
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    if (0 == esp_cpu_get_core_id()) {
        esp_crosscore_int_send_gdb_call(1);
    } else {
--- a/components/esp_gdbstub/src/port/xtensa/gdbstub_xtensa.c
+++ b/components/esp_gdbstub/src/port/xtensa/gdbstub_xtensa.c
@ -132,7 +132,7 @@ void esp_gdbstub_init_dports(void)
 {
 }

-#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
+#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
 static bool stall_started = false;
 #endif

@ -141,7 +141,7 @@ static bool stall_started = false;
 * */
 void esp_gdbstub_stall_other_cpus_start(void)
 {
-#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
+#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
    if (stall_started == false) {
        esp_ipc_isr_stall_other_cpu();
        stall_started = true;
@ -154,7 +154,7 @@ void esp_gdbstub_stall_other_cpus_start(void)
 * */
 void esp_gdbstub_stall_other_cpus_end(void)
 {
-#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
+#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
    if (stall_started == true) {
        esp_ipc_isr_release_other_cpu();
        stall_started = false;
@ -193,7 +193,7 @@ void esp_gdbstub_do_step( esp_gdbstub_frame_t *frame)
 * */
 void esp_gdbstub_trigger_cpu(void)
 {
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    if (0 == esp_cpu_get_core_id()) {
        esp_crosscore_int_send_gdb_call(1);
    } else {
--- a/components/esp_hw_support/include/dport_access.h
+++ b/components/esp_hw_support/include/dport_access.h
@ -13,7 +13,7 @@
 extern "C" {
 #endif

-#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !SOC_DPORT_WORKAROUND
+#if defined(BOOTLOADER_BUILD) || defined(CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) || !SOC_DPORT_WORKAROUND
 #define DPORT_STALL_OTHER_CPU_START()
 #define DPORT_STALL_OTHER_CPU_END()
 #else
--- a/components/esp_hw_support/include/esp_memory_utils.h
+++ b/components/esp_hw_support/include/esp_memory_utils.h
@ -39,7 +39,7 @@ inline static bool esp_dram_match_iram(void) {
 */
 __attribute__((always_inline))
 inline static bool esp_ptr_in_iram(const void *p) {
-#if CONFIG_IDF_TARGET_ESP32 && CONFIG_FREERTOS_UNICORE
+#if CONFIG_IDF_TARGET_ESP32 && CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    return ((intptr_t)p >= SOC_CACHE_APP_LOW && (intptr_t)p < SOC_IRAM_HIGH);
 #else
    return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH);
@ -230,7 +230,7 @@ inline static bool esp_ptr_executable(const void *p)
    return (ip >= SOC_IROM_LOW && ip < SOC_IROM_HIGH)
        || (ip >= SOC_IRAM_LOW && ip < SOC_IRAM_HIGH)
        || (ip >= SOC_IROM_MASK_LOW && ip < SOC_IROM_MASK_HIGH)
-#if defined(SOC_CACHE_APP_LOW) && defined(CONFIG_FREERTOS_UNICORE)
+#if defined(SOC_CACHE_APP_LOW) && defined(CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE)
        || (ip >= SOC_CACHE_APP_LOW && ip < SOC_CACHE_APP_HIGH)
 #endif
 #if SOC_RTC_FAST_MEM_SUPPORTED
--- a/components/esp_hw_support/include/spinlock.h
+++ b/components/esp_hw_support/include/spinlock.h
@ -51,7 +51,7 @@ typedef struct {
 static inline void __attribute__((always_inline)) spinlock_initialize(spinlock_t *lock)
 {
    assert(lock);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    lock->owner = SPINLOCK_FREE;
    lock->count = 0;
 #endif
@ -73,7 +73,7 @@ static inline void __attribute__((always_inline)) spinlock_initialize(spinlock_t
 */
 static inline bool __attribute__((always_inline)) spinlock_acquire(spinlock_t *lock, int32_t timeout)
 {
-#if !CONFIG_FREERTOS_UNICORE && !BOOTLOADER_BUILD
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !BOOTLOADER_BUILD
    uint32_t irq_status;
    uint32_t core_owner_id, other_core_owner_id;
    bool lock_set;
@ -151,7 +151,7 @@ exit:
 #endif
    return lock_set;

-#else  // !CONFIG_FREERTOS_UNICORE
+#else  // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    return true;
 #endif
 }
@ -171,7 +171,7 @@ exit:
 */
 static inline void __attribute__((always_inline)) spinlock_release(spinlock_t *lock)
 {
-#if !CONFIG_FREERTOS_UNICORE && !BOOTLOADER_BUILD
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !BOOTLOADER_BUILD
    uint32_t irq_status;
    uint32_t core_owner_id;

@ -198,7 +198,7 @@ static inline void __attribute__((always_inline)) spinlock_release(spinlock_t *l
 #else
    rv_utils_restore_intlevel(irq_status);
 #endif  //#if __XTENSA__
-#endif  //#if !CONFIG_FREERTOS_UNICORE && !BOOTLOADER_BUILD
+#endif  //#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !BOOTLOADER_BUILD
 }

 #ifdef __cplusplus
--- a/components/esp_mm/cache_esp32.c
+++ b/components/esp_mm/cache_esp32.c
@ -27,7 +27,7 @@ void cache_sync(void)
    }

    s_cache_drv.cache_flush(0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    s_cache_drv.cache_flush(1);
-#endif // !CONFIG_FREERTOS_UNICORE
+#endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 }
--- a/components/esp_mm/esp_mmu_map.c
+++ b/components/esp_mm/esp_mmu_map.c
@ -402,9 +402,9 @@ FORCE_INLINE_ATTR uint32_t s_mapping_operation(mmu_target_t target, uint32_t vad

    mmu_hal_map_region(0, target, vaddr_start, paddr_start, size, &actual_mapped_len);
 #if (SOC_MMU_PERIPH_NUM == 2)
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    mmu_hal_map_region(1, target, vaddr_start, paddr_start, size, &actual_mapped_len);
-#endif //  #if !CONFIG_FREERTOS_UNICORE
+#endif //  #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 #endif //  #if (SOC_MMU_PERIPH_NUM == 2)

    return actual_mapped_len;
@ -424,7 +424,7 @@ static void IRAM_ATTR NOINLINE_ATTR s_do_mapping(mmu_target_t target, uint32_t v

    cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, vaddr_start, size);
    cache_ll_l1_enable_bus(0, bus_mask);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    bus_mask = cache_ll_l1_get_bus(0, vaddr_start, size);
    cache_ll_l1_enable_bus(1, bus_mask);
 #endif
@ -602,9 +602,9 @@ FORCE_INLINE_ATTR void s_unmapping_operation(uint32_t vaddr_start, uint32_t size
 {
    mmu_hal_unmap_region(0, vaddr_start, size);
 #if (SOC_MMU_PERIPH_NUM == 2)
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    mmu_hal_unmap_region(1, vaddr_start, size);
-#endif //  #if !CONFIG_FREERTOS_UNICORE
+#endif //  #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 #endif //  #if (SOC_MMU_PERIPH_NUM == 2)
 }
 #endif
--- a/components/esp_psram/esp32/esp_psram_extram_cache.c
+++ b/components/esp_psram/esp32/esp_psram_extram_cache.c
@ -9,7 +9,7 @@
 #include "esp_psram.h"
 #include "esp_private/esp_psram_extram.h"

-#if CONFIG_FREERTOS_UNICORE
+#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 #define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
 #else
 #define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH
@ -38,7 +38,7 @@ void IRAM_ATTR esp_psram_extram_writeback_cache(void)
        cache_was_disabled |= (1 << 0);
        DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S);
    }
-#ifndef CONFIG_FREERTOS_UNICORE
+#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    if (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE) == 0) {
        cache_was_disabled |= (1 << 1);
        DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S);
@ -70,7 +70,7 @@ void IRAM_ATTR esp_psram_extram_writeback_cache(void)
        while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) ;
        DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S);
    }
-#ifndef CONFIG_FREERTOS_UNICORE
+#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    if (cache_was_disabled & (1 << 1)) {
        while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1);
        DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S);
--- a/components/esp_psram/esp32/esp_psram_impl_quad.c
+++ b/components/esp_psram/esp32/esp_psram_impl_quad.c
@ -201,7 +201,7 @@ typedef enum {
    PSRAM_VADDR_MODE_EVENODD,    ///< App and pro CPU share external RAM caches: pro CPU does even 32yte ranges, app does odd ones.
 } psram_vaddr_mode_t;

-#if CONFIG_FREERTOS_UNICORE
+#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 #define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
 #else
 #define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH
--- a/components/esp_psram/esp32s2/esp_psram_impl_quad.c
+++ b/components/esp_psram/esp32s2/esp_psram_impl_quad.c
@ -531,7 +531,7 @@ static void IRAM_ATTR psram_cache_init(psram_cache_speed_t psram_cache_mode, psr
    SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy,
                      SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); //dummy, psram cache :  40m--+1dummy,80m--+2dummy

-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL | DPORT_PRO_DRAM_SPLIT);
    DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL | DPORT_APP_DRAM_SPLIT);
    if (vaddrmode == PSRAM_VADDR_MODE_LOWHIGH) {
--- a/components/esp_psram/esp_psram.c
+++ b/components/esp_psram/esp_psram.c
@ -96,7 +96,7 @@ static void IRAM_ATTR s_mapping(int v_start, int size)
    //Enable external RAM in MMU
    cache_sram_mmu_set(0, 0, v_start, 0, 32, (size / 1024 / 32));
    //Flush and enable icache for APP CPU
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1);
    cache_sram_mmu_set(1, 0, v_start, 0, 32, (size / 1024 / 32));
 #endif
@ -126,7 +126,7 @@ esp_err_t esp_psram_init(void)
    ESP_EARLY_LOGI(TAG, "Found %dMB PSRAM device", psram_physical_size / (1024 * 1024));
    ESP_EARLY_LOGI(TAG, "Speed: %dMHz", CONFIG_SPIRAM_SPEED);
 #if CONFIG_IDF_TARGET_ESP32
-#if CONFIG_FREERTOS_UNICORE
+#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in normal (1-core) mode.");
 #else
    ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in low/high (2-core) mode.");
@ -206,7 +206,7 @@ esp_err_t esp_psram_init(void)

    cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, (uint32_t)v_start_8bit_aligned, actual_mapped_len);
    cache_ll_l1_enable_bus(0, bus_mask);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    bus_mask = cache_ll_l1_get_bus(1, (uint32_t)v_start_8bit_aligned, actual_mapped_len);
    cache_ll_l1_enable_bus(1, bus_mask);
 #endif
--- a/components/esp_psram/mmu_psram_flash.c
+++ b/components/esp_psram/mmu_psram_flash.c
@ -64,7 +64,7 @@ esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size
    //Enable the most high bus, which is used for copying FLASH .text to PSRAM
    cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, SOC_EXTRAM_DATA_HIGH, 0);
    cache_ll_l1_enable_bus(0, bus_mask);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    bus_mask = cache_ll_l1_get_bus(1, SOC_EXTRAM_DATA_HIGH, 0);
    cache_ll_l1_enable_bus(1, bus_mask);
 #endif
@ -108,7 +108,7 @@ esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_si
    //Enable the most high bus, which is used for copying FLASH .text to PSRAM
    cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, SOC_EXTRAM_DATA_HIGH, 0);
    cache_ll_l1_enable_bus(0, bus_mask);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    bus_mask = cache_ll_l1_get_bus(1, SOC_EXTRAM_DATA_HIGH, 0);
    cache_ll_l1_enable_bus(1, bus_mask);
 #endif
--- a/components/esp_rom/patches/esp_rom_sys.c
+++ b/components/esp_rom/patches/esp_rom_sys.c
@ -44,7 +44,7 @@ IRAM_ATTR void esp_rom_install_uart_printf(void)
 #if CONFIG_IDF_TARGET_ESP32
 extern uint32_t g_ticks_per_us_pro;
 #if SOC_CPU_CORES_NUM > 1
-#ifndef CONFIG_FREERTOS_UNICORE
+#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 extern uint32_t g_ticks_per_us_app;
 #endif
 #endif
@ -53,7 +53,7 @@ IRAM_ATTR void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us)
    /* Update scale factors used by esp_rom_delay_us */
    g_ticks_per_us_pro = ticks_per_us;
 #if SOC_CPU_CORES_NUM > 1
-#ifndef CONFIG_FREERTOS_UNICORE
+#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    g_ticks_per_us_app = ticks_per_us;
 #endif
 #endif
--- a/components/esp_system/Kconfig
+++ b/components/esp_system/Kconfig
@ -92,7 +92,7 @@ menu "ESP System Settings"

    config ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
        bool
-        default y if IDF_TARGET_ESP32 && FREERTOS_UNICORE
+        default y if IDF_TARGET_ESP32 && ESP_SYSTEM_SINGLE_CORE_MODE
        default y if IDF_TARGET_ESP32S2
        default y if IDF_TARGET_ESP32C3
        default y if IDF_TARGET_ESP32S3
@ -590,7 +590,7 @@ menu "IPC (Inter-Processor Call)"

    config ESP_IPC_ISR_ENABLE
        bool
-        default y if !FREERTOS_UNICORE
+        default y if !ESP_SYSTEM_SINGLE_CORE_MODE
        help
            The IPC ISR feature is similar to the IPC feature except that the callback function is executed in the
            context of a High Priority Interrupt. The IPC ISR feature is intended for low latency execution of simple
--- a/components/esp_system/port/esp_system_chip.c
+++ b/components/esp_system/port/esp_system_chip.c
@ -51,7 +51,7 @@ void IRAM_ATTR esp_restart_noos_dig(void)
    // esp_restart_noos_dig() will generates a core reset, which does not reset the
    // registers of the RTC domain, so the CPU's stall state remains after the reset,
    // we need to release them here
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    // unstall all other cores
    int core_id = esp_cpu_get_core_id();
    for (uint32_t i = 0; i < SOC_CPU_CORES_NUM; i++) {
--- a/components/esp_system/port/soc/esp32/Kconfig.memory
+++ b/components/esp_system/port/soc/esp32/Kconfig.memory
@ -3,11 +3,11 @@ menu "Memory"
    config ESP32_RTCDATA_IN_FAST_MEM
        bool "Place RTC_DATA_ATTR and RTC_RODATA_ATTR variables into RTC fast memory segment"
        default n
-        depends on FREERTOS_UNICORE
+        depends on ESP_SYSTEM_SINGLE_CORE_MODE
        help
            This option allows to place .rtc_data and .rtc_rodata sections into
            RTC fast memory segment to free the slow memory region for ULP programs.
-            This option depends on the CONFIG_FREERTOS_UNICORE option because RTC fast memory
+            This option depends on the CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE option because RTC fast memory
            can be accessed only by PRO_CPU core.

    config ESP32_USE_FIXED_STATIC_RAM_SIZE
@ -33,7 +33,7 @@ menu "Memory"

    config ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
        bool "Enable IRAM as 8 bit accessible memory"
-        depends on FREERTOS_UNICORE
+        depends on ESP_SYSTEM_SINGLE_CORE_MODE
        help
            If enabled, application can use IRAM as byte accessible region for storing data
            (Note: IRAM region cannot be used as task stack)
--- a/components/esp_system/port/soc/esp32/Kconfig.system
+++ b/components/esp_system/port/soc/esp32/Kconfig.system
@ -66,4 +66,4 @@ config ESP32_DISABLE_BASIC_ROM_CONSOLE
 config ESP32_ECO3_CACHE_LOCK_FIX
    bool
    default y
-    depends on !FREERTOS_UNICORE && SPIRAM
+    depends on !ESP_SYSTEM_SINGLE_CORE_MODE && SPIRAM
--- a/components/esp_system/port/soc/esp32/Kconfig.tracemem
+++ b/components/esp_system/port/soc/esp32/Kconfig.tracemem
@ -21,7 +21,7 @@ menu "Trace memory"
    config ESP32_TRAX_TWOBANKS
        bool "Reserve memory for tracing both pro as well as app cpu execution"
        default "n"
-        depends on ESP32_TRAX && !FREERTOS_UNICORE
+        depends on ESP32_TRAX && !ESP_SYSTEM_SINGLE_CORE_MODE
        select ESP32_MEMMAP_TRACEMEM_TWOBANKS
        help
            The ESP32 contains a feature which allows you to trace the execution path the processor
--- a/components/esp_system/port/soc/esp32/clk.c
+++ b/components/esp_system/port/soc/esp32/clk.c
@ -199,14 +199,14 @@ __attribute__((weak)) void esp_perip_clk_init(void)
    uint32_t hwcrypto_perip_clk;
    uint32_t wifi_bt_sdio_clk;

-#if CONFIG_FREERTOS_UNICORE
+#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    soc_reset_reason_t rst_reas[1];
 #else
    soc_reset_reason_t rst_reas[2];
 #endif

    rst_reas[0] = esp_rom_get_reset_reason(0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    rst_reas[1] = esp_rom_get_reset_reason(1);
 #endif

@ -214,7 +214,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
     * that have been enabled before reset.
     */
    if ((rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_SW || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT)
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
        || (rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_SW || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT)
 #endif
    ) {
--- a/components/esp_system/port/soc/esp32/highint_hdl.S
+++ b/components/esp_system/port/soc/esp32/highint_hdl.S
@ -163,7 +163,7 @@ _lx_intr_livelock_pro:
    .align      4
 xt_highintx:

-#ifndef CONFIG_FREERTOS_UNICORE
+#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    /* See if we're here for the IPC_ISR interrupt */
    rsr     a0, INTERRUPT
    extui   a0, a0, ETS_IPC_ISR_INUM, 1
@ -176,7 +176,7 @@ xt_highintx:
    movi    a0, esp_ipc_isr_handler
    jx      a0
 1:
-#endif /* not CONFIG_FREERTOS_UNICORE */
+#endif /* not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE */

 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_ESP_INT_WDT

--- a/components/esp_system/port/soc/esp32p4/system_internal.c
+++ b/components/esp_system/port/soc/esp32p4/system_internal.c
@ -84,7 +84,7 @@ void IRAM_ATTR esp_restart_noos(void)
    wdt_hal_write_protect_enable(&rtc_wdt_ctx);

    const uint32_t core_id = esp_cpu_get_core_id();
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
    esp_cpu_reset(other_core_id);
    esp_cpu_stall(other_core_id);
@ -111,7 +111,7 @@ void IRAM_ATTR esp_restart_noos(void)
    rtc_clk_cpu_freq_set_xtal();
 #endif

-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    // clear entry point for APP CPU
    ets_set_appcpu_boot_addr(0);
 #endif
@ -125,12 +125,12 @@ void IRAM_ATTR esp_restart_noos(void)
    // Reset CPUs
    if (core_id == 0) {
        // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
        esp_cpu_reset(1);
 #endif
        esp_cpu_reset(0);
    }
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    else {
        // Running on APP CPU: need to reset PRO CPU and unstall it,
        // then reset APP CPU
--- a/components/esp_system/port/soc/esp32s3/Kconfig.tracemem
+++ b/components/esp_system/port/soc/esp32s3/Kconfig.tracemem
@ -21,7 +21,7 @@ menu "Trace memory"
    config ESP32S3_TRAX_TWOBANKS
        bool "Reserve memory for tracing both pro as well as app cpu execution"
        default "n"
-        depends on ESP32S3_TRAX && !FREERTOS_UNICORE
+        depends on ESP32S3_TRAX && !ESP_SYSTEM_SINGLE_CORE_MODE
        select ESP32S3_MEMMAP_TRACEMEM_TWOBANKS
        help
            The esp32-s3 contains a feature which allows you to trace the execution path the processor
--- a/components/esp_system/port/soc/esp32s3/clk.c
+++ b/components/esp_system/port/soc/esp32s3/clk.c
@ -197,14 +197,14 @@ __attribute__((weak)) void esp_perip_clk_init(void)
    uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
    uint32_t common_perip_clk1 = 0;

-#if CONFIG_FREERTOS_UNICORE
+#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    soc_reset_reason_t rst_reas[1];
 #else
    soc_reset_reason_t rst_reas[2];
 #endif

    rst_reas[0] = esp_rom_get_reset_reason(0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    rst_reas[1] = esp_rom_get_reset_reason(1);
 #endif

@ -213,7 +213,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
     */
    if ((rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_SW ||
            rst_reas[0] == RESET_REASON_CPU0_RTC_WDT || rst_reas[0] == RESET_REASON_CPU0_MWDT1)
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
        || (rst_reas[1] == RESET_REASON_CPU1_MWDT0 || rst_reas[1] == RESET_REASON_CPU1_SW ||
            rst_reas[1] == RESET_REASON_CPU1_RTC_WDT || rst_reas[1] == RESET_REASON_CPU1_MWDT1)
 #endif
--- a/components/esp_system/port/soc/esp32s3/highint_hdl.S
+++ b/components/esp_system/port/soc/esp32s3/highint_hdl.S
@ -37,12 +37,12 @@ _l4_intr_stack:
    .align      4
 xt_highint4:

-#ifndef CONFIG_FREERTOS_UNICORE
+#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    /* See if we're here for the IPC_ISR interrupt */
    rsr     a0, INTERRUPT
    extui   a0, a0, ETS_IPC_ISR_INUM, 1
    bnez    a0, jump_to_esp_ipc_isr_handler
-#endif // not CONFIG_FREERTOS_UNICORE
+#endif // not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

    /* Allocate exception frame and save minimal context. */
    mov     a0, sp
--- a/components/esp_system/port/soc/esp32s3/system_internal.c
+++ b/components/esp_system/port/soc/esp32s3/system_internal.c
@ -112,7 +112,7 @@ void IRAM_ATTR esp_restart_noos(void)
    // instruction. This would cause memory pool to be locked by arbiter
    // to the stalled CPU, preventing current CPU from accessing this pool.
    const uint32_t core_id = esp_cpu_get_core_id();
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
    esp_rom_software_reset_cpu(other_core_id);
    esp_cpu_stall(other_core_id);
@ -135,7 +135,7 @@ void IRAM_ATTR esp_restart_noos(void)
    rtc_clk_cpu_set_to_default_config();
 #endif

-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    // Clear entry point for APP CPU
    REG_WRITE(SYSTEM_CORE_1_CONTROL_1_REG, 0);
 #endif
@ -143,12 +143,12 @@ void IRAM_ATTR esp_restart_noos(void)
    // Reset CPUs
    if (core_id == 0) {
        // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
        esp_rom_software_reset_cpu(1);
 #endif
        esp_rom_software_reset_cpu(0);
    }
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    else {
        // Running on APP CPU: need to reset PRO CPU and unstall it,
        // then reset APP CPU
--- a/components/esp_system/task_wdt/task_wdt.c
+++ b/components/esp_system/task_wdt/task_wdt.c
@ -386,7 +386,7 @@ static void task_wdt_timeout_handling(int cores_fail, bool panic)
    const int current_core = xPortGetCoreID();

    if (panic) {
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
        const int other_core = !current_core;

        if ((cores_fail & BIT(0)) && (cores_fail & BIT(1))) {
@ -404,7 +404,7 @@ static void task_wdt_timeout_handling(int cores_fail, bool panic)
            esp_crosscore_int_send_twdt_abort(other_core);
            while (1) {}
        }
-#endif // !CONFIG_FREERTOS_UNICORE
+#endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
        /* Current core is failing, abort right now */
        task_wdt_timeout_abort(true);
    } else {
@ -413,13 +413,13 @@ static void task_wdt_timeout_handling(int cores_fail, bool panic)
            ESP_EARLY_LOGE(TAG, "Print CPU %d (current core) backtrace", current_core);
            esp_backtrace_print(100);
        }
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
        const int other_core = !current_core;
        if (cores_fail & BIT(other_core)) {
            ESP_EARLY_LOGE(TAG, "Print CPU %d backtrace", other_core);
            esp_crosscore_int_send_print_backtrace(other_core);
        }
-#endif // !CONFIG_FREERTOS_UNICORE
+#endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    }
 }

--- a/components/hal/cache_hal.c
+++ b/components/hal/cache_hal.c
@ -67,7 +67,7 @@ void cache_hal_init(void)

    cache_ll_l1_enable_bus(0, CACHE_LL_DEFAULT_DBUS_MASK);
    cache_ll_l1_enable_bus(0, CACHE_LL_DEFAULT_IBUS_MASK);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    cache_ll_l1_enable_bus(1, CACHE_LL_DEFAULT_DBUS_MASK);
    cache_ll_l1_enable_bus(1, CACHE_LL_DEFAULT_IBUS_MASK);
 #endif
--- a/components/hal/esp32/cache_hal_esp32.c
+++ b/components/hal/esp32/cache_hal_esp32.c
@ -18,7 +18,7 @@ void cache_hal_suspend(uint32_t cache_level, cache_type_t type)
 {
    s_cache_status[0] = cache_ll_l1_get_enabled_bus(0);
    cache_ll_l1_disable_cache(0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    s_cache_status[1] = cache_ll_l1_get_enabled_bus(1);
    cache_ll_l1_disable_cache(1);
 #endif
@ -29,7 +29,7 @@ void cache_hal_resume(uint32_t cache_level, cache_type_t type)
 {
    cache_ll_l1_enable_cache(0);
    cache_ll_l1_enable_bus(0, s_cache_status[0]);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    cache_ll_l1_enable_cache(1);
    cache_ll_l1_enable_bus(1, s_cache_status[1]);
 #endif
@ -39,7 +39,7 @@ void cache_hal_resume(uint32_t cache_level, cache_type_t type)
 bool cache_hal_is_cache_enabled(uint32_t cache_level, cache_type_t type)
 {
    bool result = cache_ll_l1_is_cache_enabled(0, CACHE_TYPE_ALL);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    result = result && cache_ll_l1_is_cache_enabled(1, CACHE_TYPE_ALL);
 #endif
    return result;
--- a/components/hal/mmu_hal.c
+++ b/components/hal/mmu_hal.c
@ -31,7 +31,7 @@ void mmu_hal_unmap_all(void)
    mmu_ll_unmap_all(MMU_LL_PSRAM_MMU_ID);
 #else
    mmu_ll_unmap_all(0);
-#if !CONFIG_FREERTOS_UNICORE
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    mmu_ll_unmap_all(1);
 #endif
 #endif
--- a/components/heap/include/heap_trace.inc
+++ b/components/heap/include/heap_trace.inc
@ -22,7 +22,7 @@
 inline static uint32_t get_ccount(void)
 {
    uint32_t ccount = esp_cpu_get_cycle_count() & ~3;
-#ifndef CONFIG_FREERTOS_UNICORE
+#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
    ccount |= xPortGetCoreID();
 #endif
    return ccount;
--- a/components/heap/port/esp32/memory_layout.c
+++ b/components/heap/port/esp32/memory_layout.c
@ -126,7 +126,7 @@ const size_t soc_memory_region_count = sizeof(soc_memory_regions)/sizeof(soc_mem
   These are removed from the soc_memory_regions array when heaps are created.
 */
 SOC_RESERVE_MEMORY_REGION(SOC_CACHE_PRO_LOW, SOC_CACHE_PRO_HIGH, cpu0_cache);
-#ifndef CONFIG_FREERTOS_UNICORE
+#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 SOC_RESERVE_MEMORY_REGION(SOC_CACHE_APP_LOW, SOC_CACHE_APP_HIGH, cpu1_cache);
 #endif

@ -147,7 +147,7 @@ SOC_RESERVE_MEMORY_REGION(SOC_CACHE_APP_LOW, SOC_CACHE_APP_HIGH, cpu1_cache);
    */

 SOC_RESERVE_MEMORY_REGION(0x3ffe0000, 0x3ffe0440, rom_pro_data); //Reserve ROM PRO data region
-#ifndef CONFIG_FREERTOS_UNICORE
+#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 SOC_RESERVE_MEMORY_REGION(0x3ffe3f20, 0x3ffe4350, rom_app_data); //Reserve ROM APP data region
 #endif

--- a/components/soc/esp32/dport_access.c
+++ b/components/soc/esp32/dport_access.c
@ -12,7 +12,7 @@

 IRAM_ATTR uint32_t esp_dport_access_reg_read(uint32_t reg)
 {
-#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !SOC_DPORT_WORKAROUND
+#if defined(BOOTLOADER_BUILD) || defined(CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) || !SOC_DPORT_WORKAROUND
    return _DPORT_REG_READ(reg);
 #else
    uint32_t apb;
@ -34,7 +34,7 @@ IRAM_ATTR uint32_t esp_dport_access_reg_read(uint32_t reg)

 IRAM_ATTR uint32_t esp_dport_access_sequence_reg_read(uint32_t reg)
 {
-#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !SOC_DPORT_WORKAROUND
+#if defined(BOOTLOADER_BUILD) || defined(CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) || !SOC_DPORT_WORKAROUND
    return _DPORT_REG_READ(reg);
 #else
    uint32_t apb;
--- a/components/soc/esp32/include/soc/dport_access.h
+++ b/components/soc/esp32/include/soc/dport_access.h
@ -107,7 +107,7 @@ uint32_t esp_dport_access_sequence_reg_read(uint32_t reg);
 */
 void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words);

-#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !SOC_DPORT_WORKAROUND
+#if defined(BOOTLOADER_BUILD) || defined(CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) || !SOC_DPORT_WORKAROUND
    #define DPORT_INTERRUPT_DISABLE()
    #define DPORT_INTERRUPT_RESTORE()
    #define DPORT_REG_READ(reg)          _DPORT_REG_READ(reg)
@ -128,7 +128,7 @@ void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t
                __asm__ __volatile__("wsr.ps %0 ; rsync\n" \
                                    : : "a" (__tmp) : "memory" ); \
                }while(0)
-#endif // defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !SOC_DPORT_WORKAROUND
+#endif // defined(BOOTLOADER_BUILD) || defined(CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE) || !SOC_DPORT_WORKAROUND

 //get bit or get bits from register
 #define DPORT_REG_GET_BIT(_r, _b)  (DPORT_REG_READ(_r) & (_b))
--- a/components/soc/esp32/include/soc/soc.h
+++ b/components/soc/esp32/include/soc/soc.h
@ -31,7 +31,7 @@

 #define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)

-#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && SOC_DPORT_WORKAROUND
+#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE ) && SOC_DPORT_WORKAROUND
 #define ASSERT_IF_DPORT_REG(_r, OP)  TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP));
 #else
 #define ASSERT_IF_DPORT_REG(_r, OP)
--- a/docs/en/api-guides/app_trace.rst
+++ b/docs/en/api-guides/app_trace.rst
@ -420,7 +420,7 @@ Data Visualization

 After trace data are collected, users can use a special tool to visualize the results and inspect behavior of the program.

-.. only:: not CONFIG_FREERTOS_UNICORE
+.. only:: not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

    Unfortunately, SystemView does not support tracing from multiple cores. So when tracing from {IDF_TARGET_NAME} with JTAG interfaces in the dual-core mode, two files are generated: one for PRO CPU and another for APP CPU. Users can load each file into separate instances of the tool. For tracing over UART, users can select ``Component config`` > ``Application Level Tracing`` > ``FreeRTOS SystemView Tracing`` in menuconfig Pro or App to choose which CPU has to be traced.

@ -432,7 +432,7 @@ Good instructions on how to install, configure, and visualize data in Impulse fr

    ESP-IDF uses its own mapping for SystemView FreeRTOS events IDs, so users need to replace the original file mapping ``$SYSVIEW_INSTALL_DIR/Description/SYSVIEW_FreeRTOS.txt`` with ``$IDF_PATH/tools/esp_app_trace/SYSVIEW_FreeRTOS.txt``. Also, contents of that ESP-IDF-specific file should be used when configuring SystemView serializer using the above link.

-.. only:: not CONFIG_FREERTOS_UNICORE
+.. only:: not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

    Configure Impulse for Dual Core Traces
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--- a/docs/en/api-guides/deep-sleep-stub.rst
+++ b/docs/en/api-guides/deep-sleep-stub.rst
@ -78,7 +78,7 @@ The first way is to use the ``RTC_DATA_ATTR`` and ``RTC_RODATA_ATTR`` to specify

 .. only:: SOC_RTC_SLOW_MEM_SUPPORTED

-    The RTC memory area where this data will be placed can be configured via menuconfig option named ``CONFIG_{IDF_TARGET_CFG_PREFIX}_RTCDATA_IN_FAST_MEM``. This option allows to keep slow memory area for ULP programs and once it is enabled the data marked with ``RTC_DATA_ATTR`` and ``RTC_RODATA_ATTR`` are placed in the RTC fast memory segment otherwise it goes to RTC slow memory (default option). This option depends on the ``CONFIG_FREERTOS_UNICORE`` because RTC fast memory can be accessed only by PRO_CPU.
+    The RTC memory area where this data will be placed can be configured via menuconfig option named ``CONFIG_{IDF_TARGET_CFG_PREFIX}_RTCDATA_IN_FAST_MEM``. This option allows to keep slow memory area for ULP programs and once it is enabled the data marked with ``RTC_DATA_ATTR`` and ``RTC_RODATA_ATTR`` are placed in the RTC fast memory segment otherwise it goes to RTC slow memory (default option). This option depends on the ``CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE`` because RTC fast memory can be accessed only by PRO_CPU.

    The attributes ``RTC_FAST_ATTR`` and ``RTC_SLOW_ATTR`` can be used to specify data that will be force placed into RTC_FAST and RTC_SLOW memory respectively. Any access to data marked with ``RTC_FAST_ATTR`` is allowed by PRO_CPU only and it is responsibility of user to make sure about it.

--- a/docs/en/api-guides/memory-types.rst
+++ b/docs/en/api-guides/memory-types.rst
@ -175,7 +175,7 @@ The ``DRAM_ATTR`` attribute can be used to force constants from DROM into the :r

    .. only:: esp32

-        In single core mode (:ref:`CONFIG_FREERTOS_UNICORE`), remaining RTC FAST memory is added to the heap, unless the option :ref:`CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP` is disabled. This memory can be used interchangeably with :ref:`DRAM`, but is slightly slower to access and not DMA-capable.
+        In single core mode (:ref:`CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE`), remaining RTC FAST memory is added to the heap, unless the option :ref:`CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP` is disabled. This memory can be used interchangeably with :ref:`DRAM`, but is slightly slower to access and not DMA-capable.

        This option is not available in dual core mode, because on {IDF_TARGET_NAME}, RTC FAST memory can only be accessed by the PRO CPU.

--- a/docs/en/api-guides/performance/speed.rst
+++ b/docs/en/api-guides/performance/speed.rst
@ -54,7 +54,7 @@ Executing the target multiple times can help average out factors, e.g., RTOS con
 - It is also possible to use the standard Unix ``gettimeofday()`` and ``utime()`` functions, although the overhead is slightly higher.
 - Otherwise, including ``hal/cpu_hal.h`` and calling the HAL function ``cpu_hal_get_cycle_count()`` returns the number of CPU cycles executed. This function has lower overhead than the others, which is good for measuring very short execution times with high precision.

-  .. only:: not CONFIG_FREERTOS_UNICORE
+  .. only:: not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

      The CPU cycles are counted per-core, so only use this method from an interrupt handler, or a task that is pinned to a single core.

--- a/docs/en/api-guides/startup.rst
+++ b/docs/en/api-guides/startup.rst
@ -22,11 +22,11 @@ This process is explained in detail in the following sections.
 First Stage Bootloader
 ^^^^^^^^^^^^^^^^^^^^^^

-.. only:: not CONFIG_FREERTOS_UNICORE
+.. only:: not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

    After SoC reset, PRO CPU will start running immediately, executing reset vector code, while APP CPU will be held in reset. During startup process, PRO CPU does all the initialization. APP CPU reset is de-asserted in the ``call_start_cpu0`` function of application startup code. Reset vector code is located in the mask ROM of the {IDF_TARGET_NAME} chip and cannot be modified.

-.. only:: CONFIG_FREERTOS_UNICORE
+.. only:: CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

    After SoC reset, the CPU will start running immediately to perform initialization. The reset vector code is located in the mask ROM of the {IDF_TARGET_NAME} chip and cannot be modified.

@ -76,7 +76,7 @@ For the selected partition, second stage bootloader reads the binary image from
 - For segments with load addresses in internal :ref:`iram` or :ref:`dram`, the contents are copied from flash to the load address.
 - For segments which have load addresses in :ref:`drom` or :ref:`irom` regions, the flash MMU is configured to provide the correct mapping from the flash to the load address.

-.. only:: not CONFIG_FREERTOS_UNICORE
+.. only:: not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

    Note that the second stage bootloader configures flash MMU for both PRO and APP CPUs, but it only enables flash MMU for PRO CPU. Reason for this is that second stage bootloader code is loaded into the memory region used by APP CPU cache. The duty of enabling cache for APP CPU is passed on to the application.

@ -114,13 +114,13 @@ This port-layer initialization function initializes the basic C Runtime Environm
   - Set the CPU clocks to the frequencies configured for the project.
   :CONFIG_ESP_SYSTEM_MEMPROT_FEATURE: - Initialize memory protection if configured.
   :esp32: - Reconfigure the main SPI flash based on the app header settings (necessary for compatibility with bootloader versions before ESP-IDF V4.0, see :ref:`bootloader-compatibility`).
-   :not CONFIG_FREERTOS_UNICORE: - If the app is configured to run on multiple cores, start the other core and wait for it to initialize as well (inside the similar "port layer" initialization function ``call_start_cpu1``).
+   :not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE: - If the app is configured to run on multiple cores, start the other core and wait for it to initialize as well (inside the similar "port layer" initialization function ``call_start_cpu1``).

-.. only:: not CONFIG_FREERTOS_UNICORE
+.. only:: not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

    Once ``call_start_cpu0`` completes running, it calls the "system layer" initialization function ``start_cpu0`` found in :idf_file:`components/esp_system/startup.c`. Other cores will also complete port-layer initialization and call ``start_other_cores`` found in the same file.

-.. only:: CONFIG_FREERTOS_UNICORE
+.. only:: CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

    Once ``call_start_cpu0`` completes running, it calls the "system layer" initialization function ``start_cpu0`` found in :idf_file:`components/esp_system/startup.c`.

@ -156,13 +156,13 @@ After doing some more initialization tasks (that require the scheduler to have s

 The main task that runs ``app_main`` has a fixed RTOS priority (one higher than the minimum) and a :ref:`configurable stack size <CONFIG_ESP_MAIN_TASK_STACK_SIZE>`.

-.. only:: not CONFIG_FREERTOS_UNICORE
+.. only:: not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

   The main task core affinity is also configurable: :ref:`CONFIG_ESP_MAIN_TASK_AFFINITY`.

 Unlike normal FreeRTOS tasks (or embedded C ``main`` functions), the ``app_main`` task is allowed to return. If this happens, The task is cleaned up and the system will continue running with other RTOS tasks scheduled normally. Therefore, it is possible to implement ``app_main`` as either a function that creates other application tasks and then returns, or as a main application task itself.

-.. only:: not CONFIG_FREERTOS_UNICORE
+.. only:: not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

    Second Core Startup
    -------------------
--- a/docs/en/api-reference/peripherals/spi_flash/index.rst
+++ b/docs/en/api-reference/peripherals/spi_flash/index.rst
@ -251,7 +251,7 @@ Once the flash operation is complete, the function on CPU A sets another flag, `

 Additionally, all API functions are protected with a mutex (``s_flash_op_mutex``).

-In a single core environment (:ref:`CONFIG_FREERTOS_UNICORE` enabled), you need to disable both caches, so that no inter-CPU communication can take place.
+In a single core environment (:ref:`CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE` enabled), you need to disable both caches, so that no inter-CPU communication can take place.

 Related Documents
 ------------------
--- a/docs/en/api-reference/system/intr_alloc.rst
+++ b/docs/en/api-reference/system/intr_alloc.rst
@ -143,7 +143,7 @@ If you have confirmed that the application is indeed running out of interrupts,

 .. list::

-    :not CONFIG_FREERTOS_UNICORE: - On multi-core SoCs, try initializing some of the peripheral drivers from a task pinned to the second core. Interrupts are typically allocated on the same core where the peripheral driver initialization function runs. Therefore by running the initialization function on the second core, more interrupt inputs can be used.
+    :not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE: - On multi-core SoCs, try initializing some of the peripheral drivers from a task pinned to the second core. Interrupts are typically allocated on the same core where the peripheral driver initialization function runs. Therefore by running the initialization function on the second core, more interrupt inputs can be used.
    - Determine the interrupts which can tolerate higher latency, and allocate them using ``ESP_INTR_FLAG_SHARED`` flag (optionally ORed with ``ESP_INTR_FLAG_LOWMED``). Using this flag for two or more peripherals will let them use a single interrupt input, and therefore save interrupt inputs for other peripherals. See :ref:`intr-alloc-shared-interrupts` above.
    :not SOC_CPU_HAS_FLEXIBLE_INTC: - Some peripheral driver may default to allocating interrupts with ``ESP_INTR_FLAG_LEVEL1`` flag, so priority 2 and 3 interrupts do not get used by default. If :cpp:func:`esp_intr_dump` shows that some priority 2 or 3 interrupts are available, try changing the interrupt allocation flags when initializing the driver to ``ESP_INTR_FLAG_LEVEL2`` or ``ESP_INTR_FLAG_LEVEL3``.
    - Check if some of the peripheral drivers do not need to be used all the time, and initialize or deinitialize them on demand. This can reduce the number of simultaneously allocated interrupts.
--- a/docs/zh_CN/api-guides/app_trace.rst
+++ b/docs/zh_CN/api-guides/app_trace.rst
@ -420,7 +420,7 @@ Start 子命令语法：

 收集到跟踪数据后，用户可以使用特殊的工具对结果进行可视化并分析程序行为。

-.. only:: not CONFIG_FREERTOS_UNICORE
+.. only:: not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

    遗憾的是，SystemView 不支持从多个核心进行跟踪。所以当使用 JTAG 追踪双核模式下的 {IDF_TARGET_NAME} 时会生成两个文件：一个用于 PRO CPU，另一个用于 APP CPU。用户可以将每个文件加载到工具中单独分析。使用 UART 进行追踪时，用户可以在 menuconfig Pro 或 App 中点击 ``Component config`` > ``Application Level Tracing`` > ``FreeRTOS SystemView Tracing`` 并选择要追踪的 CPU。

@ -432,7 +432,7 @@ Start 子命令语法：

    ESP-IDF 使用自己的 SystemView FreeRTOS 事件 ID 映射，因此用户需要将 ``$SYSVIEW_INSTALL_DIR/Description/SYSVIEW_FreeRTOS.txt`` 替换成 ``$IDF_PATH/tools/esp_app_trace/SYSVIEW_FreeRTOS.txt``。在使用上述链接配置 SystemView 序列化程序时，也应该使用该特定文件的内容。

-.. only:: not CONFIG_FREERTOS_UNICORE
+.. only:: not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

    配置 Impulse 实现双核跟踪
    ~~~~~~~~~~~~~~~~~~~~~~~~~
--- a/docs/zh_CN/api-guides/memory-types.rst
+++ b/docs/zh_CN/api-guides/memory-types.rst
@ -175,7 +175,7 @@ DROM（数据存储在 flash 中）

    .. only:: esp32

-        在单核模式下 (:ref:`CONFIG_FREERTOS_UNICORE`)，除非禁用 :ref:`CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP` 选项，否则剩余的 RTC FAST memory 会被添加到堆中。该部分内存可以和 :ref:`DRAM` 互换使用，但是访问速度稍慢，且不具备 DMA 功能。
+        在单核模式下 (:ref:`CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE`)，除非禁用 :ref:`CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP` 选项，否则剩余的 RTC FAST memory 会被添加到堆中。该部分内存可以和 :ref:`DRAM` 互换使用，但是访问速度稍慢，且不具备 DMA 功能。

        :ref:`CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP` 选项在双核模式下不可用，因为 {IDF_TARGET_NAME} 的 RTC FAST memory 只能由 PRO CPU 访问。

--- a/docs/zh_CN/api-guides/performance/speed.rst
+++ b/docs/zh_CN/api-guides/performance/speed.rst
@ -54,7 +54,7 @@
 - 也可以使用标准 Unix 函数 ``gettimeofday()`` 和 ``utime()`` 来进行计时测量，尽管其开销略高一些。
 - 此外，代码中包含 ``hal/cpu_hal.h`` 头文件，并调用 HAL 函数 ``cpu_hal_get_cycle_count()`` 可以返回已执行的 CPU 循环数。该函数开销较低，适用于高精度测量执行时间极短的代码。

-  .. only:: not CONFIG_FREERTOS_UNICORE
+  .. only:: not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

      CPU 周期是各核心独立计数的，因此本方法仅适用于测量中断处理程序或固定在单个核心上的任务。

--- a/docs/zh_CN/api-guides/startup.rst
+++ b/docs/zh_CN/api-guides/startup.rst
@ -22,11 +22,11 @@
 一级引导程序
 ~~~~~~~~~~~~

-.. only:: not CONFIG_FREERTOS_UNICORE
+.. only:: not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

   SoC 复位后，PRO CPU 会立即开始运行，执行复位向量代码，而 APP CPU 仍然保持复位状态。在启动过程中，PRO CPU 会执行所有的初始化操作。APP CPU 的复位状态会在应用程序启动代码的 ``call_start_cpu0`` 函数中失效。复位向量代码位于 {IDF_TARGET_NAME} 芯片掩膜 ROM 处，且不能被修改。

-.. only:: CONFIG_FREERTOS_UNICORE
+.. only:: CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

   SoC 复位后，CPU 会立即开始运行，执行所有的初始化操作。复位向量代码位于 {IDF_TARGET_NAME} 芯片掩膜 ROM 处，且不能被修改。

@ -76,7 +76,7 @@
 - 对于在内部 :ref:`iram` 或 :ref:`dram` 中具有加载地址的段，将把数据从 flash 复制到它们的加载地址处。
 - 对于一些加载地址位于 :ref:`drom` 或 :ref:`irom` 区域的段，通过配置 flash MMU，可为从 flash 到加载地址提供正确的映射。

-.. only:: not CONFIG_FREERTOS_UNICORE
+.. only:: not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

    请注意，二级引导程序同时为 PRO CPU 和 APP CPU 配置 flash MMU，但仅使能 PRO CPU 的 flash MMU。原因是二级引导程序代码已加载到 APP CPU 的高速缓存使用的内存区域中。因此使能 APP CPU 高速缓存的任务就交给了应用程序。

@ -114,13 +114,13 @@ ESP-IDF 应用程序的入口是 :idf_file:`components/esp_system/port/cpu_start
   - 将 CPU 时钟设置为项目配置的频率。
   :CONFIG_ESP_SYSTEM_MEMPROT_FEATURE: - 如果配置了内存保护，则初始化内存保护。
   :esp32: - 根据应用程序头部设置重新配置主 SPI flash，这是为了与 ESP-IDF V4.0 之前的引导程序版本兼容，请参考 :ref:`bootloader-compatibility`。
-   :not CONFIG_FREERTOS_UNICORE: - 如果应用程序被配置为在多个内核上运行，则启动另一个内核并等待其初始化（在类似的“端口层”初始化函数 ``call_start_cpu1`` 内）。
+   :not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE: - 如果应用程序被配置为在多个内核上运行，则启动另一个内核并等待其初始化（在类似的“端口层”初始化函数 ``call_start_cpu1`` 内）。

-.. only:: not CONFIG_FREERTOS_UNICORE
+.. only:: not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

   ``call_start_cpu0`` 完成运行后，将调用在 :idf_file:`components/esp_system/startup.c` 中找到的“系统层”初始化函数 ``start_cpu0``。其他内核也将完成端口层的初始化，并调用同一文件中的 ``start_other_cores``。

-.. only:: CONFIG_FREERTOS_UNICORE
+.. only:: CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

   ``call_start_cpu0`` 完成运行后，将调用在 :idf_file:`components/esp_system/startup.c` 中找到的“系统层”初始化函数 ``start_cpu0``。

@ -156,13 +156,13 @@ ESP-IDF 应用程序的入口是 :idf_file:`components/esp_system/port/cpu_start

 运行 ``app_main`` 的主任务有一个固定的 RTOS 优先级（比最小值高）和一个 :ref:`可配置的堆栈大小<CONFIG_ESP_MAIN_TASK_STACK_SIZE>`。

-.. only:: not CONFIG_FREERTOS_UNICORE
+.. only:: not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

   主任务的内核亲和性也是可以配置的，请参考 :ref:`CONFIG_ESP_MAIN_TASK_AFFINITY`。

 与普通的 FreeRTOS 任务（或嵌入式 C 的 ``main`` 函数）不同，``app_main`` 任务可以返回。如果``app_main`` 函数返回，那么主任务将会被删除。系统将继续运行其他的 RTOS 任务。因此可以将 ``app_main`` 实现为一个创建其他应用任务然后返回的函数，或主应用任务本身。

-.. only:: not CONFIG_FREERTOS_UNICORE
+.. only:: not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

    APP CPU 的内核启动流程
    ------------------------------------
--- a/docs/zh_CN/api-reference/peripherals/spi_flash/index.rst
+++ b/docs/zh_CN/api-reference/peripherals/spi_flash/index.rst
@ -251,7 +251,7 @@ flash 操作完成后，CPU A 上的函数将设置另一标志位，即 ``s_fla

 另外，所有 API 函数均受互斥量 ``s_flash_op_mutex`` 保护。

-在单核环境中（启用 :ref:`CONFIG_FREERTOS_UNICORE`），需要禁用上述两个 cache，以防发生 CPU 间通信。
+在单核环境中（启用 :ref:`CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE`），需要禁用上述两个 cache，以防发生 CPU 间通信。

 相关文档
 -----------------
--- a/docs/zh_CN/api-reference/system/intr_alloc.rst
+++ b/docs/zh_CN/api-reference/system/intr_alloc.rst
@ -143,7 +143,7 @@ CPU 中断在大多数 Espressif SoC 上都是有限的资源。因此，一个

 .. list::

-    :not CONFIG_FREERTOS_UNICORE: - 在多核 SoC 上，尝试通过固定在第二个核的任务来初始化某些外设驱动程序。中断通常分配在运行外设驱动程序初始化函数的同一个内核上，因此，通过在第二个内核上运行初始化函数，就可以使用更多的中断输入。
+    :not CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE: - 在多核 SoC 上，尝试通过固定在第二个核的任务来初始化某些外设驱动程序。中断通常分配在运行外设驱动程序初始化函数的同一个内核上，因此，通过在第二个内核上运行初始化函数，就可以使用更多的中断输入。
    - 找到可接受更高延迟的中断，并用 ``ESP_INTR_FLAG_SHARED`` flag （或与 ``ESP_INTR_FLAG_LOWMED`` 进行 OR 运算）分配这些中断。对两个或更多外设使用此 flag 能让它们使用单个中断输入，从而为其他外设节约中断输入。参见 :ref:`intr-alloc-shared-interrupts`。
    :not SOC_CPU_HAS_FLEXIBLE_INTC: - 一些外设驱动程序可能默认使用 ``ESP_INTR_FLAG_LEVEL1`` flag 来分配中断，因此默认情况下不会使用优先级为 2 或 3 的中断。如果 :cpp:func:`esp_intr_dump` 显示某些优先级为 2 或 3 的中断可用，尝试在初始化驱动程序时将中断分配 flag 改为 ``ESP_INTR_FLAG_LEVEL2`` 或 ``ESP_INTR_FLAG_LEVEL3``。
    - 检查是否有些外设驱动程序不需要一直启用，并按需将其初始化或取消初始化。这样可以减少同时分配的中断数量。
--- a/examples/system/app_trace_basic/pytest_app_trace_basic.py
+++ b/examples/system/app_trace_basic/pytest_app_trace_basic.py
@ -47,7 +47,7 @@ def test_examples_app_trace_basic(dut: IdfDut, openocd: OpenOcd) -> None:
    apptrace_wait_stop(dut.openocd)

    with open(openocd._logfile) as oocd_log:  # pylint: disable=protected-access
-        cores = 1 if dut.app.sdkconfig.get('FREERTOS_UNICORE') is True else 2
+        cores = 1 if dut.app.sdkconfig.get('ESP_SYSTEM_SINGLE_CORE_MODE') is True else 2
        params_str = 'App trace params: from {} cores,'.format(cores)
        found = False
        for line in oocd_log: