kopia lustrzana https://github.com/espressif/esp-idf
215 wiersze
7.3 KiB
C
215 wiersze
7.3 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_image_format.h"
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#include "flash_qio_mode.h"
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#include "soc/efuse_reg.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/io_mux_reg.h"
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#include "soc/assist_debug_reg.h"
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#include "esp_cpu.h"
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#include "soc/dport_reg.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/spi_periph.h"
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#include "soc/extmem_reg.h"
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#include "esp_rom_gpio.h"
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#include "esp_rom_efuse.h"
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#include "esp_rom_sys.h"
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#include "esp_rom_spiflash.h"
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#include "esp32s3/rom/rtc.h"
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#include "bootloader_common.h"
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#include "bootloader_init.h"
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#include "bootloader_clock.h"
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#include "bootloader_flash_config.h"
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#include "bootloader_mem.h"
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#include "bootloader_console.h"
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#include "bootloader_flash_priv.h"
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#include "bootloader_soc.h"
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#include "esp_private/bootloader_flash_internal.h"
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#include "esp_efuse.h"
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#include "hal/mmu_hal.h"
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#include "hal/cache_hal.h"
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#include "hal/rwdt_ll.h"
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#include "xtensa/config/core.h"
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#include "xt_instr_macros.h"
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static const char *TAG = "boot.esp32s3";
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static void wdt_reset_cpu0_info_enable(void)
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{
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REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG);
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REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG);
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REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_REG, 1);
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REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_RECORDING_REG, 1);
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}
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static void wdt_reset_info_dump(int cpu)
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{
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uint32_t inst = 0, pid = 0, stat = 0, data = 0, pc = 0,
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lsstat = 0, lsaddr = 0, lsdata = 0, dstat = 0;
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const char *cpu_name = cpu ? "APP" : "PRO";
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stat = 0xdeadbeef;
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pid = 0;
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if (cpu == 0) {
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inst = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_REG);
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dstat = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_REG);
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data = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_REG);
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pc = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG);
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lsstat = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_REG);
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lsaddr = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_REG);
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lsdata = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_REG);
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} else {
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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inst = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_REG);
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dstat = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_REG);
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data = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_REG);
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pc = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG);
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lsstat = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_REG);
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lsaddr = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_REG);
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lsdata = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_REG);
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#else
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ESP_LOGE(TAG, "WDT reset info: %s CPU not support!", cpu_name);
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return;
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#endif
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}
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ESP_LOGD(TAG, "WDT reset info: %s CPU STATUS 0x%08"PRIx32, cpu_name, stat);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PID 0x%08"PRIx32, cpu_name, pid);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGINST 0x%08"PRIx32, cpu_name, inst);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGSTATUS 0x%08"PRIx32, cpu_name, dstat);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGDATA 0x%08"PRIx32, cpu_name, data);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGPC 0x%08"PRIx32, cpu_name, pc);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0STAT 0x%08"PRIx32, cpu_name, lsstat);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0ADDR 0x%08"PRIx32, cpu_name, lsaddr);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0DATA 0x%08"PRIx32, cpu_name, lsdata);
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}
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static void bootloader_check_wdt_reset(void)
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{
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int wdt_rst = 0;
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soc_reset_reason_t rst_reas[2];
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rst_reas[0] = esp_rom_get_reset_reason(0);
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rst_reas[1] = esp_rom_get_reset_reason(1);
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if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0 || rst_reas[0] == RESET_REASON_CORE_MWDT1 ||
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rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT) {
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ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
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wdt_rst = 1;
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}
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if (rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0 || rst_reas[1] == RESET_REASON_CORE_MWDT1 ||
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rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT) {
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ESP_LOGW(TAG, "APP CPU has been reset by WDT.");
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wdt_rst = 1;
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}
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if (wdt_rst) {
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// if reset by WDT dump info from trace port
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wdt_reset_info_dump(0);
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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wdt_reset_info_dump(1);
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#endif
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}
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wdt_reset_cpu0_info_enable();
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}
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static void bootloader_super_wdt_auto_feed(void)
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{
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REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, RTC_CNTL_SWD_WKEY_VALUE);
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REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
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REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);
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}
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static inline void bootloader_ana_reset_config(void)
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{
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//Enable WDT, BOD, and GLITCH reset
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bootloader_ana_super_wdt_reset_config(true);
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bootloader_ana_bod_reset_config(true);
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bootloader_ana_clock_glitch_reset_config(true);
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}
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esp_err_t bootloader_init(void)
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{
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esp_err_t ret = ESP_OK;
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#if XCHAL_ERRATUM_572
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uint32_t memctl = XCHAL_CACHE_MEMCTL_DEFAULT;
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WSR(MEMCTL, memctl);
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#endif // XCHAL_ERRATUM_572
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bootloader_ana_reset_config();
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bootloader_super_wdt_auto_feed();
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// In RAM_APP, memory will be initialized in `call_start_cpu0`
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#if !CONFIG_APP_BUILD_TYPE_RAM
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// protect memory region
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bootloader_init_mem();
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/* check that static RAM is after the stack */
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#ifndef NDEBUG
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{
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assert(&_bss_start <= &_bss_end);
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assert(&_data_start <= &_data_end);
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}
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#endif
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// clear bss section
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bootloader_clear_bss_section();
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#endif // !CONFIG_APP_BUILD_TYPE_RAM
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// init eFuse virtual mode (read eFuses to RAM)
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#ifdef CONFIG_EFUSE_VIRTUAL
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ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!");
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#ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
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esp_efuse_init_virtual_mode_in_ram();
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#endif
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#endif
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// config clock
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bootloader_clock_configure();
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// initialize console, from now on, we can use esp_log
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bootloader_console_init();
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/* print 2nd bootloader banner */
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bootloader_print_banner();
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#if !CONFIG_APP_BUILD_TYPE_RAM
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//init cache hal
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cache_hal_init();
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//init mmu
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mmu_hal_init();
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// update flash ID
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bootloader_flash_update_id();
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// Check and run XMC startup flow
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if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
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ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!");
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return ret;
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}
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// read bootloader header
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if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
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return ret;
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}
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// read chip revision and check if it's compatible to bootloader
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if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
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return ret;
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}
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// initialize spi flash
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if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
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return ret;
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}
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#endif // !CONFIG_APP_BUILD_TYPE_RAM
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// check whether a WDT reset happend
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bootloader_check_wdt_reset();
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// config WDT
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bootloader_config_wdt();
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// enable RNG early entropy source
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bootloader_enable_random();
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return ret;
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}
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