kopia lustrzana https://github.com/espressif/esp-idf
340 wiersze
19 KiB
C
340 wiersze
19 KiB
C
/*
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* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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#include "esp_assert.h"
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#include "soc/soc_caps.h"
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#include "soc/interrupts.h"
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#endif
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#include "esp_bit_defs.h"
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#include "reg_base.h"
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#define PRO_CPU_NUM (0)
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#define APP_CPU_NUM (1)
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#define SOC_MAX_CONTIGUOUS_RAM_SIZE 0x400000 ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
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//Registers Operation {{
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#define ETS_UNCACHED_ADDR(addr) (addr)
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#define ETS_CACHED_ADDR(addr) (addr)
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#ifndef __ASSEMBLER__
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#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)
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#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE ) && SOC_DPORT_WORKAROUND
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#define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP));
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#else
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#define ASSERT_IF_DPORT_REG(_r, OP)
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#endif
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//write value to register
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#define REG_WRITE(_r, _v) do { \
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ASSERT_IF_DPORT_REG((_r), REG_WRITE); \
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(*(volatile uint32_t *)(_r)) = (_v); \
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} while(0)
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//read value from register
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#define REG_READ(_r) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_READ); \
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(*(volatile uint32_t *)(_r)); \
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})
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//get bit or get bits from register
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#define REG_GET_BIT(_r, _b) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); \
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(*(volatile uint32_t*)(_r) & (_b)); \
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})
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//set bit or set bits to register
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#define REG_SET_BIT(_r, _b) do { \
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ASSERT_IF_DPORT_REG((_r), REG_SET_BIT); \
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*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \
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} while(0)
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//clear bit or clear bits of register
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#define REG_CLR_BIT(_r, _b) do { \
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ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT); \
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*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \
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} while(0)
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//set bits of register controlled by mask
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#define REG_SET_BITS(_r, _b, _m) do { \
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ASSERT_IF_DPORT_REG((_r), REG_SET_BITS); \
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*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \
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} while(0)
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//get field from register, uses field _S & _V to determine mask
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#define REG_GET_FIELD(_r, _f) ({ \
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ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD); \
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((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
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})
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//set field of a register from variable, uses field _S & _V to determine mask
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#define REG_SET_FIELD(_r, _f, _v) do { \
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ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD); \
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REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \
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} while(0)
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//get field value from a variable, used when _f is not left shifted by _f##_S
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#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
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//get field value from a variable, used when _f is left shifted by _f##_S
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#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
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//set field value to a variable, used when _f is not left shifted by _f##_S
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#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
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//set field value to a variable, used when _f is left shifted by _f##_S
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#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
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//generate a value from a field value, used when _f is not left shifted by _f##_S
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#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
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//generate a value from a field value, used when _f is left shifted by _f##_S
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#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
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//read value from register
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#define READ_PERI_REG(addr) ({ \
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ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); \
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(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
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})
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//write value to register
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#define WRITE_PERI_REG(addr, val) do { \
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ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); \
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(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
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} while(0)
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//clear bits of register controlled by mask
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#define CLEAR_PERI_REG_MASK(reg, mask) do { \
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ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK); \
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WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
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} while(0)
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//set bits of register controlled by mask
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#define SET_PERI_REG_MASK(reg, mask) do { \
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ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK); \
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WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
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} while(0)
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//get bits of register controlled by mask
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#define GET_PERI_REG_MASK(reg, mask) ({ \
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ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); \
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(READ_PERI_REG(reg) & (mask)); \
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})
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//get bits of register controlled by highest bit and lowest bit
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#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
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ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS); \
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((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
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})
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//set bits of register controlled by mask and shift
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#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \
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ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS); \
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WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \
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} while(0)
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//get field of register
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#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
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ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2); \
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((READ_PERI_REG(reg)>>(shift))&(mask)); \
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})
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#endif /* !__ASSEMBLER__ */
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//}}
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//Periheral Clock {{
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#define APB_CLK_FREQ_ROM ( 26*1000000 )
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#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
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#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
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#define CPU_CLK_FREQ APB_CLK_FREQ //this may be incorrect, please refer to ESP_DEFAULT_CPU_FREQ_MHZ
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#define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz
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#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 )
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#define REF_CLK_FREQ ( 1000000 )
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#define UART_CLK_FREQ APB_CLK_FREQ
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#define WDT_CLK_FREQ APB_CLK_FREQ
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#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
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#define SPI_CLK_DIV 4
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#define TICKS_PER_US_ROM 26 // CPU is 80MHz
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#define GPIO_MATRIX_DELAY_NS 25
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//}}
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/* Overall memory map */
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#define SOC_DROM_LOW 0x3F400000
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#define SOC_DROM_HIGH 0x3F800000
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#define SOC_DRAM_LOW 0x3FFAE000
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#define SOC_DRAM_HIGH 0x40000000
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#define SOC_IROM_LOW 0x400D0000
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#define SOC_IROM_HIGH 0x40400000
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#define SOC_IROM_MASK_LOW 0x40000000
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#define SOC_IROM_MASK_HIGH 0x40070000
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#define SOC_CACHE_PRO_LOW 0x40070000
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#define SOC_CACHE_PRO_HIGH 0x40078000
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#define SOC_CACHE_APP_LOW 0x40078000
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#define SOC_CACHE_APP_HIGH 0x40080000
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#define SOC_IRAM_LOW 0x40080000
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#define SOC_IRAM_HIGH 0x400AA000
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#define SOC_RTC_IRAM_LOW 0x400C0000
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#define SOC_RTC_IRAM_HIGH 0x400C2000
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#define SOC_RTC_DRAM_LOW 0x3FF80000
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#define SOC_RTC_DRAM_HIGH 0x3FF82000
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#define SOC_RTC_DATA_LOW 0x50000000
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#define SOC_RTC_DATA_HIGH 0x50002000
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#define SOC_EXTRAM_DATA_LOW 0x3F800000
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#define SOC_EXTRAM_DATA_HIGH 0x3FC00000
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#define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW)
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//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
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#define SOC_DIRAM_IRAM_LOW 0x400A0000
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#define SOC_DIRAM_IRAM_HIGH 0x400C0000
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#define SOC_DIRAM_DRAM_LOW 0x3FFE0000
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#define SOC_DIRAM_DRAM_HIGH 0x40000000
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// Byte order of D/IRAM regions is reversed between accessing as DRAM or IRAM
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#define SOC_DIRAM_INVERTED 1
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// Region of memory accessible via DMA. See esp_ptr_dma_capable().
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#define SOC_DMA_LOW 0x3FFAE000
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#define SOC_DMA_HIGH 0x40000000
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// Region of memory that is byte-accessible. See esp_ptr_byte_accessible().
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#define SOC_BYTE_ACCESSIBLE_LOW 0x3FF90000
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#define SOC_BYTE_ACCESSIBLE_HIGH 0x40000000
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//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
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//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
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#define SOC_MEM_INTERNAL_LOW 0x3FF90000
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#define SOC_MEM_INTERNAL_HIGH 0x400C2000
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// Start (highest address) of ROM boot stack, only relevant during early boot
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#define SOC_ROM_STACK_START 0x3ffe3f20
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#if CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5
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//interrupt cpu using table, Please see the core-isa.h
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/*************************************************************************************************************
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* Intr num Level Type PRO CPU usage APP CPU uasge
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* 0 1 extern level WMAC Reserved
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* 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA
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* 2 1 extern level
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* 3 1 extern level
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* 4 1 extern level WBB
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* 5 1 extern level
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* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
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* 7 1 software BT/BLE VHCI BT/BLE VHCI
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* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
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* 9 1 extern level
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* 10 1 extern edge
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* 11 3 profiling
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* 12 1 extern level
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* 13 1 extern level
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* 14 7 nmi Reserved Reserved
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* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
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* 16 5 timer Reserved Reserved
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* 17 1 extern level
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* 18 1 extern level
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* 19 2 extern level
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* 20 2 extern level
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* 21 2 extern level
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* 22 3 extern edge
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* 23 3 extern level
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* 24 4 extern level
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* 25 4 extern level BT/BLE Controller BT/BLE Controller
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* 26 5 extern level TG1_WDT & CACHEERR
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* 27 3 extern level Reserved Reserved
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* 28 4 extern edge
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* 29 3 software BT/BLE hli BT/BLE hli
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* 30 4 extern edge Reserved Reserved
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* 31 5 extern level IPC_ISR IPC_ISR
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*************************************************************************************************************
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*/
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//CPU0 Interrupt number reserved, not touch this.
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#define ETS_WMAC_INUM 0
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#define ETS_BT_HOST_INUM 1
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#define ETS_WBB_INUM 4
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#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
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#define ETS_FRC1_INUM 22
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#define ETS_T1_WDT_CACHEERR_INUM 26
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#define ETS_T1_WDT_INUM ETS_T1_WDT_CACHEERR_INUM
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#define ETS_MEMACCESS_ERR_INUM ETS_T1_WDT_CACHEERR_INUM
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/* backwards compatibility only, use ETS_MEMACCESS_ERR_INUM instead*/
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#define ETS_CACHEERR_INUM ETS_MEMACCESS_ERR_INUM
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#define ETS_IPC_ISR_INUM 31
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#elif CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4
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//interrupt cpu using table, Please see the core-isa.h
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/*************************************************************************************************************
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* Intr num Level Type PRO CPU usage APP CPU uasge
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* 0 1 extern level WMAC Reserved
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* 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA
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* 2 1 extern level
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* 3 1 extern level
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* 4 1 extern level WBB
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* 5 1 extern level BT/BLE Controller BT/BLE Controller
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* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
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* 7 1 software BT/BLE VHCI BT/BLE VHCI
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* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
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* 9 1 extern level
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* 10 1 extern edge
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* 11 3 profiling
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* 12 1 extern level
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* 13 1 extern level
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* 14 7 nmi Reserved Reserved
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* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
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* 16 5 timer
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* 17 1 extern level
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* 18 1 extern level
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* 19 2 extern level
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* 20 2 extern level
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* 21 2 extern level
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* 22 3 extern edge
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* 23 3 extern level
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* 24 4 extern level TG1_WDT
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* 25 4 extern level CACHEERR
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* 26 5 extern level
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* 27 3 extern level Reserved Reserved
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* 28 4 extern edge IPC_ISR IPC_ISR
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* 29 3 software Reserved Reserved
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* 30 4 extern edge Reserved Reserved
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* 31 5 extern level
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*************************************************************************************************************
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*/
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//CPU0 Interrupt number reserved, not touch this.
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#define ETS_WMAC_INUM 0
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#define ETS_BT_HOST_INUM 1
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#define ETS_WBB_INUM 4
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#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
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#define ETS_FRC1_INUM 22
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#define ETS_T1_WDT_INUM 24
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#define ETS_MEMACCESS_ERR_INUM 25
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/* backwards compatibility only, use ETS_MEMACCESS_ERR_INUM instead*/
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#define ETS_CACHEERR_INUM ETS_MEMACCESS_ERR_INUM
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#define ETS_IPC_ISR_INUM 28
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#endif /* CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 */
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//CPU0 Interrupt number used in ROM, should be cancelled in SDK
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#define ETS_SLC_INUM 1
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#define ETS_UART0_INUM 5
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#define ETS_UART1_INUM 5
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//Other interrupt number should be managed by the user
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//Invalid interrupt for number interrupt matrix
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#define ETS_INVALID_INUM 6
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// Interrupt number for the Interrupt watchdog
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#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM)
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