kopia lustrzana https://github.com/espressif/esp-idf
243 wiersze
8.8 KiB
C
243 wiersze
8.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_image_format.h"
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#include "flash_qio_mode.h"
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#include "bootloader_init.h"
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#include "bootloader_clock.h"
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#include "bootloader_common.h"
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#include "bootloader_flash_config.h"
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#include "bootloader_mem.h"
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#include "bootloader_console.h"
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#include "bootloader_flash_priv.h"
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#include "esp_private/bootloader_flash_internal.h"
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#include "esp_cpu.h"
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#include "soc/dport_reg.h"
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#include "soc/efuse_reg.h"
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#include "soc/gpio_periph.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/io_mux_reg.h"
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#include "soc/rtc.h"
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#include "soc/spi_periph.h"
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#include "hal/gpio_hal.h"
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#include "xtensa/config/core.h"
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#include "xt_instr_macros.h"
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#include "esp32/rom/cache.h"
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#include "esp_rom_gpio.h"
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#include "esp_rom_efuse.h"
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#include "esp_rom_sys.h"
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#include "esp_rom_spiflash.h"
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#include "esp_efuse.h"
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static const char *TAG = "boot.esp32";
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#if !CONFIG_APP_BUILD_TYPE_RAM
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static void bootloader_reset_mmu(void)
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{
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/* completely reset MMU in case serial bootloader was running */
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Cache_Read_Disable(0);
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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Cache_Read_Disable(1);
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#endif
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Cache_Flush(0);
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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Cache_Flush(1);
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#endif
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mmu_init(0);
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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/* The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are
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necessary to work around a hardware bug. */
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DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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mmu_init(1);
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DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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#endif
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/* normal ROM boot exits with DROM0 cache unmasked,
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but serial bootloader exits with it masked. */
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DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
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#endif
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}
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#endif //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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static esp_err_t bootloader_check_rated_cpu_clock(void)
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{
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int rated_freq = bootloader_clock_get_rated_freq_mhz();
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if (rated_freq < CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ) {
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ESP_LOGE(TAG, "Chip CPU frequency rated for %dMHz, configured for %dMHz. Modify CPU frequency in menuconfig",
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rated_freq, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ);
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return ESP_FAIL;
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}
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return ESP_OK;
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}
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static void wdt_reset_cpu0_info_enable(void)
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{
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//We do not reset core1 info here because it didn't work before cpu1 was up. So we put it into call_start_cpu1.
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DPORT_REG_SET_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_PDEBUG_ENABLE | DPORT_PRO_CPU_RECORD_ENABLE);
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DPORT_REG_CLR_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_RECORD_ENABLE);
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}
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static void wdt_reset_info_dump(int cpu)
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{
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uint32_t inst = 0, pid = 0, stat = 0, data = 0, pc = 0,
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lsstat = 0, lsaddr = 0, lsdata = 0, dstat = 0;
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const char *cpu_name = cpu ? "APP" : "PRO";
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if (cpu == 0) {
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stat = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_STATUS_REG);
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pid = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PID_REG);
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inst = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGINST_REG);
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dstat = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG);
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data = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG);
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pc = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGPC_REG);
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lsstat = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG);
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lsaddr = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG);
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lsdata = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG);
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} else {
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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stat = DPORT_REG_READ(DPORT_APP_CPU_RECORD_STATUS_REG);
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pid = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PID_REG);
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inst = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGINST_REG);
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dstat = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG);
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data = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGDATA_REG);
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pc = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGPC_REG);
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lsstat = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG);
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lsaddr = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG);
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lsdata = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG);
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#endif
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}
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if (DPORT_RECORD_PDEBUGINST_SZ(inst) == 0 &&
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DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(dstat) == DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI) {
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ESP_LOGW(TAG, "WDT reset info: %s CPU PC=0x%"PRIx32" (waiti mode)", cpu_name, pc);
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} else {
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ESP_LOGW(TAG, "WDT reset info: %s CPU PC=0x%"PRIx32, cpu_name, pc);
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}
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ESP_LOGD(TAG, "WDT reset info: %s CPU STATUS 0x%08"PRIx32, cpu_name, stat);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PID 0x%08"PRIx32, cpu_name, pid);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGINST 0x%08"PRIx32, cpu_name, inst);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGSTATUS 0x%08"PRIx32, cpu_name, dstat);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGDATA 0x%08"PRIx32, cpu_name, data);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGPC 0x%08"PRIx32, cpu_name, pc);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0STAT 0x%08"PRIx32, cpu_name, lsstat);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0ADDR 0x%08"PRIx32, cpu_name, lsaddr);
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0DATA 0x%08"PRIx32, cpu_name, lsdata);
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}
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static void bootloader_check_wdt_reset(void)
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{
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int wdt_rst = 0;
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soc_reset_reason_t rst_reas[2];
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rst_reas[0] = esp_rom_get_reset_reason(0);
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rst_reas[1] = esp_rom_get_reset_reason(1);
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if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0 || rst_reas[0] == RESET_REASON_CORE_MWDT1 ||
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rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT) {
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ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
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wdt_rst = 1;
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}
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if (rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0 || rst_reas[1] == RESET_REASON_CORE_MWDT1 ||
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rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT) {
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ESP_LOGW(TAG, "APP CPU has been reset by WDT.");
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wdt_rst = 1;
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}
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if (wdt_rst) {
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// if reset by WDT dump info from trace port
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wdt_reset_info_dump(0);
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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wdt_reset_info_dump(1);
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#endif
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}
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wdt_reset_cpu0_info_enable();
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}
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esp_err_t bootloader_init(void)
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{
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esp_err_t ret = ESP_OK;
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#if XCHAL_ERRATUM_572
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uint32_t memctl = XCHAL_CACHE_MEMCTL_DEFAULT;
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WSR(MEMCTL, memctl);
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#endif // XCHAL_ERRATUM_572
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// In RAM_APP, memory will be initialized in `call_start_cpu0`
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#if !CONFIG_APP_BUILD_TYPE_RAM
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bootloader_init_mem();
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// check that static RAM is after the stack
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#ifndef NDEBUG
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{
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assert(&_bss_start <= &_bss_end);
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assert(&_data_start <= &_data_end);
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int *sp = esp_cpu_get_sp();
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assert(sp < &_bss_start);
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assert(sp < &_data_start);
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}
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#endif
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// clear bss section
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bootloader_clear_bss_section();
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#endif // !CONFIG_APP_BUILD_TYPE_RAM
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// init eFuse virtual mode (read eFuses to RAM)
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#ifdef CONFIG_EFUSE_VIRTUAL
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ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!");
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#ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
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esp_efuse_init_virtual_mode_in_ram();
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#endif
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#endif
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// bootst up vddsdio
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bootloader_common_vddsdio_configure();
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// check rated CPU clock
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if ((ret = bootloader_check_rated_cpu_clock()) != ESP_OK) {
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return ret;
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}
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// config clock
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bootloader_clock_configure();
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// initialize uart console, from now on, we can use esp_log
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bootloader_console_init();
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/* print 2nd bootloader banner */
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bootloader_print_banner();
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#if !CONFIG_APP_BUILD_TYPE_RAM
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// reset MMU
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bootloader_reset_mmu();
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// update flash ID
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bootloader_flash_update_id();
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// Check and run XMC startup flow
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if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
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ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!");
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return ret;
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}
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// read bootloader header
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if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
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return ret;
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}
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// read chip revision and check if it's compatible to bootloader
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if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
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return ret;
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}
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// initialize spi flash
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if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
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return ret;
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}
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#endif // #if !CONFIG_APP_BUILD_TYPE_RAM
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// check whether a WDT reset happend
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bootloader_check_wdt_reset();
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// config WDT
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bootloader_config_wdt();
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// enable RNG early entropy source
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bootloader_enable_random();
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return ret;
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}
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