Wykres commitów

906 Commity (main)

Autor SHA1 Wiadomość Data
jaseg 227d4ed1cd Bump version to v1.2.0 2023-11-14 21:56:03 +01:00
jaseg ea4c28e307 Make new test files pass 2023-11-14 21:54:04 +01:00
jaseg 51ef4882a1 Fix failing tests 2023-11-14 21:54:04 +01:00
jaseg df75a2fddb Small bugfix 2023-11-14 21:52:12 +01:00
jaseg 11325b213b Calculate out all aperture macros by default.
There are just too many severely buggy implementations around. Today I
ran into problems with both gerbv and with whatever JLC uses. You can
still export macros with raw expressions by setting a flag in the export
FileSettings.
2023-11-14 21:52:12 +01:00
jaseg 74fb384c4c aperture macros: work around gerbv/jlc wonkiness 2023-11-14 21:52:12 +01:00
jaseg 9af0713445 Remove debug print 2023-11-14 21:52:12 +01:00
jaseg 09e3731b74 aperture macros: Add expression simplification 2023-11-14 21:52:12 +01:00
jaseg 37b6b8f8d2 Aperture macro expression simplification WIP 2023-11-14 21:52:12 +01:00
jaseg 07362c592f Make sure we asterisk-terminate all G0x commands.
While this is common in the wild, not terminating them violates the
spec. It also breaks JLCPCB pretty badly. It seems their human review
process uses a Gerber viewer that like most can handle this, and won't
notice anything out of the ordinary, but then their photoplotter chokes
on this and literally stops plotting the file, discarding anything that
is after that line. This error is then apparently ignored and the
resulting broken boards shipped to the customer.
2023-11-14 21:52:12 +01:00
jaseg 2f5f7719c6 Split CLI into pretty svg and layer export sub-commands 2023-11-14 21:52:12 +01:00
jaseg cb1d3eb3fb pretty svg export: Mirror board bottom side 2023-11-14 21:52:12 +01:00
jaseg 4ee5c51f22 Add JLCPCB KiCad Gerber X2/aperture macro test files 2023-11-14 21:52:12 +01:00
jaseg 53788354e8 Add JLCPCB/FAB-3000 example gerbers 2023-11-14 21:52:12 +01:00
jaseg 10962ae2f4 Add P-CAD 2006 example gerbers 2023-11-14 21:52:12 +01:00
jaseg a19d307a7d Bump version to v1.1.0 2023-10-27 14:47:42 +02:00
jaseg 165e101dda ci: Disable tests for now, since upstream kicad-cli is broken. 2023-10-27 14:40:50 +02:00
jaseg 187c44555c Work around pip now requiring a new random feature switch to work
...for no good reason except to annoy anyone using it in a container.
2023-10-27 12:55:38 +02:00
jaseg 36da1fd68b Fix failing test cases 2023-10-26 23:53:23 +02:00
jaseg 9624e46147 Move coil stuff to separate repo 2023-10-26 00:48:52 +02:00
jaseg a35125b123 Fix all failing tests that don't involve kicad-cli 2023-10-26 00:36:24 +02:00
jaseg 31af2b260c WIP 2023-10-20 18:24:45 +02:00
jaseg dd49698df9 Update coil generator for the board house's latest fit 2023-10-20 12:44:48 +02:00
jaseg ef2b53325c Test board fixes 2023-10-20 11:44:10 +02:00
jaseg 5d3cd4694d Improve mouse bite spacing for JLC 2023-10-18 17:19:05 +02:00
jaseg 3631871a40 Optimize coil model mesh precision 2023-10-18 17:15:20 +02:00
jaseg b710462419 WIP 2023-10-18 10:59:28 +02:00
jaseg 313aa7dd26 Make coil test board more amenable to our favorite fab 2023-10-16 14:34:06 +02:00
jaseg 1ce02a9d25 Update sims & gen 2023-10-13 18:22:00 +02:00
jaseg 0ae13de322 Fix trace orientation 2023-10-12 20:50:40 +02:00
jaseg c212663bb2 Update gen script 2023-10-12 20:47:55 +02:00
jaseg 2a9c91b025 Add coil test board gen 2023-10-12 20:44:52 +02:00
jaseg 2d4c40c0f7 Get self capacitance simulation to work 2023-10-11 17:06:42 +02:00
jaseg a11f144c67 Give notebook a sensible name 2023-10-10 17:52:31 +02:00
jaseg e78e939a13 Run more sims 2023-10-10 17:52:01 +02:00
jaseg 4ea1b26293 Coupling sims work 2023-10-09 19:56:42 +02:00
jaseg cc59a6567e magnetic sim agreees with calculations now 2023-10-09 14:46:27 +02:00
jaseg a2d1429036 Try to fix mesh export 2023-10-06 18:49:08 +02:00
jaseg f793f12edb Try to fix mesh fragmentation 2023-10-06 16:45:21 +02:00
jaseg 78f5bf965f Mesh WIP 2023-10-06 16:17:25 +02:00
jaseg 84f7e5d25b Add missing simulation yamls 2023-10-06 14:42:35 +02:00
jaseg ba689e632e EM solver WIP 2023-10-04 16:02:46 +02:00
jaseg 4400dc361e mag mesh gen looks good 2023-09-29 18:30:02 +02:00
jaseg fdaf3c7e93 Add sim files 2023-09-29 10:37:40 +02:00
jaseg 6e12adb07e mesh gen works 2023-09-27 15:50:40 +02:00
jaseg cff22b9e08 WIP 2023-09-26 22:42:57 +02:00
jaseg f711c1d91c cli: Add kicad schematic svg rendering 2023-09-26 16:44:40 +02:00
jaseg 61e591b5b8 WiP 2023-09-22 18:54:11 +02:00
jaseg 95da482033 WIP 2023-09-22 18:54:11 +02:00
jaseg d2143bdf4d Trace connectivity WIP 2023-09-22 13:30:11 +02:00