kopia lustrzana https://github.com/espressif/esp-idf
refactor(rtc): move soc/rtc.h from soc to esp_hw_support component
Deprecated rtc_xtal_freq_t, replaced with soc_xtal_freq_t defined in clk_tree_defs.h in soc component.pull/13114/head
Song Ruo Jing
rodzic
e81932d2b2
commit
cf93777077
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@ -280,7 +280,7 @@ menu "Hardware Settings"
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bool "Autodetect"
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endchoice
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# rtc_xtal_freq_t enum in soc/rtc.h lists the XTAL frequencies can be supported
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# soc_xtal_freq_t enum in soc/clk_tree_defs.h lists the XTAL frequencies can be supported
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# SOC_XTAL_SUPPORT_XXX in soc_caps.h lists the XTAL frequencies already supported
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config XTAL_FREQ
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int
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@ -353,7 +353,7 @@ static bool get_working_pll_freq(const uint8_t *reference_data, bool is_flash, u
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uint32_t big_num = MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MAX * 2; //This number should be larger than MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MAX, for error handling
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uint32_t max_freq = 0;
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uint32_t min_freq = big_num;
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rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
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soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
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for (int pll_mhz_tuning = MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MIN; pll_mhz_tuning <= MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MAX; pll_mhz_tuning += 8) {
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//bbpll calibration start
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@ -1,4 +1,4 @@
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target_include_directories(${COMPONENT_LIB} PUBLIC .)
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target_include_directories(${COMPONENT_LIB} PUBLIC . include)
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set(srcs
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"rtc_clk.c"
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -12,12 +12,15 @@
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#include "soc/rtc_periph.h"
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#include "soc/clk_tree_defs.h"
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#define MHZ (1000000)
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#ifdef __cplusplus
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extern "C" {
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#endif
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/************************************************************************************/
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/***************** THIS FILE IS CONSIDERED AS A PRIVATE HEADER FILE *****************/
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/*** IT IS NOT RECOMMENDED TO USE THE APIS IN THIS FILE DIRECTLY IN APPLICATIONS ****/
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/************************************************************************************/
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/**
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* @file rtc.h
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* @brief Low-level RTC power, clock, and sleep functions.
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@ -47,6 +50,8 @@ extern "C" {
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* - rtc_init: initialization
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*/
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#define MHZ (1000000)
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/* Delays for various clock sources to be enabled/switched.
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* All values are in microseconds.
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*/
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@ -74,18 +79,6 @@ extern "C" {
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#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
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#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
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/**
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* @brief Possible main XTAL frequency values.
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*
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* Enum values should be equal to frequency in MHz.
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*/
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typedef enum {
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RTC_XTAL_FREQ_AUTO = 0, //!< Automatic XTAL frequency detection
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RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
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RTC_XTAL_FREQ_26M = 26, //!< 26 MHz XTAL
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RTC_XTAL_FREQ_24M = 24, //!< 24 MHz XTAL
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} rtc_xtal_freq_t;
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/**
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* @brief CPU clock configuration structure
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*/
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@ -109,7 +102,7 @@ typedef enum {
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* Initialization parameters for rtc_clk_init
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*/
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typedef struct rtc_clk_config_s {
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rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
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soc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
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uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
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soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose
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soc_rtc_slow_clk_src_t slow_clk_src : 2; //!< RTC_SLOW_CLK clock source to choose
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@ -134,7 +127,7 @@ typedef struct rtc_clk_config_s {
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/**
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* Initialize clocks and set CPU frequency
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*
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* If cfg.xtal_freq is set to RTC_XTAL_FREQ_AUTO, this function will attempt
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* If cfg.xtal_freq is set to SOC_XTAL_FREQ_AUTO, this function will attempt
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* to auto detect XTAL frequency. Auto detection is performed by comparing
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* XTAL frequency with the frequency of internal 8MHz oscillator. Note that at
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* high temperatures the frequency of the internal 8MHz oscillator may drift
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@ -151,12 +144,12 @@ void rtc_clk_init(rtc_clk_config_t cfg);
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* @brief Get main XTAL frequency
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*
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* This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
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* rtc_clk_init function, or if the value was RTC_XTAL_FREQ_AUTO, the detected
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* rtc_clk_init function, or if the value was SOC_XTAL_FREQ_AUTO, the detected
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* XTAL frequency.
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*
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* @return XTAL frequency, one of rtc_xtal_freq_t
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* @return XTAL frequency, one of soc_xtal_freq_t
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*/
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rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
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soc_xtal_freq_t rtc_clk_xtal_freq_get(void);
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/**
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* @brief Update XTAL frequency
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@ -166,7 +159,7 @@ rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
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*
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* @param xtal_freq New frequency value
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*/
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void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
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void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq);
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/**
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* @brief Enable or disable 32 kHz XTAL oscillator
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@ -544,8 +537,8 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_
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#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1)
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#define RTC_CNTL_MIN_SLP_VAL_MIN (128)
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#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
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#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
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#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 // Equivalent macro as `CLK_LL_RC_FAST_WAIT_DEFAULT`
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#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5 // Equivalent macro as `CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT`
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/**
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* @brief Prepare the chip to enter sleep mode
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@ -736,6 +729,15 @@ typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
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#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 4
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#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 8 MHz RC oscillator
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/**
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* @brief Possible main XTAL frequency values.
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*/
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typedef soc_xtal_freq_t rtc_xtal_freq_t;
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#define RTC_XTAL_FREQ_AUTO SOC_XTAL_FREQ_AUTO //!< Automatic XTAL frequency detection
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#define RTC_XTAL_FREQ_40M SOC_XTAL_FREQ_40M //!< 40 MHz XTAL
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#define RTC_XTAL_FREQ_26M SOC_XTAL_FREQ_26M //!< 26 MHz XTAL
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#define RTC_XTAL_FREQ_24M SOC_XTAL_FREQ_24M //!< 24 MHz XTAL
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/* Alias of frequency related macros */
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#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX
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#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -329,7 +329,7 @@ static void rtc_clk_bbpll_enable(void)
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clk_ll_bbpll_enable();
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}
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static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
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static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
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{
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/* Raise the voltage */
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if (pll_freq == CLK_LL_PLL_320M_FREQ_MHZ) {
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@ -459,7 +459,7 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t* ou
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void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t* config)
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{
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rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
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soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
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soc_cpu_clk_src_t old_cpu_clk_src = clk_ll_cpu_get_src();
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if (old_cpu_clk_src != SOC_CPU_CLK_SRC_XTAL) {
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rtc_clk_cpu_freq_to_xtal(xtal_freq, 1);
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@ -544,16 +544,16 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t* config)
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}
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}
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rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
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soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
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{
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uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
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if (xtal_freq_mhz == 0) {
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return RTC_XTAL_FREQ_AUTO;
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return SOC_XTAL_FREQ_AUTO;
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}
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return (rtc_xtal_freq_t)xtal_freq_mhz;
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return (soc_xtal_freq_t)xtal_freq_mhz;
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}
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void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
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void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq)
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{
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clk_ll_xtal_store_freq_mhz((uint32_t)xtal_freq);
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}
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -23,7 +23,7 @@
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*/
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#define XTAL_FREQ_EST_CYCLES 10
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static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void);
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static soc_xtal_freq_t rtc_clk_xtal_freq_estimate(void);
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extern void rtc_clk_cpu_freq_to_xtal(int freq, int div);
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static const char* TAG = "rtc_clk_init";
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@ -70,28 +70,28 @@ void rtc_clk_init(rtc_clk_config_t cfg)
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regi2c_ctrl_ll_i2c_apll_enable(); // TODO: This should be moved to apll_set_config
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/* Estimate XTAL frequency */
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rtc_xtal_freq_t configured_xtal_freq = cfg.xtal_freq;
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rtc_xtal_freq_t stored_xtal_freq = rtc_clk_xtal_freq_get(); // read the xtal freq value from RTC storage register
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rtc_xtal_freq_t xtal_freq = configured_xtal_freq;
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if (configured_xtal_freq == RTC_XTAL_FREQ_AUTO) {
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if (stored_xtal_freq != RTC_XTAL_FREQ_AUTO) {
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soc_xtal_freq_t configured_xtal_freq = cfg.xtal_freq;
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soc_xtal_freq_t stored_xtal_freq = rtc_clk_xtal_freq_get(); // read the xtal freq value from RTC storage register
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soc_xtal_freq_t xtal_freq = configured_xtal_freq;
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if (configured_xtal_freq == SOC_XTAL_FREQ_AUTO) {
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if (stored_xtal_freq != SOC_XTAL_FREQ_AUTO) {
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/* XTAL frequency has already been set, use existing value */
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xtal_freq = stored_xtal_freq;
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} else {
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/* Not set yet, estimate XTAL frequency based on RTC_FAST_CLK */
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xtal_freq = rtc_clk_xtal_freq_estimate();
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if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
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if (xtal_freq == SOC_XTAL_FREQ_AUTO) {
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ESP_HW_LOGW(TAG, "Can't estimate XTAL frequency, assuming 26MHz");
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xtal_freq = RTC_XTAL_FREQ_26M;
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xtal_freq = SOC_XTAL_FREQ_26M;
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}
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}
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} else if (stored_xtal_freq == RTC_XTAL_FREQ_AUTO) {
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} else if (stored_xtal_freq == SOC_XTAL_FREQ_AUTO) {
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/* Exact frequency was set in sdkconfig, but still warn if autodetected
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* frequency is different. If autodetection failed, worst case we get a
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* bit of garbage output.
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*/
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rtc_xtal_freq_t est_xtal_freq = rtc_clk_xtal_freq_estimate();
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soc_xtal_freq_t est_xtal_freq = rtc_clk_xtal_freq_estimate();
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if (est_xtal_freq != configured_xtal_freq) {
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ESP_HW_LOGW(TAG, "Possibly invalid CONFIG_XTAL_FREQ setting (%dMHz). Detected %d MHz.",
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configured_xtal_freq, est_xtal_freq);
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@ -137,12 +137,12 @@ void rtc_clk_init(rtc_clk_config_t cfg)
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rtc_clk_slow_src_set(cfg.slow_clk_src);
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}
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static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void)
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static soc_xtal_freq_t rtc_clk_xtal_freq_estimate(void)
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{
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#if CONFIG_IDF_ENV_FPGA
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return RTC_XTAL_FREQ_40M;
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return SOC_XTAL_FREQ_40M;
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#endif // CONFIG_IDF_ENV_FPGA
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rtc_xtal_freq_t xtal_freq;
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soc_xtal_freq_t xtal_freq;
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/* Enable 8M/256 clock if needed */
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const bool clk_8m_enabled = rtc_clk_8m_enabled();
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const bool clk_8md256_enabled = rtc_clk_8md256_enabled();
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@ -160,22 +160,22 @@ static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void)
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*/
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switch (freq_mhz) {
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case 21 ... 31:
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xtal_freq = RTC_XTAL_FREQ_26M;
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xtal_freq = SOC_XTAL_FREQ_26M;
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break;
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case 32 ... 33:
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ESP_HW_LOGW(TAG, "Potentially bogus XTAL frequency: %"PRIu32" MHz, guessing 26 MHz", freq_mhz);
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xtal_freq = RTC_XTAL_FREQ_26M;
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xtal_freq = SOC_XTAL_FREQ_26M;
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break;
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case 34 ... 35:
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ESP_HW_LOGW(TAG, "Potentially bogus XTAL frequency: %"PRIu32" MHz, guessing 40 MHz", freq_mhz);
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xtal_freq = RTC_XTAL_FREQ_40M;
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xtal_freq = SOC_XTAL_FREQ_40M;
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break;
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case 36 ... 45:
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xtal_freq = RTC_XTAL_FREQ_40M;
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xtal_freq = SOC_XTAL_FREQ_40M;
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break;
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default:
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ESP_HW_LOGW(TAG, "Bogus XTAL frequency: %"PRIu32" MHz", freq_mhz);
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xtal_freq = RTC_XTAL_FREQ_AUTO;
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xtal_freq = SOC_XTAL_FREQ_AUTO;
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break;
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}
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/* Restore 8M and 8md256 clocks to original state */
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -67,10 +67,10 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
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}
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uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq);
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/* Check if the required number of slowclk_cycles may result in an overflow of TIMG_RTC_CALI_VALUE */
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rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
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if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
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soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
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if (xtal_freq == SOC_XTAL_FREQ_AUTO) {
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/* XTAL frequency is not known yet; assume worst case (40 MHz) */
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xtal_freq = RTC_XTAL_FREQ_40M;
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xtal_freq = SOC_XTAL_FREQ_40M;
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}
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const uint32_t us_timer_max = TIMG_RTC_CALI_VALUE / (uint32_t) xtal_freq;
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if (us_time_estimate >= us_timer_max) {
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@ -119,7 +119,7 @@ uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
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return ratio;
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}
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static inline bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
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static inline bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
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{
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uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768
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uint64_t delta = expected_xtal_cycles / 2000; // 5/10000
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@ -129,10 +129,10 @@ static inline bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slo
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uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
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{
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assert(slowclk_cycles);
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rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
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soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
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uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
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if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid(xtal_freq, slowclk_cycles, xtal_cycles)) {
|
||||
if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -15,3 +15,4 @@ endif()
|
|||
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
|
||||
|
||||
target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
|
||||
target_include_directories(${COMPONENT_LIB} PUBLIC . include)
|
||||
|
|
|
|||
|
|
@ -1,22 +0,0 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file i2c_brownout.h
|
||||
* @brief Register definitions for brownout detector
|
||||
*
|
||||
* This file lists register fields of the brownout detector, located on an internal configuration
|
||||
* bus. These definitions are used via macros defined in i2c_rtc_clk.h.
|
||||
*/
|
||||
|
||||
#define I2C_BOD 0x61
|
||||
#define I2C_BOD_HOSTID 1
|
||||
|
||||
#define I2C_BOD_THRESHOLD 0x5
|
||||
#define I2C_BOD_THRESHOLD_MSB 2
|
||||
#define I2C_BOD_THRESHOLD_LSB 0
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -15,11 +15,16 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/************************************************************************************/
|
||||
/***************** THIS FILE IS CONSIDERED AS A PRIVATE HEADER FILE *****************/
|
||||
/*** IT IS NOT RECOMMENDED TO USE THE APIS IN THIS FILE DIRECTLY IN APPLICATIONS ****/
|
||||
/************************************************************************************/
|
||||
|
||||
/**
|
||||
* @file rtc.h
|
||||
* @brief Low-level RTC power, clock, and sleep functions.
|
||||
*
|
||||
* Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
|
||||
* Functions in this file facilitate configuration of ESP32C2's RTC_CNTL peripheral.
|
||||
* RTC_CNTL peripheral handles many functions:
|
||||
* - enables/disables clocks and power to various parts of the chip; this is
|
||||
* done using direct register access (forcing power up or power down) or by
|
||||
|
|
@ -83,8 +88,8 @@ extern "C" {
|
|||
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
|
||||
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
|
||||
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
|
||||
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 // Equivalent macro as `CLK_LL_RC_FAST_WAIT_DEFAULT`
|
||||
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5 // Equivalent macro as `CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT`
|
||||
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 255
|
||||
|
|
@ -135,17 +140,6 @@ storing in efuse (based on ATE 5k ECO3 chips)
|
|||
#define V_RTC_MID_MUL10000 10800
|
||||
#define V_DIG_MID_MUL10000 10860
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency values.
|
||||
*
|
||||
* Enum values should be equal to frequency in MHz.
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_XTAL_FREQ_26M = 26, //!< 26 MHz XTAL
|
||||
RTC_XTAL_FREQ_32M = 32, //!< 32 MHz XTAL
|
||||
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
|
||||
} rtc_xtal_freq_t;
|
||||
|
||||
/**
|
||||
* @brief CPU clock configuration structure
|
||||
*/
|
||||
|
|
@ -177,7 +171,7 @@ typedef enum {
|
|||
* Initialization parameters for rtc_clk_init
|
||||
*/
|
||||
typedef struct {
|
||||
rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
soc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
|
||||
soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose
|
||||
soc_rtc_slow_clk_src_t slow_clk_src : 2; //!< RTC_SLOW_CLK clock source to choose
|
||||
|
|
@ -244,9 +238,9 @@ void rtc_clk_init(rtc_clk_config_t cfg);
|
|||
* This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
|
||||
* rtc_clk_init function
|
||||
*
|
||||
* @return XTAL frequency, one of rtc_xtal_freq_t
|
||||
* @return XTAL frequency, one of soc_xtal_freq_t
|
||||
*/
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
||||
soc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
||||
|
||||
/**
|
||||
* @brief Update XTAL frequency
|
||||
|
|
@ -256,7 +250,7 @@ rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
|||
*
|
||||
* @param xtal_freq New frequency value
|
||||
*/
|
||||
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
|
||||
void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq);
|
||||
|
||||
/**
|
||||
* @brief Enable 32KHz external oscillator
|
||||
|
|
@ -723,6 +717,14 @@ typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
|
|||
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2
|
||||
#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency values.
|
||||
*/
|
||||
typedef soc_xtal_freq_t rtc_xtal_freq_t;
|
||||
#define RTC_XTAL_FREQ_40M SOC_XTAL_FREQ_40M //!< 40 MHz XTAL
|
||||
#define RTC_XTAL_FREQ_32M SOC_XTAL_FREQ_32M //!< 32 MHz XTAL
|
||||
#define RTC_XTAL_FREQ_26M SOC_XTAL_FREQ_26M //!< 26 MHz XTAL
|
||||
|
||||
/* Alias of frequency related macros */
|
||||
#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX
|
||||
#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -117,7 +117,7 @@ static void rtc_clk_bbpll_enable(void)
|
|||
clk_ll_bbpll_enable();
|
||||
}
|
||||
|
||||
static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
|
||||
static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
|
||||
{
|
||||
/* Digital part */
|
||||
clk_ll_bbpll_set_freq_mhz(pll_freq);
|
||||
|
|
@ -304,17 +304,17 @@ static void rtc_clk_cpu_freq_to_8m(void)
|
|||
rtc_clk_apb_freq_update(SOC_CLK_RC_FAST_FREQ_APPROX);
|
||||
}
|
||||
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
|
||||
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
|
||||
{
|
||||
uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
|
||||
if (xtal_freq_mhz == 0) {
|
||||
ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume %dMHz", CONFIG_XTAL_FREQ);
|
||||
return CONFIG_XTAL_FREQ;
|
||||
}
|
||||
return (rtc_xtal_freq_t)xtal_freq_mhz;
|
||||
return (soc_xtal_freq_t)xtal_freq_mhz;
|
||||
}
|
||||
|
||||
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
|
||||
void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq)
|
||||
{
|
||||
clk_ll_xtal_store_freq_mhz(xtal_freq);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
|
|||
/* Enable the internal bus used to configure BBPLL */
|
||||
regi2c_ctrl_ll_i2c_bbpll_enable(); // TODO: This should be moved to bbpll_set_config
|
||||
|
||||
rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
|
||||
soc_xtal_freq_t xtal_freq = cfg.xtal_freq;
|
||||
esp_rom_output_tx_wait_idle(0);
|
||||
rtc_clk_xtal_freq_update(xtal_freq);
|
||||
rtc_clk_apb_freq_update(xtal_freq * MHZ);
|
||||
|
|
|
|||
|
|
@ -133,7 +133,7 @@ uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
|||
return ratio;
|
||||
}
|
||||
|
||||
static inline bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
|
||||
static inline bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
|
||||
{
|
||||
uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768
|
||||
uint64_t delta = expected_xtal_cycles / 2000; // 5/10000
|
||||
|
|
@ -143,10 +143,10 @@ static inline bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slo
|
|||
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
||||
{
|
||||
assert(slowclk_cycles);
|
||||
rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
||||
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
||||
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
|
||||
|
||||
if ((cal_clk == RTC_CAL_32K_OSC_SLOW) && !rtc_clk_cal_32k_valid(xtal_freq, slowclk_cycles, xtal_cycles)) {
|
||||
if ((cal_clk == RTC_CAL_32K_OSC_SLOW) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -22,3 +22,4 @@ endif()
|
|||
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
|
||||
|
||||
target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
|
||||
target_include_directories(${COMPONENT_LIB} PUBLIC . include)
|
||||
|
|
|
|||
|
|
@ -1,22 +0,0 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file i2c_brownout.h
|
||||
* @brief Register definitions for brownout detector
|
||||
*
|
||||
* This file lists register fields of the brownout detector, located on an internal configuration
|
||||
* bus. These definitions are used via macros defined in i2c_rtc_clk.h.
|
||||
*/
|
||||
|
||||
#define I2C_BOD 0x61
|
||||
#define I2C_BOD_HOSTID 1
|
||||
|
||||
#define I2C_BOD_THRESHOLD 0x5
|
||||
#define I2C_BOD_THRESHOLD_MSB 2
|
||||
#define I2C_BOD_THRESHOLD_LSB 0
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -15,11 +15,16 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/************************************************************************************/
|
||||
/***************** THIS FILE IS CONSIDERED AS A PRIVATE HEADER FILE *****************/
|
||||
/*** IT IS NOT RECOMMENDED TO USE THE APIS IN THIS FILE DIRECTLY IN APPLICATIONS ****/
|
||||
/************************************************************************************/
|
||||
|
||||
/**
|
||||
* @file rtc.h
|
||||
* @brief Low-level RTC power, clock, and sleep functions.
|
||||
*
|
||||
* Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
|
||||
* Functions in this file facilitate configuration of ESP32C3's RTC_CNTL peripheral.
|
||||
* RTC_CNTL peripheral handles many functions:
|
||||
* - enables/disables clocks and power to various parts of the chip; this is
|
||||
* done using direct register access (forcing power up or power down) or by
|
||||
|
|
@ -85,8 +90,8 @@ extern "C" {
|
|||
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
|
||||
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
|
||||
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
|
||||
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 // Equivalent macro as `CLK_LL_RC_FAST_WAIT_DEFAULT`
|
||||
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5 // Equivalent macro as `CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT`
|
||||
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 255
|
||||
|
|
@ -137,16 +142,6 @@ storing in efuse (based on ATE 5k ECO3 chips)
|
|||
#define V_RTC_MID_MUL10000 10800
|
||||
#define V_DIG_MID_MUL10000 10860
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency values.
|
||||
*
|
||||
* Enum values should be equal to frequency in MHz.
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_XTAL_FREQ_32M = 32,
|
||||
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
|
||||
} rtc_xtal_freq_t;
|
||||
|
||||
/**
|
||||
* @brief CPU clock configuration structure
|
||||
*/
|
||||
|
|
@ -176,7 +171,7 @@ typedef enum {
|
|||
* Initialization parameters for rtc_clk_init
|
||||
*/
|
||||
typedef struct {
|
||||
rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
soc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
|
||||
soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose
|
||||
soc_rtc_slow_clk_src_t slow_clk_src : 2; //!< RTC_SLOW_CLK clock source to choose
|
||||
|
|
@ -243,9 +238,9 @@ void rtc_clk_init(rtc_clk_config_t cfg);
|
|||
* This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
|
||||
* rtc_clk_init function
|
||||
*
|
||||
* @return XTAL frequency, one of rtc_xtal_freq_t
|
||||
* @return XTAL frequency, one of soc_xtal_freq_t
|
||||
*/
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
||||
soc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
||||
|
||||
/**
|
||||
* @brief Update XTAL frequency
|
||||
|
|
@ -255,7 +250,7 @@ rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
|||
*
|
||||
* @param xtal_freq New frequency value
|
||||
*/
|
||||
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
|
||||
void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable 32 kHz XTAL oscillator
|
||||
|
|
@ -803,6 +798,13 @@ typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
|
|||
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2
|
||||
#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency values.
|
||||
*/
|
||||
typedef soc_xtal_freq_t rtc_xtal_freq_t;
|
||||
#define RTC_XTAL_FREQ_40M SOC_XTAL_FREQ_40M //!< 40 MHz XTAL
|
||||
#define RTC_XTAL_FREQ_32M SOC_XTAL_FREQ_32M //!< 32 MHz XTAL
|
||||
|
||||
/* Alias of frequency related macros */
|
||||
#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX
|
||||
#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -147,7 +147,7 @@ static void rtc_clk_bbpll_enable(void)
|
|||
clk_ll_bbpll_enable();
|
||||
}
|
||||
|
||||
static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
|
||||
static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
|
||||
{
|
||||
/* Digital part */
|
||||
clk_ll_bbpll_set_freq_mhz(pll_freq);
|
||||
|
|
@ -330,17 +330,17 @@ static void rtc_clk_cpu_freq_to_8m(void)
|
|||
rtc_clk_apb_freq_update(SOC_CLK_RC_FAST_FREQ_APPROX);
|
||||
}
|
||||
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
|
||||
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
|
||||
{
|
||||
uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
|
||||
if (xtal_freq_mhz == 0) {
|
||||
ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
|
||||
return RTC_XTAL_FREQ_40M;
|
||||
return SOC_XTAL_FREQ_40M;
|
||||
}
|
||||
return (rtc_xtal_freq_t)xtal_freq_mhz;
|
||||
return (soc_xtal_freq_t)xtal_freq_mhz;
|
||||
}
|
||||
|
||||
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
|
||||
void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq)
|
||||
{
|
||||
clk_ll_xtal_store_freq_mhz(xtal_freq);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
|
|||
/* Enable the internal bus used to configure BBPLL */
|
||||
regi2c_ctrl_ll_i2c_bbpll_enable(); // TODO: This should be moved to bbpll_set_config
|
||||
|
||||
rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
|
||||
soc_xtal_freq_t xtal_freq = cfg.xtal_freq;
|
||||
esp_rom_output_tx_wait_idle(0);
|
||||
rtc_clk_xtal_freq_update(xtal_freq);
|
||||
rtc_clk_apb_freq_update(xtal_freq * MHZ);
|
||||
|
|
|
|||
|
|
@ -136,7 +136,7 @@ uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
|||
return ratio;
|
||||
}
|
||||
|
||||
static bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
|
||||
static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
|
||||
{
|
||||
uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768
|
||||
uint64_t delta = expected_xtal_cycles / 2000; // 5/10000
|
||||
|
|
@ -146,10 +146,10 @@ static bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cy
|
|||
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
||||
{
|
||||
assert(slowclk_cycles);
|
||||
rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
||||
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
||||
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
|
||||
|
||||
if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid(xtal_freq, slowclk_cycles, xtal_cycles)) {
|
||||
if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -14,4 +14,4 @@ endif()
|
|||
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
|
||||
|
||||
target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
|
||||
target_include_directories(${COMPONENT_LIB} PUBLIC . private_include)
|
||||
target_include_directories(${COMPONENT_LIB} PUBLIC . include private_include)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -15,11 +15,16 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/************************************************************************************/
|
||||
/***************** THIS FILE IS CONSIDERED AS A PRIVATE HEADER FILE *****************/
|
||||
/*** IT IS NOT RECOMMENDED TO USE THE APIS IN THIS FILE DIRECTLY IN APPLICATIONS ****/
|
||||
/************************************************************************************/
|
||||
|
||||
/**
|
||||
* @file rtc.h
|
||||
* @brief Low-level RTC power, clock functions.
|
||||
*
|
||||
* Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
|
||||
* Functions in this file facilitate configuration of ESP32C5's RTC_CNTL peripheral.
|
||||
* RTC_CNTL peripheral handles many functions:
|
||||
* - enables/disables clocks and power to various parts of the chip; this is
|
||||
* done using direct register access (forcing power up or power down) or by
|
||||
|
|
@ -51,21 +56,6 @@ extern "C" {
|
|||
#define OTHER_BLOCKS_POWERUP 1
|
||||
#define OTHER_BLOCKS_WAIT 1
|
||||
|
||||
// TODO: [ESP32C5] IDF-8667
|
||||
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
|
||||
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
|
||||
*/
|
||||
#define RTC_CNTL_DBIAS_SLP 5 //sleep dig_dbias & rtc_dbias
|
||||
#define RTC_CNTL_DBIAS_0V90 13 //digital voltage
|
||||
#define RTC_CNTL_DBIAS_0V95 16
|
||||
#define RTC_CNTL_DBIAS_1V00 18
|
||||
#define RTC_CNTL_DBIAS_1V05 20
|
||||
#define RTC_CNTL_DBIAS_1V10 23
|
||||
#define RTC_CNTL_DBIAS_1V15 25
|
||||
#define RTC_CNTL_DBIAS_1V20 28
|
||||
#define RTC_CNTL_DBIAS_1V25 30
|
||||
#define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact
|
||||
|
||||
/* Delays for various clock sources to be enabled/switched.
|
||||
* All values are in microseconds.
|
||||
*/
|
||||
|
|
@ -75,19 +65,8 @@ extern "C" {
|
|||
#define SOC_DELAY_RC_FAST_DIGI_SWITCH 5
|
||||
#define SOC_DELAY_RC32K_ENABLE 300
|
||||
|
||||
/* Core voltage: // TODO: [ESP32C5] IDF-8667
|
||||
* Currently, ESP32C5 never adjust its wake voltage in runtime
|
||||
* Only sets dig/rtc voltage dbias at startup time
|
||||
*/
|
||||
#define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V20
|
||||
#define DIG_DBIAS_160M RTC_CNTL_DBIAS_1V20
|
||||
#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
|
||||
#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
|
||||
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
|
||||
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
|
||||
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
|
||||
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 128
|
||||
|
|
@ -126,16 +105,6 @@ storing in efuse (based on ATE 5k ECO3 chips)
|
|||
#define V_RTC_MID_MUL10000 10800
|
||||
#define V_DIG_MID_MUL10000 10860
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency values.
|
||||
*
|
||||
* Enum values should be equal to frequency in MHz.
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
|
||||
RTC_XTAL_FREQ_48M = 48, //!< 48 MHz XTAL
|
||||
} rtc_xtal_freq_t;
|
||||
|
||||
/**
|
||||
* @brief CPU clock configuration structure
|
||||
*/
|
||||
|
|
@ -172,7 +141,7 @@ typedef enum {
|
|||
* Initialization parameters for rtc_clk_init
|
||||
*/
|
||||
typedef struct {
|
||||
rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
soc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
|
||||
soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose
|
||||
soc_rtc_slow_clk_src_t slow_clk_src : 3; //!< RTC_SLOW_CLK clock source to choose
|
||||
|
|
@ -211,9 +180,9 @@ void rtc_clk_init(rtc_clk_config_t cfg);
|
|||
* This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
|
||||
* rtc_clk_init function
|
||||
*
|
||||
* @return XTAL frequency, one of rtc_xtal_freq_t
|
||||
* @return XTAL frequency, one of soc_xtal_freq_t
|
||||
*/
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
||||
soc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
||||
|
||||
/**
|
||||
* @brief Update XTAL frequency
|
||||
|
|
@ -223,7 +192,7 @@ rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
|||
*
|
||||
* @param xtal_freq New frequency value
|
||||
*/
|
||||
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
|
||||
void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable 32 kHz XTAL oscillator
|
||||
|
|
@ -481,43 +450,12 @@ bool rtc_dig_8m_enabled(void);
|
|||
*/
|
||||
uint32_t rtc_clk_freq_cal(uint32_t cal_val);
|
||||
|
||||
|
||||
// -------------------------- CLOCK TREE DEFS ALIAS ----------------------------
|
||||
// **WARNING**: The following are only for backwards compatibility.
|
||||
// Please use the declarations in soc/clk_tree_defs.h instead.
|
||||
/**
|
||||
* @brief CPU clock source
|
||||
* @brief Possible main XTAL frequency values. TODO: To be removed!
|
||||
*/
|
||||
typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t;
|
||||
#define RTC_CPU_FREQ_SRC_XTAL SOC_CPU_CLK_SRC_XTAL //!< XTAL
|
||||
#define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL //!< PLL (480M)
|
||||
#define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 17.5M RTC oscillator
|
||||
|
||||
/**
|
||||
* @brief RTC SLOW_CLK frequency values
|
||||
*/
|
||||
typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
|
||||
#define RTC_SLOW_FREQ_RTC SOC_RTC_SLOW_CLK_SRC_RC_SLOW //!< Internal 150 kHz RC oscillator
|
||||
#define RTC_SLOW_FREQ_32K_XTAL SOC_RTC_SLOW_CLK_SRC_XTAL32K //!< External 32 kHz XTAL
|
||||
|
||||
/**
|
||||
* @brief RTC FAST_CLK frequency values
|
||||
*/
|
||||
typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
|
||||
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2
|
||||
#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator
|
||||
|
||||
/* Alias of frequency related macros */
|
||||
#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX
|
||||
#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX
|
||||
#define RTC_SLOW_CLK_FREQ_150K SOC_CLK_RC_SLOW_FREQ_APPROX
|
||||
#define RTC_SLOW_CLK_FREQ_32K SOC_CLK_XTAL32K_FREQ_APPROX
|
||||
|
||||
/* Alias of deprecated function names */
|
||||
#define rtc_clk_slow_freq_set(slow_freq) rtc_clk_slow_src_set(slow_freq)
|
||||
#define rtc_clk_slow_freq_get() rtc_clk_slow_src_get()
|
||||
#define rtc_clk_fast_freq_set(fast_freq) rtc_clk_fast_src_set(fast_freq)
|
||||
#define rtc_clk_fast_freq_get() rtc_clk_fast_src_get()
|
||||
typedef soc_xtal_freq_t rtc_xtal_freq_t;
|
||||
#define RTC_XTAL_FREQ_40M SOC_XTAL_FREQ_40M //!< 40 MHz XTAL
|
||||
#define RTC_XTAL_FREQ_48M SOC_XTAL_FREQ_48M //!< 48 MHz XTAL
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
@ -157,7 +157,7 @@ static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
|
|||
#endif
|
||||
}
|
||||
|
||||
static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
|
||||
static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
|
||||
{
|
||||
assert((pll_freq == CLK_LL_PLL_160M_FREQ_MHZ) || \
|
||||
(pll_freq == CLK_LL_PLL_240M_FREQ_MHZ));
|
||||
|
|
@ -371,12 +371,12 @@ void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
|
|||
clk_ll_cpu_clk_src_lock_release();
|
||||
}
|
||||
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
|
||||
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
|
||||
{
|
||||
return CONFIG_XTAL_FREQ;
|
||||
}
|
||||
|
||||
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
|
||||
void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq)
|
||||
{
|
||||
clk_ll_xtal_store_freq_mhz(xtal_freq);
|
||||
}
|
||||
|
|
@ -434,8 +434,3 @@ bool rtc_dig_8m_enabled(void)
|
|||
{
|
||||
return clk_ll_rc_fast_digi_is_enabled();
|
||||
}
|
||||
|
||||
/* Name used in libphy.a:phy_chip_v7.o
|
||||
* TODO: update the library to use rtc_clk_xtal_freq_get
|
||||
*/
|
||||
rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get")));
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
|
|||
|
||||
clk_ll_rc_fast_tick_conf();
|
||||
|
||||
rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
|
||||
soc_xtal_freq_t xtal_freq = cfg.xtal_freq;
|
||||
esp_rom_output_tx_wait_idle(0);
|
||||
rtc_clk_xtal_freq_update(xtal_freq);
|
||||
|
||||
|
|
|
|||
|
|
@ -203,7 +203,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
|
|||
return cal_val;
|
||||
}
|
||||
|
||||
static bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
|
||||
static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
|
||||
{
|
||||
uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768
|
||||
uint64_t delta = expected_xtal_cycles / 2000; // 5/10000 = 0.05% error range
|
||||
|
|
@ -212,7 +212,7 @@ static bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cy
|
|||
|
||||
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
||||
{
|
||||
rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
||||
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
||||
|
||||
/*The Fosc CLK of calibration circuit is divided by 32 for ECO1.
|
||||
So we need to divide the calibrate cycles of the FOSC for ECO1 and above chips by 32 to
|
||||
|
|
@ -225,7 +225,7 @@ uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
|||
|
||||
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
|
||||
|
||||
if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid(xtal_freq, slowclk_cycles, xtal_cycles)) {
|
||||
if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -21,4 +21,4 @@ endif()
|
|||
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
|
||||
|
||||
target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
|
||||
target_include_directories(${COMPONENT_LIB} PUBLIC . private_include)
|
||||
target_include_directories(${COMPONENT_LIB} PUBLIC . include private_include)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -15,11 +15,16 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/************************************************************************************/
|
||||
/***************** THIS FILE IS CONSIDERED AS A PRIVATE HEADER FILE *****************/
|
||||
/*** IT IS NOT RECOMMENDED TO USE THE APIS IN THIS FILE DIRECTLY IN APPLICATIONS ****/
|
||||
/************************************************************************************/
|
||||
|
||||
/**
|
||||
* @file rtc.h
|
||||
* @brief Low-level RTC power, clock functions.
|
||||
*
|
||||
* Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
|
||||
* Functions in this file facilitate configuration of ESP32C6's RTC_CNTL peripheral.
|
||||
* RTC_CNTL peripheral handles many functions:
|
||||
* - enables/disables clocks and power to various parts of the chip; this is
|
||||
* done using direct register access (forcing power up or power down) or by
|
||||
|
|
@ -51,21 +56,6 @@ extern "C" {
|
|||
#define OTHER_BLOCKS_POWERUP 1
|
||||
#define OTHER_BLOCKS_WAIT 1
|
||||
|
||||
// TODO: IDF-5781
|
||||
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
|
||||
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
|
||||
*/
|
||||
#define RTC_CNTL_DBIAS_SLP 5 //sleep dig_dbias & rtc_dbias
|
||||
#define RTC_CNTL_DBIAS_0V90 13 //digital voltage
|
||||
#define RTC_CNTL_DBIAS_0V95 16
|
||||
#define RTC_CNTL_DBIAS_1V00 18
|
||||
#define RTC_CNTL_DBIAS_1V05 20
|
||||
#define RTC_CNTL_DBIAS_1V10 23
|
||||
#define RTC_CNTL_DBIAS_1V15 25
|
||||
#define RTC_CNTL_DBIAS_1V20 28
|
||||
#define RTC_CNTL_DBIAS_1V25 30
|
||||
#define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact
|
||||
|
||||
/* Delays for various clock sources to be enabled/switched.
|
||||
* All values are in microseconds.
|
||||
*/
|
||||
|
|
@ -75,19 +65,8 @@ extern "C" {
|
|||
#define SOC_DELAY_RC_FAST_DIGI_SWITCH 5
|
||||
#define SOC_DELAY_RC32K_ENABLE 300
|
||||
|
||||
/* Core voltage: // TODO: IDF-5781
|
||||
* Currently, ESP32C6 never adjust its wake voltage in runtime
|
||||
* Only sets dig/rtc voltage dbias at startup time
|
||||
*/
|
||||
#define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V20
|
||||
#define DIG_DBIAS_160M RTC_CNTL_DBIAS_1V20
|
||||
#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
|
||||
#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
|
||||
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
|
||||
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
|
||||
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
|
||||
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 128
|
||||
|
|
@ -126,15 +105,6 @@ storing in efuse (based on ATE 5k ECO3 chips)
|
|||
#define V_RTC_MID_MUL10000 10800
|
||||
#define V_DIG_MID_MUL10000 10860
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency values.
|
||||
*
|
||||
* Enum values should be equal to frequency in MHz.
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
|
||||
} rtc_xtal_freq_t;
|
||||
|
||||
/**
|
||||
* @brief CPU clock configuration structure
|
||||
*/
|
||||
|
|
@ -171,7 +141,7 @@ typedef enum {
|
|||
* Initialization parameters for rtc_clk_init
|
||||
*/
|
||||
typedef struct {
|
||||
rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
soc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
|
||||
soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose
|
||||
soc_rtc_slow_clk_src_t slow_clk_src : 3; //!< RTC_SLOW_CLK clock source to choose
|
||||
|
|
@ -210,9 +180,9 @@ void rtc_clk_init(rtc_clk_config_t cfg);
|
|||
* This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
|
||||
* rtc_clk_init function
|
||||
*
|
||||
* @return XTAL frequency, one of rtc_xtal_freq_t
|
||||
* @return XTAL frequency, one of soc_xtal_freq_t
|
||||
*/
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
||||
soc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
||||
|
||||
/**
|
||||
* @brief Update XTAL frequency
|
||||
|
|
@ -222,7 +192,7 @@ rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
|||
*
|
||||
* @param xtal_freq New frequency value
|
||||
*/
|
||||
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
|
||||
void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable 32 kHz XTAL oscillator
|
||||
|
|
@ -506,6 +476,12 @@ typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
|
|||
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2
|
||||
#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency values.
|
||||
*/
|
||||
typedef soc_xtal_freq_t rtc_xtal_freq_t;
|
||||
#define RTC_XTAL_FREQ_40M SOC_XTAL_FREQ_40M //!< 40 MHz XTAL
|
||||
|
||||
/* Alias of frequency related macros */
|
||||
#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX
|
||||
#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -157,7 +157,7 @@ static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
|
|||
#endif
|
||||
}
|
||||
|
||||
static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
|
||||
static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
|
||||
{
|
||||
/* Digital part */
|
||||
clk_ll_bbpll_set_freq_mhz(pll_freq);
|
||||
|
|
@ -357,17 +357,17 @@ void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
|
|||
clk_ll_cpu_clk_src_lock_release();
|
||||
}
|
||||
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
|
||||
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
|
||||
{
|
||||
uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
|
||||
if (xtal_freq_mhz == 0) {
|
||||
ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
|
||||
return RTC_XTAL_FREQ_40M;
|
||||
return SOC_XTAL_FREQ_40M;
|
||||
}
|
||||
return (rtc_xtal_freq_t)xtal_freq_mhz;
|
||||
return (soc_xtal_freq_t)xtal_freq_mhz;
|
||||
}
|
||||
|
||||
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
|
||||
void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq)
|
||||
{
|
||||
clk_ll_xtal_store_freq_mhz(xtal_freq);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
|
|||
|
||||
clk_ll_rc_fast_tick_conf();
|
||||
|
||||
rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
|
||||
soc_xtal_freq_t xtal_freq = cfg.xtal_freq;
|
||||
esp_rom_output_tx_wait_idle(0);
|
||||
rtc_clk_xtal_freq_update(xtal_freq);
|
||||
|
||||
|
|
|
|||
|
|
@ -200,7 +200,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
|
|||
return cal_val;
|
||||
}
|
||||
|
||||
static bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
|
||||
static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
|
||||
{
|
||||
uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768
|
||||
uint64_t delta = expected_xtal_cycles / 2000; // 5/10000 = 0.05% error range
|
||||
|
|
@ -210,7 +210,7 @@ static bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cy
|
|||
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
||||
{
|
||||
assert(slowclk_cycles);
|
||||
rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
||||
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
||||
|
||||
/*The Fosc CLK of calibration circuit is divided by 32 for ECO1.
|
||||
So we need to divide the calibrate cycles of the FOSC for ECO1 and above chips by 32 to
|
||||
|
|
@ -223,7 +223,7 @@ uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
|||
|
||||
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
|
||||
|
||||
if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid(xtal_freq, slowclk_cycles, xtal_cycles)) {
|
||||
if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -15,4 +15,4 @@ endif()
|
|||
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
|
||||
|
||||
target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
|
||||
target_include_directories(${COMPONENT_LIB} PUBLIC . private_include)
|
||||
target_include_directories(${COMPONENT_LIB} PUBLIC . include private_include)
|
||||
|
|
|
|||
|
|
@ -1,22 +0,0 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file i2c_brownout.h
|
||||
* @brief Register definitions for brownout detector
|
||||
*
|
||||
* This file lists register fields of the brownout detector, located on an internal configuration
|
||||
* bus. These definitions are used via macros defined in i2c_rtc_clk.h.
|
||||
*/
|
||||
|
||||
#define I2C_BOD 0x61
|
||||
#define I2C_BOD_HOSTID 1
|
||||
|
||||
#define I2C_BOD_THRESHOLD 0x5
|
||||
#define I2C_BOD_THRESHOLD_MSB 2
|
||||
#define I2C_BOD_THRESHOLD_LSB 0
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -15,11 +15,16 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/************************************************************************************/
|
||||
/***************** THIS FILE IS CONSIDERED AS A PRIVATE HEADER FILE *****************/
|
||||
/*** IT IS NOT RECOMMENDED TO USE THE APIS IN THIS FILE DIRECTLY IN APPLICATIONS ****/
|
||||
/************************************************************************************/
|
||||
|
||||
/**
|
||||
* @file rtc.h
|
||||
* @brief Low-level RTC power, clock functions.
|
||||
*
|
||||
* Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
|
||||
* Functions in this file facilitate configuration of ESP32H2's RTC_CNTL peripheral.
|
||||
* RTC_CNTL peripheral handles many functions:
|
||||
* - enables/disables clocks and power to various parts of the chip; this is
|
||||
* done using direct register access (forcing power up or power down) or by
|
||||
|
|
@ -52,21 +57,6 @@ extern "C" {
|
|||
#define OTHER_BLOCKS_POWERUP 1
|
||||
#define OTHER_BLOCKS_WAIT 1
|
||||
|
||||
// TODO: IDF-6254
|
||||
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
|
||||
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
|
||||
*/
|
||||
#define RTC_CNTL_DBIAS_SLP 5 //sleep dig_dbias & rtc_dbias
|
||||
#define RTC_CNTL_DBIAS_0V90 13 //digital voltage
|
||||
#define RTC_CNTL_DBIAS_0V95 16
|
||||
#define RTC_CNTL_DBIAS_1V00 18
|
||||
#define RTC_CNTL_DBIAS_1V05 20
|
||||
#define RTC_CNTL_DBIAS_1V10 23
|
||||
#define RTC_CNTL_DBIAS_1V15 25
|
||||
#define RTC_CNTL_DBIAS_1V20 28
|
||||
#define RTC_CNTL_DBIAS_1V25 30
|
||||
#define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact
|
||||
|
||||
/* Delays for various clock sources to be enabled/switched.
|
||||
* All values are in microseconds.
|
||||
*/
|
||||
|
|
@ -78,19 +68,8 @@ extern "C" {
|
|||
#define SOC_DELAY_LP_PLL_SWITCH 3
|
||||
#define SOC_DELAY_LP_PLL_ENABLE 50
|
||||
|
||||
/* Core voltage: //TODO: IDF-6254
|
||||
* Currently, ESP32H2 never adjust its wake voltage in runtime
|
||||
* Only sets dig/rtc voltage dbias at startup time
|
||||
*/
|
||||
#define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V20
|
||||
#define DIG_DBIAS_160M RTC_CNTL_DBIAS_1V20
|
||||
#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
|
||||
#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
|
||||
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
|
||||
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
|
||||
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
|
||||
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 860
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 85
|
||||
|
|
@ -129,15 +108,6 @@ storing in efuse (based on ATE 5k ECO3 chips)
|
|||
#define V_RTC_MID_MUL10000 10800
|
||||
#define V_DIG_MID_MUL10000 10860
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency values.
|
||||
*
|
||||
* Enum values should be equal to frequency in MHz.
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_XTAL_FREQ_32M = 32,
|
||||
} rtc_xtal_freq_t;
|
||||
|
||||
/**
|
||||
* @brief CPU clock configuration structure
|
||||
*/
|
||||
|
|
@ -173,7 +143,7 @@ typedef enum {
|
|||
* Initialization parameters for rtc_clk_init
|
||||
*/
|
||||
typedef struct {
|
||||
rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
soc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
|
||||
soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose
|
||||
soc_rtc_slow_clk_src_t slow_clk_src : 3; //!< RTC_SLOW_CLK clock source to choose
|
||||
|
|
@ -188,7 +158,7 @@ typedef struct {
|
|||
* Default initializer for rtc_clk_config_t
|
||||
*/
|
||||
#define RTC_CLK_CONFIG_DEFAULT() { \
|
||||
.xtal_freq = RTC_XTAL_FREQ_32M, \
|
||||
.xtal_freq = SOC_XTAL_FREQ_32M, \
|
||||
.cpu_freq_mhz = 96, \
|
||||
.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
|
||||
.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
|
||||
|
|
@ -212,9 +182,9 @@ void rtc_clk_init(rtc_clk_config_t cfg);
|
|||
* This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
|
||||
* rtc_clk_init function
|
||||
*
|
||||
* @return XTAL frequency, one of rtc_xtal_freq_t
|
||||
* @return XTAL frequency, one of soc_xtal_freq_t
|
||||
*/
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
||||
soc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
||||
|
||||
/**
|
||||
* @brief Update XTAL frequency
|
||||
|
|
@ -224,7 +194,7 @@ rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
|||
*
|
||||
* @param xtal_freq New frequency value
|
||||
*/
|
||||
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
|
||||
void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable 32 kHz XTAL oscillator
|
||||
|
|
@ -501,6 +471,12 @@ typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
|
|||
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2
|
||||
#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 8 MHz RC oscillator
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency values.
|
||||
*/
|
||||
typedef soc_xtal_freq_t rtc_xtal_freq_t;
|
||||
#define RTC_XTAL_FREQ_32M SOC_XTAL_FREQ_32M //!< 32 MHz XTAL
|
||||
|
||||
/* Alias of frequency related macros */
|
||||
#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX
|
||||
#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -173,7 +173,7 @@ static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
|
|||
#endif
|
||||
}
|
||||
|
||||
static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
|
||||
static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
|
||||
{
|
||||
/* Digital part */
|
||||
clk_ll_bbpll_set_freq_mhz(pll_freq);
|
||||
|
|
@ -411,17 +411,17 @@ void rtc_clk_cpu_set_to_default_config(void)
|
|||
rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
|
||||
}
|
||||
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
|
||||
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
|
||||
{
|
||||
uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
|
||||
if (xtal_freq_mhz == 0) {
|
||||
ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 32MHz");
|
||||
return RTC_XTAL_FREQ_32M;
|
||||
return SOC_XTAL_FREQ_32M;
|
||||
}
|
||||
return (rtc_xtal_freq_t)xtal_freq_mhz;
|
||||
return (soc_xtal_freq_t)xtal_freq_mhz;
|
||||
}
|
||||
|
||||
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
|
||||
void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq)
|
||||
{
|
||||
clk_ll_xtal_store_freq_mhz(xtal_freq);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
|
|||
|
||||
clk_ll_rc_fast_tick_conf();
|
||||
|
||||
rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
|
||||
soc_xtal_freq_t xtal_freq = cfg.xtal_freq;
|
||||
esp_rom_output_tx_wait_idle(0);
|
||||
rtc_clk_xtal_freq_update(xtal_freq);
|
||||
|
||||
|
|
|
|||
|
|
@ -200,7 +200,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
|
|||
return cal_val;
|
||||
}
|
||||
|
||||
static bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
|
||||
static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
|
||||
{
|
||||
uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768
|
||||
uint64_t delta = expected_xtal_cycles / 2000; // 5/10000 = 0.05% error range
|
||||
|
|
@ -210,7 +210,7 @@ static bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cy
|
|||
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
||||
{
|
||||
assert(slowclk_cycles);
|
||||
rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
||||
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
||||
|
||||
/*The Fosc CLK of calibration circuit is divided by 32 for ECO2.
|
||||
So we need to divide the calibrate cycles of the FOSC for ECO1 and above chips by 32 to
|
||||
|
|
@ -223,7 +223,7 @@ uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
|||
|
||||
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
|
||||
|
||||
if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid(xtal_freq, slowclk_cycles, xtal_cycles)) {
|
||||
if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -25,4 +25,4 @@ endif()
|
|||
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
|
||||
|
||||
target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
|
||||
target_include_directories(${COMPONENT_LIB} PUBLIC . private_include)
|
||||
target_include_directories(${COMPONENT_LIB} PUBLIC . include private_include)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -10,17 +10,22 @@
|
|||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
#include "hal/hal_utils.h" // TODO: IDF-8941 Move rtc.h to esp_hw_support, so that dependency is correct
|
||||
#include "hal/hal_utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/************************************************************************************/
|
||||
/***************** THIS FILE IS CONSIDERED AS A PRIVATE HEADER FILE *****************/
|
||||
/*** IT IS NOT RECOMMENDED TO USE THE APIS IN THIS FILE DIRECTLY IN APPLICATIONS ****/
|
||||
/************************************************************************************/
|
||||
|
||||
/**
|
||||
* @file rtc.h
|
||||
* @brief Low-level RTC power, clock functions.
|
||||
*
|
||||
* Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
|
||||
* Functions in this file facilitate configuration of ESP32P4's RTC_CNTL peripheral.
|
||||
* RTC_CNTL peripheral handles many functions:
|
||||
* - enables/disables clocks and power to various parts of the chip; this is
|
||||
* done using direct register access (forcing power up or power down) or by
|
||||
|
|
@ -48,21 +53,6 @@ extern "C" {
|
|||
#define OTHER_BLOCKS_POWERUP 1
|
||||
#define OTHER_BLOCKS_WAIT 1
|
||||
|
||||
// TODO: IDF-7528, TODO: IDF-7529
|
||||
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
|
||||
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
|
||||
*/
|
||||
#define RTC_CNTL_DBIAS_SLP 5 //sleep dig_dbias & rtc_dbias
|
||||
#define RTC_CNTL_DBIAS_0V90 13 //digital voltage
|
||||
#define RTC_CNTL_DBIAS_0V95 16
|
||||
#define RTC_CNTL_DBIAS_1V00 18
|
||||
#define RTC_CNTL_DBIAS_1V05 20
|
||||
#define RTC_CNTL_DBIAS_1V10 23
|
||||
#define RTC_CNTL_DBIAS_1V15 25
|
||||
#define RTC_CNTL_DBIAS_1V20 28
|
||||
#define RTC_CNTL_DBIAS_1V25 30
|
||||
#define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact
|
||||
|
||||
/* Delays for various clock sources to be enabled/switched.
|
||||
* All values are in microseconds.
|
||||
*/
|
||||
|
|
@ -74,19 +64,8 @@ extern "C" {
|
|||
#define SOC_DELAY_LP_PLL_SWITCH 3
|
||||
#define SOC_DELAY_LP_PLL_ENABLE 50
|
||||
|
||||
/* Core voltage: // TODO: IDF-7528, TODO: IDF-7529
|
||||
* Currently, ESP32C6 never adjust its wake voltage in runtime
|
||||
* Only sets dig/rtc voltage dbias at startup time
|
||||
*/
|
||||
#define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V20
|
||||
#define DIG_DBIAS_160M RTC_CNTL_DBIAS_1V20
|
||||
#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
|
||||
#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
|
||||
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
|
||||
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
|
||||
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
|
||||
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 128
|
||||
|
|
@ -125,15 +104,6 @@ storing in efuse (based on ATE 5k ECO3 chips)
|
|||
#define V_RTC_MID_MUL10000 10800
|
||||
#define V_DIG_MID_MUL10000 10860
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency values.
|
||||
*
|
||||
* Enum values should be equal to frequency in MHz.
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
|
||||
} rtc_xtal_freq_t;
|
||||
|
||||
/**
|
||||
* @brief CPU clock configuration structure
|
||||
*/
|
||||
|
|
@ -175,7 +145,7 @@ typedef enum {
|
|||
* Initialization parameters for rtc_clk_init
|
||||
*/
|
||||
typedef struct {
|
||||
rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
soc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
|
||||
soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose
|
||||
soc_rtc_slow_clk_src_t slow_clk_src : 3; //!< RTC_SLOW_CLK clock source to choose
|
||||
|
|
@ -214,9 +184,9 @@ void rtc_clk_init(rtc_clk_config_t cfg);
|
|||
* This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
|
||||
* rtc_clk_init function
|
||||
*
|
||||
* @return XTAL frequency, one of rtc_xtal_freq_t
|
||||
* @return XTAL frequency, one of soc_xtal_freq_t
|
||||
*/
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
||||
soc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
||||
|
||||
/**
|
||||
* @brief Update XTAL frequency
|
||||
|
|
@ -226,7 +196,7 @@ rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
|||
*
|
||||
* @param xtal_freq New frequency value
|
||||
*/
|
||||
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
|
||||
void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable 32 kHz XTAL oscillator
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -133,7 +133,7 @@ static void rtc_clk_cpll_enable(void)
|
|||
clk_ll_cpll_enable();
|
||||
}
|
||||
|
||||
static void rtc_clk_cpll_configure(rtc_xtal_freq_t xtal_freq, int cpll_freq)
|
||||
static void rtc_clk_cpll_configure(soc_xtal_freq_t xtal_freq, int cpll_freq)
|
||||
{
|
||||
/* Digital part */
|
||||
clk_ll_cpll_set_freq_mhz(cpll_freq);
|
||||
|
|
@ -314,7 +314,7 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
|
|||
rtc_clk_cpll_enable();
|
||||
}
|
||||
if (config->source_freq_mhz != s_cur_cpll_freq) {
|
||||
rtc_xtal_freq_t xtal_freq_mhz = rtc_clk_xtal_freq_get();
|
||||
soc_xtal_freq_t xtal_freq_mhz = rtc_clk_xtal_freq_get();
|
||||
// Calibrate CPLL freq to a new value requires to switch CPU clock source to XTAL first
|
||||
rtc_clk_cpu_freq_to_xtal((uint32_t)xtal_freq_mhz, 1, false);
|
||||
rtc_clk_cpll_configure(xtal_freq_mhz, config->source_freq_mhz);
|
||||
|
|
@ -394,17 +394,17 @@ void rtc_clk_cpu_set_to_default_config(void)
|
|||
rtc_clk_cpu_freq_to_xtal(freq_mhz, 1, true);
|
||||
}
|
||||
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
|
||||
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
|
||||
{
|
||||
uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
|
||||
if (xtal_freq_mhz == 0) {
|
||||
ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
|
||||
return RTC_XTAL_FREQ_40M;
|
||||
return SOC_XTAL_FREQ_40M;
|
||||
}
|
||||
return (rtc_xtal_freq_t)xtal_freq_mhz;
|
||||
return (soc_xtal_freq_t)xtal_freq_mhz;
|
||||
}
|
||||
|
||||
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
|
||||
void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq)
|
||||
{
|
||||
clk_ll_xtal_store_freq_mhz(xtal_freq);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
|
|||
esp_rom_delay_us(1000);
|
||||
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_XPD);
|
||||
|
||||
rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
|
||||
soc_xtal_freq_t xtal_freq = cfg.xtal_freq;
|
||||
esp_rom_output_tx_wait_idle(0);
|
||||
rtc_clk_xtal_freq_update(xtal_freq);
|
||||
|
||||
|
|
|
|||
|
|
@ -169,7 +169,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
|||
return cal_val;
|
||||
}
|
||||
|
||||
static bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
|
||||
static bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
|
||||
{
|
||||
uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768
|
||||
uint64_t delta = expected_xtal_cycles / 2000; // 5/10000 = 0.05% error range
|
||||
|
|
@ -179,10 +179,10 @@ static bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cy
|
|||
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
||||
{
|
||||
assert(slowclk_cycles);
|
||||
rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
||||
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
||||
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
|
||||
|
||||
if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid(xtal_freq, slowclk_cycles, xtal_cycles)) {
|
||||
if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
target_include_directories(${COMPONENT_LIB} PUBLIC .)
|
||||
target_include_directories(${COMPONENT_LIB} PUBLIC . include)
|
||||
|
||||
set(srcs
|
||||
"rtc_clk.c"
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -15,11 +15,16 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/************************************************************************************/
|
||||
/***************** THIS FILE IS CONSIDERED AS A PRIVATE HEADER FILE *****************/
|
||||
/*** IT IS NOT RECOMMENDED TO USE THE APIS IN THIS FILE DIRECTLY IN APPLICATIONS ****/
|
||||
/************************************************************************************/
|
||||
|
||||
/**
|
||||
* @file rtc.h
|
||||
* @brief Low-level RTC power, clock, and sleep functions.
|
||||
*
|
||||
* Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
|
||||
* Functions in this file facilitate configuration of ESP32S2's RTC_CNTL peripheral.
|
||||
* RTC_CNTL peripheral handles many functions:
|
||||
* - enables/disables clocks and power to various parts of the chip; this is
|
||||
* done using direct register access (forcing power up or power down) or by
|
||||
|
|
@ -92,8 +97,8 @@ extern "C" {
|
|||
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
|
||||
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
|
||||
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
|
||||
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 // Equivalent macro as `CLK_LL_RC_FAST_WAIT_DEFAULT`
|
||||
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5 // Equivalent macro as `CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT`
|
||||
|
||||
/* Various delays to be programmed into power control state machines */
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1)
|
||||
|
|
@ -139,16 +144,6 @@ use together with RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT
|
|||
#define RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V75 0
|
||||
#define RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V75 1
|
||||
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency values.
|
||||
*
|
||||
* Enum values should be equal to frequency in MHz.
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
|
||||
} rtc_xtal_freq_t;
|
||||
|
||||
/**
|
||||
* @brief CPU clock configuration structure
|
||||
*/
|
||||
|
|
@ -178,7 +173,7 @@ typedef enum {
|
|||
* Initialization parameters for rtc_clk_init
|
||||
*/
|
||||
typedef struct {
|
||||
rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
soc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
|
||||
soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose
|
||||
soc_rtc_slow_clk_src_t slow_clk_src : 2; //!< RTC_SLOW_CLK clock source to choose
|
||||
|
|
@ -250,7 +245,7 @@ void rtc_clk_init(rtc_clk_config_t cfg);
|
|||
*
|
||||
* @return XTAL frequency in MHz
|
||||
*/
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
||||
soc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable 32 kHz XTAL oscillator
|
||||
|
|
@ -871,6 +866,12 @@ typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
|
|||
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 4
|
||||
#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 8 MHz RC oscillator
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency values.
|
||||
*/
|
||||
typedef soc_xtal_freq_t rtc_xtal_freq_t;
|
||||
#define RTC_XTAL_FREQ_40M SOC_XTAL_FREQ_40M //!< 40 MHz XTAL
|
||||
|
||||
/* Alias of frequency related macros */
|
||||
#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX
|
||||
#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -225,9 +225,9 @@ static void rtc_clk_bbpll_enable(void)
|
|||
clk_ll_bbpll_enable();
|
||||
}
|
||||
|
||||
static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
|
||||
static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
|
||||
{
|
||||
assert(xtal_freq == RTC_XTAL_FREQ_40M);
|
||||
assert(xtal_freq == SOC_XTAL_FREQ_40M);
|
||||
|
||||
/* Digital part */
|
||||
clk_ll_bbpll_set_freq_mhz(pll_freq);
|
||||
|
|
@ -353,7 +353,7 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t* config)
|
|||
}
|
||||
} else if (config->source == SOC_CPU_CLK_SRC_PLL) {
|
||||
rtc_clk_bbpll_enable();
|
||||
rtc_clk_bbpll_configure((rtc_xtal_freq_t)CLK_LL_XTAL_FREQ_MHZ, config->source_freq_mhz);
|
||||
rtc_clk_bbpll_configure((soc_xtal_freq_t)CLK_LL_XTAL_FREQ_MHZ, config->source_freq_mhz);
|
||||
rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
|
||||
} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
|
||||
rtc_clk_cpu_freq_to_8m();
|
||||
|
|
@ -471,10 +471,10 @@ static void rtc_clk_cpu_freq_to_8m(void)
|
|||
rtc_clk_apb_freq_update(SOC_CLK_RC_FAST_FREQ_APPROX);
|
||||
}
|
||||
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
|
||||
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
|
||||
{
|
||||
// Note, inside esp32s2-only code it's better to use CLK_LL_XTAL_FREQ_MHZ constant
|
||||
return (rtc_xtal_freq_t)CLK_LL_XTAL_FREQ_MHZ;
|
||||
return (soc_xtal_freq_t)CLK_LL_XTAL_FREQ_MHZ;
|
||||
}
|
||||
|
||||
void rtc_clk_apb_freq_update(uint32_t apb_freq)
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
|
|||
regi2c_ctrl_ll_i2c_bbpll_enable(); // TODO: This should be moved to bbpll_set_config
|
||||
regi2c_ctrl_ll_i2c_apll_enable(); // TODO: This should be moved to apll_set_config
|
||||
|
||||
rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
|
||||
soc_xtal_freq_t xtal_freq = cfg.xtal_freq;
|
||||
esp_rom_output_tx_wait_idle(0);
|
||||
rtc_clk_apb_freq_update(xtal_freq * MHZ);
|
||||
|
||||
|
|
|
|||
|
|
@ -124,7 +124,7 @@ static uint32_t rtc_clk_cal_internal_cycling(rtc_cal_sel_t cal_clk, uint32_t slo
|
|||
static uint32_t rtc_clk_xtal_to_slowclk(uint64_t xtal_cycles, uint32_t slowclk_cycles)
|
||||
{
|
||||
assert(slowclk_cycles);
|
||||
rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
||||
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
||||
uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles;
|
||||
uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider;
|
||||
uint32_t period = (uint32_t)(period_64 & UINT32_MAX);
|
||||
|
|
@ -199,7 +199,7 @@ uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
|||
return ratio;
|
||||
}
|
||||
|
||||
static inline bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
|
||||
static inline bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
|
||||
{
|
||||
uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768
|
||||
uint64_t delta = expected_xtal_cycles / 2000; // 5/10000
|
||||
|
|
@ -210,7 +210,7 @@ uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
|||
{
|
||||
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles, RTC_TIME_CAL_ONEOFF_MODE);
|
||||
|
||||
if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid(rtc_clk_xtal_freq_get(), slowclk_cycles, xtal_cycles)) {
|
||||
if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)rtc_clk_xtal_freq_get(), slowclk_cycles, xtal_cycles)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
target_include_directories(${COMPONENT_LIB} PUBLIC .)
|
||||
target_include_directories(${COMPONENT_LIB} PUBLIC . include)
|
||||
|
||||
set(srcs
|
||||
"rtc_clk.c"
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -16,11 +16,16 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/************************************************************************************/
|
||||
/***************** THIS FILE IS CONSIDERED AS A PRIVATE HEADER FILE *****************/
|
||||
/*** IT IS NOT RECOMMENDED TO USE THE APIS IN THIS FILE DIRECTLY IN APPLICATIONS ****/
|
||||
/************************************************************************************/
|
||||
|
||||
/**
|
||||
* @file rtc.h
|
||||
* @brief Low-level RTC power, clock, and sleep functions.
|
||||
*
|
||||
* Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
|
||||
* Functions in this file facilitate configuration of ESP32S3's RTC_CNTL peripheral.
|
||||
* RTC_CNTL peripheral handles many functions:
|
||||
* - enables/disables clocks and power to various parts of the chip; this is
|
||||
* done using direct register access (forcing power up or power down) or by
|
||||
|
|
@ -91,8 +96,8 @@ extern "C" {
|
|||
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
|
||||
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
|
||||
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
|
||||
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 // Equivalent macro as `CLK_LL_RC_FAST_WAIT_DEFAULT`
|
||||
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5 // Equivalent macro as `CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT`
|
||||
|
||||
/* Various delays to be programmed into power control state machines */
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250)
|
||||
|
|
@ -141,18 +146,6 @@ set LDO slave during CPU switch
|
|||
*/
|
||||
#define DEFAULT_LDO_SLAVE 0x7
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency values.
|
||||
*
|
||||
* Enum values should be equal to frequency in MHz.
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_XTAL_FREQ_32M = 32,
|
||||
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
|
||||
} rtc_xtal_freq_t;
|
||||
|
||||
/**
|
||||
* @brief CPU clock configuration structure
|
||||
*/
|
||||
|
|
@ -182,7 +175,7 @@ typedef enum {
|
|||
* Initialization parameters for rtc_clk_init
|
||||
*/
|
||||
typedef struct {
|
||||
rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
soc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
|
||||
soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose
|
||||
soc_rtc_slow_clk_src_t slow_clk_src : 2; //!< RTC_SLOW_CLK clock source to choose
|
||||
|
|
@ -257,9 +250,9 @@ void rtc_clk_init(rtc_clk_config_t cfg);
|
|||
* This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
|
||||
* rtc_clk_init function
|
||||
*
|
||||
* @return XTAL frequency, one of rtc_xtal_freq_t
|
||||
* @return XTAL frequency, one of soc_xtal_freq_t
|
||||
*/
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
||||
soc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
||||
|
||||
/**
|
||||
* @brief Update XTAL frequency
|
||||
|
|
@ -269,7 +262,7 @@ rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
|||
*
|
||||
* @param xtal_freq New frequency value
|
||||
*/
|
||||
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
|
||||
void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable 32 kHz XTAL oscillator
|
||||
|
|
@ -851,6 +844,13 @@ typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
|
|||
#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2
|
||||
#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency values.
|
||||
*/
|
||||
typedef soc_xtal_freq_t rtc_xtal_freq_t;
|
||||
#define RTC_XTAL_FREQ_40M SOC_XTAL_FREQ_40M //!< 40 MHz XTAL
|
||||
#define RTC_XTAL_FREQ_32M SOC_XTAL_FREQ_32M //!< 32 MHz XTAL
|
||||
|
||||
/* Alias of frequency related macros */
|
||||
#define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX
|
||||
#define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -162,7 +162,7 @@ static void rtc_clk_bbpll_enable(void)
|
|||
clk_ll_bbpll_enable();
|
||||
}
|
||||
|
||||
static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
|
||||
static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
|
||||
{
|
||||
/* Digital part */
|
||||
clk_ll_bbpll_set_freq_mhz(pll_freq);
|
||||
|
|
@ -408,17 +408,17 @@ static void rtc_clk_cpu_freq_to_8m(void)
|
|||
REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, DEFAULT_LDO_SLAVE);
|
||||
}
|
||||
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
|
||||
soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
|
||||
{
|
||||
uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
|
||||
if (xtal_freq_mhz == 0) {
|
||||
ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
|
||||
return RTC_XTAL_FREQ_40M;
|
||||
return SOC_XTAL_FREQ_40M;
|
||||
}
|
||||
return (rtc_xtal_freq_t)xtal_freq_mhz;
|
||||
return (soc_xtal_freq_t)xtal_freq_mhz;
|
||||
}
|
||||
|
||||
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
|
||||
void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq)
|
||||
{
|
||||
clk_ll_xtal_store_freq_mhz(xtal_freq);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
|
|||
/* Enable the internal bus used to configure BBPLL */
|
||||
regi2c_ctrl_ll_i2c_bbpll_enable(); // TODO: This should be moved to bbpll_set_config
|
||||
|
||||
rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
|
||||
soc_xtal_freq_t xtal_freq = cfg.xtal_freq;
|
||||
esp_rom_output_tx_wait_idle(0);
|
||||
rtc_clk_xtal_freq_update(xtal_freq);
|
||||
rtc_clk_apb_freq_update(xtal_freq * MHZ);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -135,7 +135,7 @@ uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
|||
return ratio;
|
||||
}
|
||||
|
||||
static inline bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
|
||||
static inline bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
|
||||
{
|
||||
uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768
|
||||
uint64_t delta = expected_xtal_cycles / 2000; // 5/10000
|
||||
|
|
@ -145,10 +145,10 @@ static inline bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slo
|
|||
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
|
||||
{
|
||||
assert(slowclk_cycles);
|
||||
rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
||||
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
||||
uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
|
||||
|
||||
if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid(xtal_freq, slowclk_cycles, xtal_cycles)) {
|
||||
if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -17,6 +17,7 @@
|
|||
#include "soc/rtc.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/uart_ll.h"
|
||||
#include "hal/clk_tree_ll.h"
|
||||
|
||||
#if SOC_LP_TIMER_SUPPORTED
|
||||
#include "hal/lp_timer_ll.h"
|
||||
|
|
@ -91,9 +92,8 @@ void RTC_IRAM_ATTR esp_wake_stub_uart_tx_wait_idle(uint8_t uart_no)
|
|||
|
||||
void RTC_IRAM_ATTR esp_wake_stub_set_wakeup_time(uint64_t time_in_us)
|
||||
{
|
||||
uint64_t rtc_count_delta = time_in_us * (1 << RTC_CLK_CAL_FRACT) / clk_ll_rtc_slow_load_cal();
|
||||
#if SOC_LP_TIMER_SUPPORTED
|
||||
uint64_t rtc_count_delta = lp_timer_ll_time_to_count(time_in_us);
|
||||
|
||||
lp_timer_ll_counter_snapshot(&LP_TIMER);
|
||||
uint32_t lo = lp_timer_ll_get_counter_value_low(&LP_TIMER, 0);
|
||||
uint32_t hi = lp_timer_ll_get_counter_value_high(&LP_TIMER, 0);
|
||||
|
|
@ -103,7 +103,6 @@ void RTC_IRAM_ATTR esp_wake_stub_set_wakeup_time(uint64_t time_in_us)
|
|||
lp_timer_ll_set_alarm_target(&LP_TIMER, 0, rtc_curr_count + rtc_count_delta);
|
||||
lp_timer_ll_set_target_enable(&LP_TIMER, 0, true);
|
||||
#else
|
||||
uint64_t rtc_count_delta = rtc_cntl_ll_time_to_count(time_in_us);
|
||||
uint64_t rtc_curr_count = rtc_cntl_ll_get_rtc_time();
|
||||
rtc_cntl_ll_set_wakeup_timer(rtc_curr_count + rtc_count_delta);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include "esp_assert.h"
|
||||
|
||||
#include "soc/soc.h"
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <stddef.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/lp_aon_reg.h"
|
||||
#include "soc/reset_reasons.h"
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include "esp_assert.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/reset_reasons.h"
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -116,14 +116,14 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
|
|||
|
||||
Bootloaders pre-v2.1 don't do this.
|
||||
*/
|
||||
rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
||||
if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
|
||||
soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
||||
if (xtal_freq == SOC_XTAL_FREQ_AUTO) {
|
||||
ESP_EARLY_LOGW(TAG, "RTC domain not initialised by bootloader");
|
||||
bootloader_clock_configure();
|
||||
}
|
||||
#else
|
||||
/* If this assertion fails, either upgrade the bootloader or enable CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS */
|
||||
assert(rtc_clk_xtal_freq_get() != RTC_XTAL_FREQ_AUTO);
|
||||
assert(rtc_clk_xtal_freq_get() != SOC_XTAL_FREQ_AUTO);
|
||||
#endif
|
||||
|
||||
bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled();
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ static const char *TAG = "clk";
|
|||
}
|
||||
rtc_init(cfg);
|
||||
|
||||
assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
|
||||
assert(rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M);
|
||||
|
||||
bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled();
|
||||
rtc_clk_8m_enable(true, rc_fast_d256_is_enabled);
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ static const char *TAG = "clk";
|
|||
pmu_init();
|
||||
#endif
|
||||
|
||||
assert((rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M) || (rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_48M));
|
||||
assert((rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M) || (rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_48M));
|
||||
|
||||
modem_lpcon_ll_set_pwr_tick_target(&MODEM_LPCON, rtc_clk_xtal_freq_get() - 1);
|
||||
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ static const char *TAG = "clk";
|
|||
esp_ocode_calib_init();
|
||||
}
|
||||
|
||||
assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
|
||||
assert(rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M);
|
||||
|
||||
rtc_clk_8m_enable(true);
|
||||
rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ static const char *TAG = "clk";
|
|||
#if !CONFIG_IDF_ENV_FPGA
|
||||
pmu_init();
|
||||
|
||||
assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_32M);
|
||||
assert(rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_32M);
|
||||
|
||||
rtc_clk_8m_enable(true);
|
||||
rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ static const char *TAG = "clk";
|
|||
pmu_init();
|
||||
#endif //SOC_PMU_SUPPORTED
|
||||
|
||||
assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
|
||||
assert(rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M);
|
||||
|
||||
rtc_clk_8m_enable(true);
|
||||
rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
|
|||
}
|
||||
rtc_init(cfg);
|
||||
|
||||
assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
|
||||
assert(rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M);
|
||||
|
||||
bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled();
|
||||
rtc_clk_8m_enable(true, rc_fast_d256_is_enabled);
|
||||
|
|
|
|||
|
|
@ -6,7 +6,6 @@
|
|||
|
||||
#include "hal/clk_tree_hal.h"
|
||||
#include "hal/clk_tree_ll.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/log.h"
|
||||
|
||||
|
|
@ -89,7 +88,7 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
|
|||
{
|
||||
uint32_t freq = clk_ll_xtal_load_freq_mhz();
|
||||
if (freq == 0) {
|
||||
return (uint32_t)RTC_XTAL_FREQ_AUTO;
|
||||
return (uint32_t)SOC_XTAL_FREQ_AUTO;
|
||||
}
|
||||
return freq;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -9,7 +9,6 @@
|
|||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/rtc_io_reg.h"
|
||||
#include "soc/dport_reg.h"
|
||||
|
|
@ -73,6 +72,10 @@ extern "C" {
|
|||
#define CLK_LL_XTAL_32K_BOOTSTRAP_DRES_VAL 3
|
||||
#define CLK_LL_XTAL_32K_BOOTSTRAP_DBIAS_VAL 0
|
||||
|
||||
/* RC_FAST clock enable/disable wait time */
|
||||
#define CLK_LL_RC_FAST_WAIT_DEFAULT 20
|
||||
#define CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT 5
|
||||
|
||||
/* APLL multiplier output frequency range */
|
||||
// apll_multiplier_out = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)
|
||||
#define CLK_LL_APLL_MULTIPLIER_MIN_HZ (350000000) // 350 MHz
|
||||
|
|
@ -275,7 +278,7 @@ static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void
|
|||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
|
||||
{
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -284,7 +287,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
|
|||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
|
||||
{
|
||||
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_WAIT_DEFAULT);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -449,7 +452,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
if (pll_freq_mhz == CLK_LL_PLL_320M_FREQ_MHZ) {
|
||||
/* Configure 320M PLL */
|
||||
switch (xtal_freq_mhz) {
|
||||
case RTC_XTAL_FREQ_40M:
|
||||
case SOC_XTAL_FREQ_40M:
|
||||
div_ref = 0;
|
||||
div7_0 = 32;
|
||||
div10_8 = 0;
|
||||
|
|
@ -457,7 +460,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
dcur = 6;
|
||||
bw = 3;
|
||||
break;
|
||||
case RTC_XTAL_FREQ_26M:
|
||||
case SOC_XTAL_FREQ_26M:
|
||||
div_ref = 12;
|
||||
div7_0 = 224;
|
||||
div10_8 = 4;
|
||||
|
|
@ -465,7 +468,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
dcur = 0;
|
||||
bw = 1;
|
||||
break;
|
||||
case RTC_XTAL_FREQ_24M:
|
||||
case SOC_XTAL_FREQ_24M:
|
||||
div_ref = 11;
|
||||
div7_0 = 224;
|
||||
div10_8 = 4;
|
||||
|
|
@ -487,7 +490,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
} else {
|
||||
/* Configure 480M PLL */
|
||||
switch (xtal_freq_mhz) {
|
||||
case RTC_XTAL_FREQ_40M:
|
||||
case SOC_XTAL_FREQ_40M:
|
||||
div_ref = 0;
|
||||
div7_0 = 28;
|
||||
div10_8 = 0;
|
||||
|
|
@ -495,7 +498,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
dcur = 6;
|
||||
bw = 3;
|
||||
break;
|
||||
case RTC_XTAL_FREQ_26M:
|
||||
case SOC_XTAL_FREQ_26M:
|
||||
div_ref = 12;
|
||||
div7_0 = 144;
|
||||
div10_8 = 4;
|
||||
|
|
@ -503,7 +506,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
dcur = 0;
|
||||
bw = 1;
|
||||
break;
|
||||
case RTC_XTAL_FREQ_24M:
|
||||
case SOC_XTAL_FREQ_24M:
|
||||
div_ref = 11;
|
||||
div7_0 = 144;
|
||||
div10_8 = 4;
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -7,7 +7,6 @@
|
|||
#pragma once
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "clk_tree_ll.h"
|
||||
#include "esp_rom_sys.h"
|
||||
|
|
@ -106,12 +105,6 @@ FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
|
|||
return t;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us)
|
||||
{
|
||||
uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG);
|
||||
return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
|
||||
{
|
||||
return REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_CAUSE);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -9,7 +9,6 @@
|
|||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/system_reg.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "hal/regi2c_ctrl.h"
|
||||
|
|
@ -33,6 +32,10 @@ extern "C" {
|
|||
|
||||
#define CLK_LL_AHB_MAX_FREQ_MHZ CLK_LL_PLL_40M_FREQ_MHZ
|
||||
|
||||
/* RC_FAST clock enable/disable wait time */
|
||||
#define CLK_LL_RC_FAST_WAIT_DEFAULT 20
|
||||
#define CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT 5
|
||||
|
||||
/**
|
||||
* @brief XTAL32K_CLK enable modes
|
||||
*/
|
||||
|
|
@ -65,7 +68,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
|
|||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
|
||||
{
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -74,7 +77,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
|
|||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
|
||||
{
|
||||
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_WAIT_DEFAULT);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -238,7 +241,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
|
||||
/* Configure 480M PLL */
|
||||
switch (xtal_freq_mhz) {
|
||||
case RTC_XTAL_FREQ_26M:
|
||||
case SOC_XTAL_FREQ_26M:
|
||||
div_ref = 12;
|
||||
div7_0 = 236;
|
||||
dr1 = 4;
|
||||
|
|
@ -247,7 +250,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
dcur = 0;
|
||||
dbias = 2;
|
||||
break;
|
||||
case RTC_XTAL_FREQ_32M:
|
||||
case SOC_XTAL_FREQ_32M:
|
||||
div_ref = 0;
|
||||
div7_0 = 11;
|
||||
dr1 = 0;
|
||||
|
|
@ -256,7 +259,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
dcur = 3;
|
||||
dbias = 2;
|
||||
break;
|
||||
case RTC_XTAL_FREQ_40M:
|
||||
case SOC_XTAL_FREQ_40M:
|
||||
default:
|
||||
div_ref = 0;
|
||||
div7_0 = 8;
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -7,7 +7,6 @@
|
|||
#pragma once
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/syscon_reg.h"
|
||||
#include "esp_attr.h"
|
||||
|
|
@ -74,12 +73,6 @@ FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
|
|||
return t;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us)
|
||||
{
|
||||
uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG);
|
||||
return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
|
||||
{
|
||||
return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE);
|
||||
|
|
|
|||
|
|
@ -6,7 +6,6 @@
|
|||
|
||||
#include "hal/clk_tree_hal.h"
|
||||
#include "hal/clk_tree_ll.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/log.h"
|
||||
|
||||
|
|
@ -77,7 +76,7 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
|
|||
uint32_t freq = clk_ll_xtal_load_freq_mhz();
|
||||
if (freq == 0) {
|
||||
HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
|
||||
return (uint32_t)RTC_XTAL_FREQ_40M;
|
||||
return (uint32_t)SOC_XTAL_FREQ_40M;
|
||||
}
|
||||
return freq;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -9,7 +9,6 @@
|
|||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/system_reg.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "hal/regi2c_ctrl.h"
|
||||
|
|
@ -32,6 +31,10 @@ extern "C" {
|
|||
|
||||
#define CLK_LL_AHB_MAX_FREQ_MHZ CLK_LL_PLL_80M_FREQ_MHZ
|
||||
|
||||
/* RC_FAST clock enable/disable wait time */
|
||||
#define CLK_LL_RC_FAST_WAIT_DEFAULT 20
|
||||
#define CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT 5
|
||||
|
||||
#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \
|
||||
.dac = 3, \
|
||||
.dres = 3, \
|
||||
|
|
@ -131,7 +134,7 @@ static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void
|
|||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
|
||||
{
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -140,7 +143,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
|
|||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
|
||||
{
|
||||
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_WAIT_DEFAULT);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -311,7 +314,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
if (pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) {
|
||||
/* Configure 480M PLL */
|
||||
switch (xtal_freq_mhz) {
|
||||
case RTC_XTAL_FREQ_40M:
|
||||
case SOC_XTAL_FREQ_40M:
|
||||
div_ref = 0;
|
||||
div7_0 = 8;
|
||||
dr1 = 0;
|
||||
|
|
@ -320,7 +323,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
dcur = 3;
|
||||
dbias = 2;
|
||||
break;
|
||||
case RTC_XTAL_FREQ_32M:
|
||||
case SOC_XTAL_FREQ_32M:
|
||||
div_ref = 1;
|
||||
div7_0 = 26;
|
||||
dr1 = 1;
|
||||
|
|
@ -343,7 +346,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
} else {
|
||||
/* Configure 320M PLL */
|
||||
switch (xtal_freq_mhz) {
|
||||
case RTC_XTAL_FREQ_40M:
|
||||
case SOC_XTAL_FREQ_40M:
|
||||
div_ref = 0;
|
||||
div7_0 = 4;
|
||||
dr1 = 0;
|
||||
|
|
@ -352,7 +355,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
dcur = 3;
|
||||
dbias = 2;
|
||||
break;
|
||||
case RTC_XTAL_FREQ_32M:
|
||||
case SOC_XTAL_FREQ_32M:
|
||||
div_ref = 1;
|
||||
div7_0 = 6;
|
||||
dr1 = 0;
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -7,7 +7,6 @@
|
|||
#pragma once
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/syscon_reg.h"
|
||||
#include "esp_attr.h"
|
||||
|
|
@ -80,12 +79,6 @@ FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
|
|||
return t;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us)
|
||||
{
|
||||
uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG);
|
||||
return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
|
||||
{
|
||||
return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE);
|
||||
|
|
|
|||
|
|
@ -6,7 +6,6 @@
|
|||
|
||||
#include "hal/clk_tree_hal.h"
|
||||
#include "hal/clk_tree_ll.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/log.h"
|
||||
|
||||
|
|
@ -72,7 +71,7 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
|
|||
uint32_t freq = clk_ll_xtal_load_freq_mhz();
|
||||
if (freq == 0) {
|
||||
HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
|
||||
return (uint32_t)RTC_XTAL_FREQ_40M;
|
||||
return (uint32_t)SOC_XTAL_FREQ_40M;
|
||||
}
|
||||
return freq;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -9,7 +9,6 @@
|
|||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/pcr_struct.h"
|
||||
#include "soc/lp_clkrst_struct.h"
|
||||
#include "soc/pmu_reg.h"
|
||||
|
|
@ -309,7 +308,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
uint8_t lref = 1;
|
||||
/* Configure 480M PLL */
|
||||
switch (xtal_freq_mhz) {
|
||||
case RTC_XTAL_FREQ_40M:
|
||||
case SOC_XTAL_FREQ_40M:
|
||||
div_ref = 1;
|
||||
div7_0 = 12;
|
||||
dr1 = 0;
|
||||
|
|
@ -317,7 +316,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
dchgp = 5;
|
||||
dbias = 2;
|
||||
break;
|
||||
case RTC_XTAL_FREQ_48M:
|
||||
case SOC_XTAL_FREQ_48M:
|
||||
div_ref = 1;
|
||||
div7_0 = 10;
|
||||
dr1 = 1;
|
||||
|
|
|
|||
|
|
@ -6,7 +6,6 @@
|
|||
|
||||
#include "hal/clk_tree_hal.h"
|
||||
#include "hal/clk_tree_ll.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/log.h"
|
||||
|
||||
|
|
@ -70,7 +69,7 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
|
|||
uint32_t freq = clk_ll_xtal_load_freq_mhz();
|
||||
if (freq == 0) {
|
||||
HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
|
||||
return (uint32_t)RTC_XTAL_FREQ_40M;
|
||||
return (uint32_t)SOC_XTAL_FREQ_40M;
|
||||
}
|
||||
return freq;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -9,7 +9,6 @@
|
|||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/pcr_struct.h"
|
||||
#include "soc/lp_clkrst_struct.h"
|
||||
#include "soc/pmu_reg.h"
|
||||
|
|
@ -307,7 +306,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
|
||||
/* Configure 480M PLL */
|
||||
switch (xtal_freq_mhz) {
|
||||
case RTC_XTAL_FREQ_40M:
|
||||
case SOC_XTAL_FREQ_40M:
|
||||
default:
|
||||
div_ref = 0;
|
||||
div7_0 = 8;
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -9,8 +9,8 @@
|
|||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/lp_timer_struct.h"
|
||||
#include "soc/lp_timer_reg.h"
|
||||
#include "soc/lp_aon_reg.h"
|
||||
|
|
@ -72,12 +72,6 @@ FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_intsts_mask(lp_timer_dev_t *dev, uin
|
|||
dev->lp_int_clr.val = mask;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint64_t lp_timer_ll_time_to_count(uint64_t time_in_us)
|
||||
{
|
||||
uint32_t slow_clk_value = REG_READ(LP_AON_STORE1_REG);
|
||||
return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -6,7 +6,6 @@
|
|||
|
||||
#include "hal/clk_tree_hal.h"
|
||||
#include "hal/clk_tree_ll.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/log.h"
|
||||
|
||||
|
|
@ -70,7 +69,7 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
|
|||
uint32_t freq = clk_ll_xtal_load_freq_mhz();
|
||||
if (freq == 0) {
|
||||
HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 32MHz");
|
||||
return (uint32_t)RTC_XTAL_FREQ_32M;
|
||||
return (uint32_t)SOC_XTAL_FREQ_32M;
|
||||
}
|
||||
return freq;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -9,7 +9,6 @@
|
|||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/pcr_struct.h"
|
||||
#include "soc/lp_clkrst_struct.h"
|
||||
#include "soc/pmu_reg.h"
|
||||
|
|
@ -305,7 +304,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_freq_mhz(uint
|
|||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32_t pll_freq_mhz, uint32_t xtal_freq_mhz)
|
||||
{
|
||||
HAL_ASSERT(xtal_freq_mhz == RTC_XTAL_FREQ_32M);
|
||||
HAL_ASSERT(xtal_freq_mhz == SOC_XTAL_FREQ_32M);
|
||||
HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_96M_FREQ_MHZ);
|
||||
uint8_t oc_ref_div;
|
||||
uint8_t oc_div;
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -9,8 +9,8 @@
|
|||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/lp_timer_struct.h"
|
||||
#include "soc/lp_aon_reg.h"
|
||||
#include "hal/lp_timer_types.h"
|
||||
|
|
@ -56,12 +56,6 @@ FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *de
|
|||
dev->int_clr.overflow = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint64_t lp_timer_ll_time_to_count(uint64_t time_in_us)
|
||||
{
|
||||
uint32_t slow_clk_value = REG_READ(LP_AON_STORE1_REG);
|
||||
return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -6,7 +6,6 @@
|
|||
|
||||
#include "hal/clk_tree_hal.h"
|
||||
#include "hal/clk_tree_ll.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/log.h"
|
||||
|
||||
|
|
@ -76,7 +75,7 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
|
|||
uint32_t freq = clk_ll_xtal_load_freq_mhz();
|
||||
if (freq == 0) {
|
||||
HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
|
||||
return (uint32_t)RTC_XTAL_FREQ_40M;
|
||||
return (uint32_t)SOC_XTAL_FREQ_40M;
|
||||
}
|
||||
return freq;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -9,7 +9,6 @@
|
|||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/hp_sys_clkrst_reg.h"
|
||||
#include "soc/hp_sys_clkrst_struct.h"
|
||||
#include "soc/lp_clkrst_struct.h"
|
||||
|
|
@ -337,7 +336,7 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_set_config(uint32_
|
|||
uint8_t oc_enb_fcal = 0;
|
||||
|
||||
// Currently, only supporting 40MHz XTAL
|
||||
HAL_ASSERT(xtal_freq_mhz == RTC_XTAL_FREQ_40M);
|
||||
HAL_ASSERT(xtal_freq_mhz == SOC_XTAL_FREQ_40M);
|
||||
switch (cpll_freq_mhz) {
|
||||
case CLK_LL_PLL_400M_FREQ_MHZ:
|
||||
/* Configure 400M CPLL */
|
||||
|
|
@ -381,7 +380,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_mpll_get_freq_mhz(u
|
|||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_mpll_set_config(uint32_t mpll_freq_mhz, uint32_t xtal_freq_mhz)
|
||||
{
|
||||
HAL_ASSERT(xtal_freq_mhz == RTC_XTAL_FREQ_40M);
|
||||
HAL_ASSERT(xtal_freq_mhz == SOC_XTAL_FREQ_40M);
|
||||
|
||||
// MPLL_Freq = XTAL_Freq * (div + 1) / (ref_div + 1)
|
||||
uint8_t ref_div = 1;
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -9,8 +9,8 @@
|
|||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/lp_timer_struct.h"
|
||||
#include "soc/lp_timer_reg.h"
|
||||
#include "soc/lp_system_reg.h"
|
||||
|
|
@ -72,12 +72,6 @@ FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_intsts_mask(lp_timer_dev_t *dev, uin
|
|||
dev->lp_int_clr.val = mask;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint64_t lp_timer_ll_time_to_count(uint64_t time_in_us)
|
||||
{
|
||||
uint32_t slow_clk_value = REG_READ(LP_SYSTEM_REG_LP_STORE1_REG);
|
||||
return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -9,7 +9,6 @@
|
|||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/dport_reg.h"
|
||||
#include "soc/syscon_reg.h"
|
||||
|
|
@ -35,7 +34,11 @@ extern "C" {
|
|||
#define CLK_LL_AHB_MAX_FREQ_MHZ CLK_LL_PLL_80M_FREQ_MHZ
|
||||
|
||||
// ESP32S2 only supports 40MHz crystal
|
||||
#define CLK_LL_XTAL_FREQ_MHZ (40)
|
||||
#define CLK_LL_XTAL_FREQ_MHZ (SOC_XTAL_FREQ_40M)
|
||||
|
||||
/* RC_FAST clock enable/disable wait time */
|
||||
#define CLK_LL_RC_FAST_WAIT_DEFAULT 20
|
||||
#define CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT 5
|
||||
|
||||
/* APLL configuration parameters */
|
||||
#define CLK_LL_APLL_SDM_STOP_VAL_1 0x09
|
||||
|
|
@ -227,7 +230,7 @@ static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void
|
|||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
|
||||
{
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -236,7 +239,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
|
|||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
|
||||
{
|
||||
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_WAIT_DEFAULT);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -7,7 +7,6 @@
|
|||
#pragma once
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/assert.h"
|
||||
|
|
@ -94,12 +93,6 @@ FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
|
|||
return t;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us)
|
||||
{
|
||||
uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG);
|
||||
return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
|
||||
{
|
||||
return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE);
|
||||
|
|
|
|||
|
|
@ -6,7 +6,6 @@
|
|||
|
||||
#include "hal/clk_tree_hal.h"
|
||||
#include "hal/clk_tree_ll.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "hal/assert.h"
|
||||
#include "hal/log.h"
|
||||
|
||||
|
|
@ -85,7 +84,7 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
|
|||
uint32_t freq = clk_ll_xtal_load_freq_mhz();
|
||||
if (freq == 0) {
|
||||
HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
|
||||
return (uint32_t)RTC_XTAL_FREQ_40M;
|
||||
return (uint32_t)SOC_XTAL_FREQ_40M;
|
||||
}
|
||||
return freq;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -9,7 +9,6 @@
|
|||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/system_reg.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/regi2c_defs.h"
|
||||
|
|
@ -34,6 +33,10 @@ extern "C" {
|
|||
|
||||
#define CLK_LL_AHB_MAX_FREQ_MHZ CLK_LL_PLL_80M_FREQ_MHZ
|
||||
|
||||
/* RC_FAST clock enable/disable wait time */
|
||||
#define CLK_LL_RC_FAST_WAIT_DEFAULT 20
|
||||
#define CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT 5
|
||||
|
||||
#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \
|
||||
.dac = 3, \
|
||||
.dres = 3, \
|
||||
|
|
@ -133,7 +136,7 @@ static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void
|
|||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
|
||||
{
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -142,7 +145,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
|
|||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
|
||||
{
|
||||
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
|
||||
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_WAIT_DEFAULT);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -313,7 +316,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
if (pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) {
|
||||
/* Configure 480M PLL */
|
||||
switch (xtal_freq_mhz) {
|
||||
case RTC_XTAL_FREQ_40M:
|
||||
case SOC_XTAL_FREQ_40M:
|
||||
div_ref = 0;
|
||||
div7_0 = 8;
|
||||
dr1 = 0;
|
||||
|
|
@ -322,7 +325,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
dcur = 3;
|
||||
dbias = 2;
|
||||
break;
|
||||
case RTC_XTAL_FREQ_32M:
|
||||
case SOC_XTAL_FREQ_32M:
|
||||
div_ref = 1;
|
||||
div7_0 = 26;
|
||||
dr1 = 1;
|
||||
|
|
@ -345,7 +348,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
} else {
|
||||
/* Configure 320M PLL */
|
||||
switch (xtal_freq_mhz) {
|
||||
case RTC_XTAL_FREQ_40M:
|
||||
case SOC_XTAL_FREQ_40M:
|
||||
div_ref = 0;
|
||||
div7_0 = 4;
|
||||
dr1 = 0;
|
||||
|
|
@ -354,7 +357,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
|
|||
dcur = 3;
|
||||
dbias = 2;
|
||||
break;
|
||||
case RTC_XTAL_FREQ_32M:
|
||||
case SOC_XTAL_FREQ_32M:
|
||||
div_ref = 1;
|
||||
div7_0 = 6;
|
||||
dr1 = 0;
|
||||
|
|
@ -687,15 +690,15 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(v
|
|||
* @brief Configure PLL frequency for MSPI timing tuning
|
||||
* @note Only used by the MSPI Timing tuning driver
|
||||
*
|
||||
* @param xtal_freq Xtal frequency
|
||||
* @param xtal_freq XTAL frequency
|
||||
* @param pll_freq PLL frequency
|
||||
* @param oc_div OC divider
|
||||
* @param oc_ref_div OC ref divider
|
||||
*/
|
||||
static inline __attribute__((always_inline))
|
||||
void clk_ll_bbpll_set_frequency_for_mspi_tuning(rtc_xtal_freq_t xtal_freq, int pll_freq, uint8_t oc_div, uint8_t oc_ref_div)
|
||||
void clk_ll_bbpll_set_frequency_for_mspi_tuning(soc_xtal_freq_t xtal_freq, int pll_freq, uint8_t oc_div, uint8_t oc_ref_div)
|
||||
{
|
||||
HAL_ASSERT(xtal_freq == RTC_XTAL_FREQ_40M);
|
||||
HAL_ASSERT(xtal_freq == SOC_XTAL_FREQ_40M);
|
||||
uint32_t pll_reg = GET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD |
|
||||
RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
|
||||
HAL_ASSERT(pll_reg == 0);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -7,7 +7,6 @@
|
|||
#pragma once
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/syscon_reg.h"
|
||||
#include "esp_attr.h"
|
||||
|
|
@ -175,12 +174,6 @@ FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
|
|||
return t;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us)
|
||||
{
|
||||
uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG);
|
||||
return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
|
||||
{
|
||||
return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -91,6 +91,19 @@ typedef enum {
|
|||
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
|
||||
} soc_rtc_fast_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency options on the target
|
||||
* @note Enum values equal to the frequency value in MHz
|
||||
* @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for
|
||||
* the supported ones.
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_XTAL_FREQ_AUTO = 0, /*!< Automatic XTAL frequency detention */
|
||||
SOC_XTAL_FREQ_24M = 24, /*!< 24MHz XTAL */
|
||||
SOC_XTAL_FREQ_26M = 26, /*!< 26MHz XTAL */
|
||||
SOC_XTAL_FREQ_40M = 40, /*!< 40MHz XTAL */
|
||||
} soc_xtal_freq_t;
|
||||
|
||||
// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
|
||||
// {[upstream]clock_name}: APB, APLL, (BB)PLL, etc.
|
||||
// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -87,6 +87,18 @@ typedef enum {
|
|||
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
|
||||
} soc_rtc_fast_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency options on the target
|
||||
* @note Enum values equal to the frequency value in MHz
|
||||
* @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for
|
||||
* the supported ones.
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_XTAL_FREQ_26M = 26, /*!< 26MHz XTAL */
|
||||
SOC_XTAL_FREQ_32M = 32, /*!< 32MHz XTAL */
|
||||
SOC_XTAL_FREQ_40M = 40, /*!< 40MHz XTAL */
|
||||
} soc_xtal_freq_t;
|
||||
|
||||
// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
|
||||
// {[upstream]clock_name}: (BB)PLL etc.
|
||||
// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -88,6 +88,17 @@ typedef enum {
|
|||
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
|
||||
} soc_rtc_fast_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency options on the target
|
||||
* @note Enum values equal to the frequency value in MHz
|
||||
* @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for
|
||||
* the supported ones.
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_XTAL_FREQ_32M = 32, /*!< 32MHz XTAL */
|
||||
SOC_XTAL_FREQ_40M = 40, /*!< 40MHz XTAL */
|
||||
} soc_xtal_freq_t;
|
||||
|
||||
// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
|
||||
// {[upstream]clock_name}: APB, (BB)PLL, etc.
|
||||
// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -104,6 +104,17 @@ typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6)
|
|||
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
|
||||
} soc_rtc_fast_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency options on the target
|
||||
* @note Enum values equal to the frequency value in MHz
|
||||
* @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for
|
||||
* the supported ones.
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_XTAL_FREQ_40M = 40, /*!< 40MHz XTAL */
|
||||
SOC_XTAL_FREQ_48M = 48, /*!< 48MHz XTAL */
|
||||
} soc_xtal_freq_t;
|
||||
|
||||
// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
|
||||
// {[upstream]clock_name}: XTAL, (BB)PLL, etc.
|
||||
// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -100,6 +100,16 @@ typedef enum {
|
|||
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
|
||||
} soc_rtc_fast_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency options on the target
|
||||
* @note Enum values equal to the frequency value in MHz
|
||||
* @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for
|
||||
* the supported ones.
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_XTAL_FREQ_40M = 40, /*!< 40MHz XTAL */
|
||||
} soc_xtal_freq_t;
|
||||
|
||||
// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
|
||||
// {[upstream]clock_name}: XTAL, (BB)PLL, etc.
|
||||
// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -112,6 +112,16 @@ typedef enum {
|
|||
SOC_LP_PLL_CLK_SRC_INVALID, /*!< Invalid LP_PLL_CLK source */
|
||||
} soc_lp_pll_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency options on the target
|
||||
* @note Enum values equal to the frequency value in MHz
|
||||
* @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for
|
||||
* the supported ones.
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_XTAL_FREQ_32M = 32, /*!< 32MHz XTAL */
|
||||
} soc_xtal_freq_t;
|
||||
|
||||
// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
|
||||
// {[upstream]clock_name}: XTAL, (BB)PLL, etc.
|
||||
// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
|
||||
|
|
|
|||
|
|
@ -118,6 +118,16 @@ typedef enum {
|
|||
SOC_LP_PLL_CLK_SRC_INVALID, /*!< Invalid LP_PLL_CLK source */
|
||||
} soc_lp_pll_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency options on the target
|
||||
* @note Enum values equal to the frequency value in MHz
|
||||
* @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for
|
||||
* the supported ones.
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_XTAL_FREQ_40M = 40, /*!< 40MHz XTAL */
|
||||
} soc_xtal_freq_t;
|
||||
|
||||
// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
|
||||
// {[upstream]clock_name}: XTAL, (S/M/A)PLL, etc.
|
||||
// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -89,6 +89,16 @@ typedef enum {
|
|||
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
|
||||
} soc_rtc_fast_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency options on the target
|
||||
* @note Enum values equal to the frequency value in MHz
|
||||
* @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for
|
||||
* the supported ones.
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_XTAL_FREQ_40M = 40, /*!< 40MHz XTAL */
|
||||
} soc_xtal_freq_t;
|
||||
|
||||
// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
|
||||
// {[upstream]clock_name}: APB, APLL, (BB)PLL, etc.
|
||||
// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -88,6 +88,17 @@ typedef enum {
|
|||
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
|
||||
} soc_rtc_fast_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency options on the target
|
||||
* @note Enum values equal to the frequency value in MHz
|
||||
* @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for
|
||||
* the supported ones.
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_XTAL_FREQ_32M = 32, /*!< 32MHz XTAL */
|
||||
SOC_XTAL_FREQ_40M = 40, /*!< 40MHz XTAL */
|
||||
} soc_xtal_freq_t;
|
||||
|
||||
// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
|
||||
// {[upstream]clock_name}: APB, (BB)PLL, etc.
|
||||
// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@
|
|||
*/
|
||||
#include "ulp_lp_core_lp_timer_shared.h"
|
||||
#include "hal/lp_timer_ll.h"
|
||||
#include "hal/clk_tree_ll.h"
|
||||
#include "soc/rtc.h"
|
||||
|
||||
#define TIMER_ID 1
|
||||
|
||||
|
|
@ -39,7 +41,7 @@ static uint64_t lp_timer_hal_get_cycle_count(void)
|
|||
void ulp_lp_core_lp_timer_set_wakeup_time(uint64_t sleep_duration_us)
|
||||
{
|
||||
uint64_t cycle_cnt = lp_timer_hal_get_cycle_count();
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||||
uint64_t alarm_target = cycle_cnt + lp_timer_ll_time_to_count(sleep_duration_us);
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||||
uint64_t alarm_target = cycle_cnt + sleep_duration_us * (1 << RTC_CLK_CAL_FRACT) / clk_ll_rtc_slow_load_cal();
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||||
|
||||
lp_timer_hal_set_alarm_target(alarm_target);
|
||||
}
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||||
|
|
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|||
Ładowanie…
Reference in New Issue