kopia lustrzana https://github.com/espressif/esp-idf
84 wiersze
3.1 KiB
C
84 wiersze
3.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <stddef.h>
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#include <stdlib.h>
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#include "esp32h2/rom/ets_sys.h"
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#include "esp32h2/rom/rtc.h"
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#include "esp32h2/rom/uart.h"
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#include "soc/rtc.h"
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#include "esp_cpu.h"
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#include "regi2c_ctrl.h"
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#include "soc/lp_clkrst_reg.h"
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#include "soc/regi2c_pmu.h"
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#include "esp_hw_log.h"
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#include "sdkconfig.h"
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#include "esp_rom_uart.h"
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#include "hal/clk_tree_ll.h"
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#include "soc/pmu_reg.h"
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#include "pmu_param.h"
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static const char *TAG = "rtc_clk_init";
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void rtc_clk_init(rtc_clk_config_t cfg)
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{
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rtc_cpu_freq_config_t old_config, new_config;
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/* Set tuning parameters for RC_FAST, RC_SLOW, and RC32K clocks.
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* Note: this doesn't attempt to set the clocks to precise frequencies.
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* Instead, we calibrate these clocks against XTAL frequency later, when necessary.
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* - SCK_DCAP value controls tuning of RC_SLOW clock.
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* The higher the value of DCAP is, the lower is the frequency.
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* - CK8M_DFREQ value controls tuning of RC_FAST clock.
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* CLK_8M_DFREQ constant gives the best temperature characteristics.
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* - RC32K_DFREQ value controls tuning of RC32K clock.
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*/
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REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, cfg.clk_8m_dfreq);
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REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OC_SCK_DCAP, cfg.slow_clk_dcap);
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REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, cfg.rc32k_dfreq);
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REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG, 0);
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REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG, 0);
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REG_SET_FIELD(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, HP_CALI_DBIAS);
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REG_SET_FIELD(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, LP_CALI_DBIAS);
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clk_ll_rc_fast_tick_conf();
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soc_xtal_freq_t xtal_freq = cfg.xtal_freq;
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esp_rom_output_tx_wait_idle(0);
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rtc_clk_xtal_freq_update(xtal_freq);
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/* Set CPU frequency */
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rtc_clk_cpu_freq_get_config(&old_config);
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uint32_t freq_before = old_config.freq_mhz;
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bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config);
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if (!res) {
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ESP_HW_LOGE(TAG, "invalid CPU frequency value");
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abort();
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}
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rtc_clk_cpu_freq_set_config(&new_config);
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/* Re-calculate the ccount to make time calculation correct. */
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esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * cfg.cpu_freq_mhz / freq_before );
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/* Slow & fast clocks setup */
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// We will not power off RC_FAST in bootloader stage even if it is not being used as any
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// cpu / rtc_fast / rtc_slow clock sources, this is because RNG always needs it in the bootloader stage.
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bool need_rc_fast_en = true;
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if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
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rtc_clk_32k_enable(true);
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} else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
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rtc_clk_32k_enable_external();
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} else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
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rtc_clk_rc32k_enable(true);
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}
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rtc_clk_8m_enable(need_rc_fast_en);
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rtc_clk_fast_src_set(cfg.fast_clk_src);
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rtc_clk_slow_src_set(cfg.slow_clk_src);
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}
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