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feat(gpio): support GPIO on ESP32C61

master
laokaiyao 2024-04-22 16:35:00 +08:00
rodzic 5bac46d996
commit 2c90b71d45
16 zmienionych plików z 367 dodań i 1445 usunięć
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3
components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
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@ -860,8 +860,7 @@ TEST_CASE("GPIO_USB_DP_pin_pullup_disable_test", "[gpio]")
}
#endif //SOC_USB_SERIAL_JTAG_SUPPORTED
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C5)
// TODO: IDF-8638 Remove when light sleep is supported on ESP32C5
#if SOC_LIGHT_SLEEP_SUPPORTED
// Ignored in CI because it needs manually connect TEST_GPIO_INPUT_LEVEL_LOW_PIN to 3.3v to wake up from light sleep
TEST_CASE("GPIO_light_sleep_wake_up_test", "[gpio][ignore]")
{

6
components/esp_rom/include/esp32c61/rom/gpio.h
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@ -28,8 +28,8 @@ extern "C" {
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4)
#define GPIO_FUNC_IN_HIGH 0x38
#define GPIO_FUNC_IN_LOW 0x3C
#define GPIO_FUNC_IN_HIGH 0x20
#define GPIO_FUNC_IN_LOW 0x30
#define GPIO_ID_IS_PIN_REGISTER(reg_id) \
((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1)))
@ -57,7 +57,7 @@ typedef enum {
*
* @param uint32_t enable_mask : the gpios that need be changed.
*
* @param uint32_t disable_mask : the gpios that need diable output.
* @param uint32_t disable_mask : the gpios that need disable output.
*
* @return None
*/

114
components/hal/esp32c61/include/hal/gpio_ll.h
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@ -20,17 +20,14 @@
#include "soc/gpio_periph.h"
#include "soc/gpio_struct.h"
#include "soc/lp_aon_struct.h"
#include "soc/lp_gpio_struct.h"
#include "soc/pmu_struct.h"
#include "soc/usb_serial_jtag_reg.h"
#include "soc/pcr_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/usb_serial_jtag_struct.h"
#include "soc/io_mux_struct.h"
#include "hal/gpio_types.h"
#include "hal/misc.h"
#include "hal/assert.h"
// TODO: [ESP32C61] IDF-9316, inherit from c6
#ifdef __cplusplus
extern "C" {
#endif
@ -60,17 +57,15 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv,
uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel)
{
uint32_t bit_mask = 1 << gpio_num;
uint32_t iomux_reg_val = REG_READ(GPIO_PIN_MUX_REG[gpio_num]);
*pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S;
*pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S;
*ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S;
*oe = (hw->enable.val & bit_mask) >> gpio_num;
*pu = IOMUX.gpion[gpio_num].gpion_fun_wpu;
*pd = IOMUX.gpion[gpio_num].gpion_fun_wpd;
*ie = IOMUX.gpion[gpio_num].gpion_fun_ie;
*oe = (hw->enable.val & (1 << gpio_num)) >> gpio_num;
*od = hw->pinn[gpio_num].pinn_pad_driver;
*drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S;
*fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
*drv = IOMUX.gpion[gpio_num].gpion_fun_drv;
*fun_sel = IOMUX.gpion[gpio_num].gpion_mcu_sel;
*sig_out = hw->funcn_out_sel_cfg[gpio_num].funcn_out_sel;
*slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
*slp_sel = IOMUX.gpion[gpio_num].gpion_slp_sel;
}
/**
@ -81,7 +76,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
*/
static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
{
REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
IOMUX.gpion[gpio_num].gpion_fun_wpu = 1;
}
/**
@ -93,7 +88,7 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
IOMUX.gpion[gpio_num].gpion_fun_wpu = 0;
}
/**
@ -104,7 +99,7 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
{
REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
IOMUX.gpion[gpio_num].gpion_fun_wpd = 1;
}
/**
@ -118,14 +113,14 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
// The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
// Note that esp32c61 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
// Note that esp32C61 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
// if (gpio_num == USB_DP_GPIO_NUM) {
// SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
// CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
// }
REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.exchg_pins_override = 1;
USB_SERIAL_JTAG.conf0.dp_pullup = 0;
}
IOMUX.gpion[gpio_num].gpion_fun_wpd = 0;
}
/**
@ -226,7 +221,7 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpion[gpio_num].gpion_fun_ie = 0;
}
/**
@ -237,7 +232,7 @@ static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpion[gpio_num].gpion_fun_ie = 1;
}
/**
@ -248,7 +243,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_FILTER_EN(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpion[gpio_num].gpion_filter_en = 1;
}
/**
@ -259,7 +254,7 @@ static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_FILTER_DIS(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpion[gpio_num].gpion_filter_en = 0;
}
/**
@ -273,7 +268,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num);
// Ensure no other output signal is routed via GPIO matrix to this pin
REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4), SIG_GPIO_OUT_IDX);
hw->funcn_out_sel_cfg[gpio_num].funcn_out_sel = SIG_GPIO_OUT_IDX;
}
/**
@ -339,6 +334,7 @@ static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t
* - 0 the GPIO input level is 0
* - 1 the GPIO input level is 1
*/
__attribute__((always_inline))
static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num)
{
return (hw->in.in_data_next >> gpio_num) & 0x1;
@ -352,7 +348,7 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
hw->pinn[gpio_num].pinn_wakeup_enable = 0x1;
hw->pinn[gpio_num].pinn_wakeup_enable = 1;
}
/**
@ -375,7 +371,7 @@ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength)
{
SET_PERI_REG_BITS(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, strength, FUN_DRV_S);
IOMUX.gpion[gpio_num].gpion_fun_drv = strength;
}
/**
@ -387,7 +383,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu
*/
static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength)
{
*strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, FUN_DRV_S);
*strength = (gpio_drive_cap_t)(IOMUX.gpion[gpio_num].gpion_fun_drv);
}
/**
@ -398,7 +394,8 @@ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu
*/
static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
{
LP_AON.gpio_hold0.gpio_hold0 |= GPIO_HOLD_MASK[gpio_num];
uint32_t mask = LP_AON.gpio_hold0.gpio_hold0;
LP_AON.gpio_hold0.gpio_hold0 = mask | GPIO_HOLD_MASK[gpio_num];
}
/**
@ -409,7 +406,8 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
LP_AON.gpio_hold0.gpio_hold0 &= ~GPIO_HOLD_MASK[gpio_num];
uint32_t mask = LP_AON.gpio_hold0.gpio_hold0;
LP_AON.gpio_hold0.gpio_hold0 = mask & (~GPIO_HOLD_MASK[gpio_num]);
}
/**
@ -440,8 +438,8 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx)
{
REG_CLR_BIT(GPIO_FUNC0_IN_SEL_CFG_REG + signal_idx * 4, GPIO_SIG0_IN_SEL);
PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio * 4));
hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0;
IOMUX.gpion[gpio].gpion_fun_ie = 1;
}
/**
@ -454,7 +452,7 @@ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
// Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
if (pin_name == IO_MUX_GPIO12_REG || pin_name == IO_MUX_GPIO13_REG) {
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
PIN_FUNC_SELECT(pin_name, func);
}
@ -482,10 +480,10 @@ __attribute__((always_inline))
static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func)
{
// Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
// if (gpio_num == USB_DM_GPIO_NUM || gpio_num == USB_DP_GPIO_NUM) {
// CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
// }
PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
IOMUX.gpion[gpio_num].gpion_mcu_sel = func;
}
/**
@ -513,10 +511,13 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
{
switch (src) {
case SOC_MOD_CLK_XTAL:
PCR.iomux_clk_conf.iomux_func_clk_sel = 3;
PCR.iomux_clk_conf.iomux_func_clk_sel = 0;
break;
case SOC_MOD_CLK_RC_FAST:
PCR.iomux_clk_conf.iomux_func_clk_sel = 1;
break;
case SOC_MOD_CLK_PLL_F80M:
PCR.iomux_clk_conf.iomux_func_clk_sel = 1;
PCR.iomux_clk_conf.iomux_func_clk_sel = 2;
break;
default:
// Unsupported IO_MUX clock source
@ -536,12 +537,9 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
*/
static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in_sig_idx)
{
uint32_t reg_val = REG_READ(GPIO_FUNC0_IN_SEL_CFG_REG + in_sig_idx * 4);
if (reg_val & GPIO_SIG0_IN_SEL) {
return (reg_val & GPIO_FUNC0_IN_SEL_M);
} else {
return -1;
}
gpio_func_in_sel_cfg_reg_t reg;
reg.val = hw->func_in_sel_cfg[in_sig_idx].val;
return (reg.sig_in_sel ? reg.func_in_sel : -1);
}
/**
@ -572,7 +570,7 @@ static inline void gpio_ll_force_unhold_all(void)
*/
static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_SEL_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpion[gpio_num].gpion_slp_sel = 1;
}
/**
@ -584,7 +582,7 @@ static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_SEL_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpion[gpio_num].gpion_slp_sel = 0;
}
/**
@ -595,7 +593,7 @@ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_PULLUP_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpion[gpio_num].gpion_mcu_wpu = 0;
}
/**
@ -606,7 +604,7 @@ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_PULLUP_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpion[gpio_num].gpion_mcu_wpu = 1;
}
/**
@ -617,7 +615,7 @@ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_PULLDOWN_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpion[gpio_num].gpion_mcu_wpd = 1;
}
/**
@ -628,7 +626,7 @@ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_PULLDOWN_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpion[gpio_num].gpion_mcu_wpd = 0;
}
/**
@ -639,7 +637,7 @@ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpion[gpio_num].gpion_mcu_ie = 0;
}
/**
@ -650,7 +648,7 @@ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num
*/
static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpion[gpio_num].gpion_mcu_ie = 1;
}
/**
@ -661,7 +659,7 @@ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_OUTPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpion[gpio_num].gpion_mcu_oe = 0;
}
/**
@ -672,7 +670,7 @@ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_nu
*/
static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
PIN_SLP_OUTPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
IOMUX.gpion[gpio_num].gpion_mcu_oe = 1;
}
#ifdef __cplusplus

6
components/soc/esp32c61/gpio_periph.c
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@ -29,9 +29,6 @@ const uint32_t GPIO_PIN_MUX_REG[] = {
IO_MUX_GPIO19_REG,
IO_MUX_GPIO20_REG,
IO_MUX_GPIO21_REG,
IO_MUX_GPIO22_REG,
IO_MUX_GPIO23_REG,
IO_MUX_GPIO24_REG,
};
_Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG");
@ -59,9 +56,6 @@ const uint32_t GPIO_HOLD_MASK[] = {
BIT(19), //GPIO19
BIT(20), //GPIO20
BIT(21), //GPIO21
BIT(22), //GPIO22
BIT(23), //GPIO23
BIT(24), //GPIO24
};
_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");

20
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
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@ -161,7 +161,7 @@ config SOC_GPIO_PORT
config SOC_GPIO_PIN_COUNT
int
default 25
default 22
config SOC_GPIO_ETM_EVENTS_PER_GROUP
int
@ -189,7 +189,7 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x000000007FFFFF00
default 0x00000000003FFF80
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
@ -575,22 +575,6 @@ config SOC_SHA_SUPPORT_SHA256
bool
default y
config SOC_SDM_GROUPS
int
default 1
config SOC_SDM_CHANNELS_PER_GROUP
int
default 4
config SOC_SDM_CLK_SUPPORT_PLL_F80M
bool
default y
config SOC_SDM_CLK_SUPPORT_XTAL
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 2

4
components/soc/esp32c61/include/soc/gpio_num.h
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@ -6,7 +6,6 @@
#pragma once
//TODO: [ESP32C61] IDF-9316, check pins attribute
#ifdef __cplusplus
extern "C" {
#endif
@ -38,9 +37,6 @@ typedef enum {
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
GPIO_NUM_21 = 21, /*!< GPIO21, input and output */
GPIO_NUM_22 = 22, /*!< GPIO22, NC */
GPIO_NUM_23 = 23, /*!< GPIO23, NC */
GPIO_NUM_24 = 24, /*!< GPIO24, NC */
GPIO_NUM_MAX,
} gpio_num_t;

4
components/soc/esp32c61/include/soc/gpio_pins.h
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@ -11,8 +11,8 @@
extern "C" {
#endif
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C)
#define GPIO_MATRIX_CONST_ONE_INPUT (0x20)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x30)
#ifdef __cplusplus
}

875
components/soc/esp32c61/include/soc/gpio_reg.h
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@ -1844,517 +1844,6 @@ extern "C" {
#define GPIO_PIN21_INT_ENA_V 0x0000001FU
#define GPIO_PIN21_INT_ENA_S 13
/** GPIO_PIN22_REG register
* GPIO22 configuration register
*/
#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0x11c)
/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN22_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN22_SYNC2_BYPASS_M (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S)
#define GPIO_PIN22_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN22_SYNC2_BYPASS_S 0
/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN22_PAD_DRIVER (BIT(2))
#define GPIO_PIN22_PAD_DRIVER_M (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S)
#define GPIO_PIN22_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN22_PAD_DRIVER_S 2
/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN22_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN22_SYNC1_BYPASS_M (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S)
#define GPIO_PIN22_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN22_SYNC1_BYPASS_S 3
/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN22_INT_TYPE 0x00000007U
#define GPIO_PIN22_INT_TYPE_M (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S)
#define GPIO_PIN22_INT_TYPE_V 0x00000007U
#define GPIO_PIN22_INT_TYPE_S 7
/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN22_WAKEUP_ENABLE_M (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S)
#define GPIO_PIN22_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN22_WAKEUP_ENABLE_S 10
/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN22_INT_ENA 0x0000001FU
#define GPIO_PIN22_INT_ENA_M (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S)
#define GPIO_PIN22_INT_ENA_V 0x0000001FU
#define GPIO_PIN22_INT_ENA_S 13
/** GPIO_PIN23_REG register
* GPIO23 configuration register
*/
#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0x120)
/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN23_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN23_SYNC2_BYPASS_M (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S)
#define GPIO_PIN23_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN23_SYNC2_BYPASS_S 0
/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN23_PAD_DRIVER (BIT(2))
#define GPIO_PIN23_PAD_DRIVER_M (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S)
#define GPIO_PIN23_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN23_PAD_DRIVER_S 2
/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN23_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN23_SYNC1_BYPASS_M (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S)
#define GPIO_PIN23_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN23_SYNC1_BYPASS_S 3
/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN23_INT_TYPE 0x00000007U
#define GPIO_PIN23_INT_TYPE_M (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S)
#define GPIO_PIN23_INT_TYPE_V 0x00000007U
#define GPIO_PIN23_INT_TYPE_S 7
/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN23_WAKEUP_ENABLE_M (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S)
#define GPIO_PIN23_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN23_WAKEUP_ENABLE_S 10
/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN23_INT_ENA 0x0000001FU
#define GPIO_PIN23_INT_ENA_M (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S)
#define GPIO_PIN23_INT_ENA_V 0x0000001FU
#define GPIO_PIN23_INT_ENA_S 13
/** GPIO_PIN24_REG register
* GPIO24 configuration register
*/
#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0x124)
/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN24_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN24_SYNC2_BYPASS_M (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S)
#define GPIO_PIN24_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN24_SYNC2_BYPASS_S 0
/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN24_PAD_DRIVER (BIT(2))
#define GPIO_PIN24_PAD_DRIVER_M (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S)
#define GPIO_PIN24_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN24_PAD_DRIVER_S 2
/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN24_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN24_SYNC1_BYPASS_M (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S)
#define GPIO_PIN24_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN24_SYNC1_BYPASS_S 3
/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN24_INT_TYPE 0x00000007U
#define GPIO_PIN24_INT_TYPE_M (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S)
#define GPIO_PIN24_INT_TYPE_V 0x00000007U
#define GPIO_PIN24_INT_TYPE_S 7
/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN24_WAKEUP_ENABLE_M (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S)
#define GPIO_PIN24_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN24_WAKEUP_ENABLE_S 10
/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN24_INT_ENA 0x0000001FU
#define GPIO_PIN24_INT_ENA_M (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S)
#define GPIO_PIN24_INT_ENA_V 0x0000001FU
#define GPIO_PIN24_INT_ENA_S 13
/** GPIO_PIN25_REG register
* GPIO25 configuration register
*/
#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0x128)
/** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN25_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN25_SYNC2_BYPASS_M (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S)
#define GPIO_PIN25_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN25_SYNC2_BYPASS_S 0
/** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN25_PAD_DRIVER (BIT(2))
#define GPIO_PIN25_PAD_DRIVER_M (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S)
#define GPIO_PIN25_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN25_PAD_DRIVER_S 2
/** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN25_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN25_SYNC1_BYPASS_M (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S)
#define GPIO_PIN25_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN25_SYNC1_BYPASS_S 3
/** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN25_INT_TYPE 0x00000007U
#define GPIO_PIN25_INT_TYPE_M (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S)
#define GPIO_PIN25_INT_TYPE_V 0x00000007U
#define GPIO_PIN25_INT_TYPE_S 7
/** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN25_WAKEUP_ENABLE_M (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S)
#define GPIO_PIN25_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN25_WAKEUP_ENABLE_S 10
/** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN25_INT_ENA 0x0000001FU
#define GPIO_PIN25_INT_ENA_M (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S)
#define GPIO_PIN25_INT_ENA_V 0x0000001FU
#define GPIO_PIN25_INT_ENA_S 13
/** GPIO_PIN26_REG register
* GPIO26 configuration register
*/
#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0x12c)
/** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN26_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN26_SYNC2_BYPASS_M (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S)
#define GPIO_PIN26_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN26_SYNC2_BYPASS_S 0
/** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN26_PAD_DRIVER (BIT(2))
#define GPIO_PIN26_PAD_DRIVER_M (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S)
#define GPIO_PIN26_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN26_PAD_DRIVER_S 2
/** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN26_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN26_SYNC1_BYPASS_M (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S)
#define GPIO_PIN26_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN26_SYNC1_BYPASS_S 3
/** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN26_INT_TYPE 0x00000007U
#define GPIO_PIN26_INT_TYPE_M (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S)
#define GPIO_PIN26_INT_TYPE_V 0x00000007U
#define GPIO_PIN26_INT_TYPE_S 7
/** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN26_WAKEUP_ENABLE_M (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S)
#define GPIO_PIN26_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN26_WAKEUP_ENABLE_S 10
/** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN26_INT_ENA 0x0000001FU
#define GPIO_PIN26_INT_ENA_M (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S)
#define GPIO_PIN26_INT_ENA_V 0x0000001FU
#define GPIO_PIN26_INT_ENA_S 13
/** GPIO_PIN27_REG register
* GPIO27 configuration register
*/
#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0x130)
/** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN27_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN27_SYNC2_BYPASS_M (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S)
#define GPIO_PIN27_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN27_SYNC2_BYPASS_S 0
/** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN27_PAD_DRIVER (BIT(2))
#define GPIO_PIN27_PAD_DRIVER_M (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S)
#define GPIO_PIN27_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN27_PAD_DRIVER_S 2
/** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN27_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN27_SYNC1_BYPASS_M (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S)
#define GPIO_PIN27_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN27_SYNC1_BYPASS_S 3
/** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN27_INT_TYPE 0x00000007U
#define GPIO_PIN27_INT_TYPE_M (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S)
#define GPIO_PIN27_INT_TYPE_V 0x00000007U
#define GPIO_PIN27_INT_TYPE_S 7
/** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN27_WAKEUP_ENABLE_M (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S)
#define GPIO_PIN27_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN27_WAKEUP_ENABLE_S 10
/** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN27_INT_ENA 0x0000001FU
#define GPIO_PIN27_INT_ENA_M (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S)
#define GPIO_PIN27_INT_ENA_V 0x0000001FU
#define GPIO_PIN27_INT_ENA_S 13
/** GPIO_PIN28_REG register
* GPIO28 configuration register
*/
#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0x134)
/** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN28_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN28_SYNC2_BYPASS_M (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S)
#define GPIO_PIN28_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN28_SYNC2_BYPASS_S 0
/** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN28_PAD_DRIVER (BIT(2))
#define GPIO_PIN28_PAD_DRIVER_M (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S)
#define GPIO_PIN28_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN28_PAD_DRIVER_S 2
/** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN28_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN28_SYNC1_BYPASS_M (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S)
#define GPIO_PIN28_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN28_SYNC1_BYPASS_S 3
/** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN28_INT_TYPE 0x00000007U
#define GPIO_PIN28_INT_TYPE_M (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S)
#define GPIO_PIN28_INT_TYPE_V 0x00000007U
#define GPIO_PIN28_INT_TYPE_S 7
/** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN28_WAKEUP_ENABLE_M (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S)
#define GPIO_PIN28_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN28_WAKEUP_ENABLE_S 10
/** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN28_INT_ENA 0x0000001FU
#define GPIO_PIN28_INT_ENA_M (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S)
#define GPIO_PIN28_INT_ENA_V 0x0000001FU
#define GPIO_PIN28_INT_ENA_S 13
/** GPIO_FUNC0_IN_SEL_CFG_REG register
* Configuration register for input signal 0
*/
@ -5293,370 +4782,6 @@ extern "C" {
#define GPIO_FUNC21_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC21_OE_INV_SEL_S 11
/** GPIO_FUNC22_OUT_SEL_CFG_REG register
* Configuration register for GPIO22 output
*/
#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb1c)
/** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO22.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit 22 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC22_OUT_SEL 0x000001FFU
#define GPIO_FUNC22_OUT_SEL_M (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S)
#define GPIO_FUNC22_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC22_OUT_SEL_S 0
/** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC22_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC22_OUT_INV_SEL_M (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S)
#define GPIO_FUNC22_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC22_OUT_INV_SEL_S 9
/** GPIO_FUNC22_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit 22 of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC22_OE_SEL (BIT(10))
#define GPIO_FUNC22_OE_SEL_M (GPIO_FUNC22_OE_SEL_V << GPIO_FUNC22_OE_SEL_S)
#define GPIO_FUNC22_OE_SEL_V 0x00000001U
#define GPIO_FUNC22_OE_SEL_S 10
/** GPIO_FUNC22_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC22_OE_INV_SEL (BIT(11))
#define GPIO_FUNC22_OE_INV_SEL_M (GPIO_FUNC22_OE_INV_SEL_V << GPIO_FUNC22_OE_INV_SEL_S)
#define GPIO_FUNC22_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC22_OE_INV_SEL_S 11
/** GPIO_FUNC23_OUT_SEL_CFG_REG register
* Configuration register for GPIO23 output
*/
#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb20)
/** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO23.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit 23 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC23_OUT_SEL 0x000001FFU
#define GPIO_FUNC23_OUT_SEL_M (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S)
#define GPIO_FUNC23_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC23_OUT_SEL_S 0
/** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC23_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC23_OUT_INV_SEL_M (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S)
#define GPIO_FUNC23_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC23_OUT_INV_SEL_S 9
/** GPIO_FUNC23_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit 23 of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC23_OE_SEL (BIT(10))
#define GPIO_FUNC23_OE_SEL_M (GPIO_FUNC23_OE_SEL_V << GPIO_FUNC23_OE_SEL_S)
#define GPIO_FUNC23_OE_SEL_V 0x00000001U
#define GPIO_FUNC23_OE_SEL_S 10
/** GPIO_FUNC23_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC23_OE_INV_SEL (BIT(11))
#define GPIO_FUNC23_OE_INV_SEL_M (GPIO_FUNC23_OE_INV_SEL_V << GPIO_FUNC23_OE_INV_SEL_S)
#define GPIO_FUNC23_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC23_OE_INV_SEL_S 11
/** GPIO_FUNC24_OUT_SEL_CFG_REG register
* Configuration register for GPIO24 output
*/
#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb24)
/** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO24.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit 24 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC24_OUT_SEL 0x000001FFU
#define GPIO_FUNC24_OUT_SEL_M (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S)
#define GPIO_FUNC24_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC24_OUT_SEL_S 0
/** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC24_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC24_OUT_INV_SEL_M (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S)
#define GPIO_FUNC24_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC24_OUT_INV_SEL_S 9
/** GPIO_FUNC24_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit 24 of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC24_OE_SEL (BIT(10))
#define GPIO_FUNC24_OE_SEL_M (GPIO_FUNC24_OE_SEL_V << GPIO_FUNC24_OE_SEL_S)
#define GPIO_FUNC24_OE_SEL_V 0x00000001U
#define GPIO_FUNC24_OE_SEL_S 10
/** GPIO_FUNC24_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC24_OE_INV_SEL (BIT(11))
#define GPIO_FUNC24_OE_INV_SEL_M (GPIO_FUNC24_OE_INV_SEL_V << GPIO_FUNC24_OE_INV_SEL_S)
#define GPIO_FUNC24_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC24_OE_INV_SEL_S 11
/** GPIO_FUNC25_OUT_SEL_CFG_REG register
* Configuration register for GPIO$n output
*/
#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb28)
/** GPIO_FUNC25_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO$n.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC25_OUT_SEL 0x000001FFU
#define GPIO_FUNC25_OUT_SEL_M (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S)
#define GPIO_FUNC25_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC25_OUT_SEL_S 0
/** GPIO_FUNC25_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC25_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC25_OUT_INV_SEL_M (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S)
#define GPIO_FUNC25_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC25_OUT_INV_SEL_S 9
/** GPIO_FUNC25_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC25_OE_SEL (BIT(10))
#define GPIO_FUNC25_OE_SEL_M (GPIO_FUNC25_OE_SEL_V << GPIO_FUNC25_OE_SEL_S)
#define GPIO_FUNC25_OE_SEL_V 0x00000001U
#define GPIO_FUNC25_OE_SEL_S 10
/** GPIO_FUNC25_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC25_OE_INV_SEL (BIT(11))
#define GPIO_FUNC25_OE_INV_SEL_M (GPIO_FUNC25_OE_INV_SEL_V << GPIO_FUNC25_OE_INV_SEL_S)
#define GPIO_FUNC25_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC25_OE_INV_SEL_S 11
/** GPIO_FUNC26_OUT_SEL_CFG_REG register
* Configuration register for GPIO$n output
*/
#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb2c)
/** GPIO_FUNC26_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO$n.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC26_OUT_SEL 0x000001FFU
#define GPIO_FUNC26_OUT_SEL_M (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S)
#define GPIO_FUNC26_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC26_OUT_SEL_S 0
/** GPIO_FUNC26_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC26_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC26_OUT_INV_SEL_M (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S)
#define GPIO_FUNC26_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC26_OUT_INV_SEL_S 9
/** GPIO_FUNC26_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC26_OE_SEL (BIT(10))
#define GPIO_FUNC26_OE_SEL_M (GPIO_FUNC26_OE_SEL_V << GPIO_FUNC26_OE_SEL_S)
#define GPIO_FUNC26_OE_SEL_V 0x00000001U
#define GPIO_FUNC26_OE_SEL_S 10
/** GPIO_FUNC26_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC26_OE_INV_SEL (BIT(11))
#define GPIO_FUNC26_OE_INV_SEL_M (GPIO_FUNC26_OE_INV_SEL_V << GPIO_FUNC26_OE_INV_SEL_S)
#define GPIO_FUNC26_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC26_OE_INV_SEL_S 11
/** GPIO_FUNC27_OUT_SEL_CFG_REG register
* Configuration register for GPIO$n output
*/
#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb30)
/** GPIO_FUNC27_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO$n.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC27_OUT_SEL 0x000001FFU
#define GPIO_FUNC27_OUT_SEL_M (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S)
#define GPIO_FUNC27_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC27_OUT_SEL_S 0
/** GPIO_FUNC27_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC27_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC27_OUT_INV_SEL_M (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S)
#define GPIO_FUNC27_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC27_OUT_INV_SEL_S 9
/** GPIO_FUNC27_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC27_OE_SEL (BIT(10))
#define GPIO_FUNC27_OE_SEL_M (GPIO_FUNC27_OE_SEL_V << GPIO_FUNC27_OE_SEL_S)
#define GPIO_FUNC27_OE_SEL_V 0x00000001U
#define GPIO_FUNC27_OE_SEL_S 10
/** GPIO_FUNC27_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC27_OE_INV_SEL (BIT(11))
#define GPIO_FUNC27_OE_INV_SEL_M (GPIO_FUNC27_OE_INV_SEL_V << GPIO_FUNC27_OE_INV_SEL_S)
#define GPIO_FUNC27_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC27_OE_INV_SEL_S 11
/** GPIO_FUNC28_OUT_SEL_CFG_REG register
* Configuration register for GPIO$n output
*/
#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb34)
/** GPIO_FUNC28_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO$n.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC28_OUT_SEL 0x000001FFU
#define GPIO_FUNC28_OUT_SEL_M (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S)
#define GPIO_FUNC28_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC28_OUT_SEL_S 0
/** GPIO_FUNC28_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC28_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC28_OUT_INV_SEL_M (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S)
#define GPIO_FUNC28_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC28_OUT_INV_SEL_S 9
/** GPIO_FUNC28_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC28_OE_SEL (BIT(10))
#define GPIO_FUNC28_OE_SEL_M (GPIO_FUNC28_OE_SEL_V << GPIO_FUNC28_OE_SEL_S)
#define GPIO_FUNC28_OE_SEL_V 0x00000001U
#define GPIO_FUNC28_OE_SEL_S 10
/** GPIO_FUNC28_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC28_OE_INV_SEL (BIT(11))
#define GPIO_FUNC28_OE_INV_SEL_M (GPIO_FUNC28_OE_INV_SEL_V << GPIO_FUNC28_OE_INV_SEL_S)
#define GPIO_FUNC28_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC28_OE_INV_SEL_S 11
/** GPIO_CLOCK_GATE_REG register
* GPIO clock gate register
*/

444
components/soc/esp32c61/include/soc/gpio_struct.h
Wyświetl plik

@ -330,254 +330,6 @@ typedef union {
uint32_t val;
} gpio_pinn_reg_t;
/** Type of pin25 register
* GPIO25 configuration register
*/
typedef union {
struct {
/** pin25_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
uint32_t pin25_sync2_bypass:2;
/** pin25_pad_driver : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
uint32_t pin25_pad_driver:1;
/** pin25_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
uint32_t pin25_sync1_bypass:2;
uint32_t reserved_5:2;
/** pin25_int_type : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
uint32_t pin25_int_type:3;
/** pin25_wakeup_enable : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
uint32_t pin25_wakeup_enable:1;
uint32_t reserved_11:2;
/** pin25_int_ena : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
uint32_t pin25_int_ena:5;
uint32_t reserved_18:14;
};
uint32_t val;
} gpio_pin25_reg_t;
/** Type of pin26 register
* GPIO26 configuration register
*/
typedef union {
struct {
/** pin26_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
uint32_t pin26_sync2_bypass:2;
/** pin26_pad_driver : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
uint32_t pin26_pad_driver:1;
/** pin26_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
uint32_t pin26_sync1_bypass:2;
uint32_t reserved_5:2;
/** pin26_int_type : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
uint32_t pin26_int_type:3;
/** pin26_wakeup_enable : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
uint32_t pin26_wakeup_enable:1;
uint32_t reserved_11:2;
/** pin26_int_ena : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
uint32_t pin26_int_ena:5;
uint32_t reserved_18:14;
};
uint32_t val;
} gpio_pin26_reg_t;
/** Type of pin27 register
* GPIO27 configuration register
*/
typedef union {
struct {
/** pin27_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
uint32_t pin27_sync2_bypass:2;
/** pin27_pad_driver : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
uint32_t pin27_pad_driver:1;
/** pin27_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
uint32_t pin27_sync1_bypass:2;
uint32_t reserved_5:2;
/** pin27_int_type : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
uint32_t pin27_int_type:3;
/** pin27_wakeup_enable : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
uint32_t pin27_wakeup_enable:1;
uint32_t reserved_11:2;
/** pin27_int_ena : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
uint32_t pin27_int_ena:5;
uint32_t reserved_18:14;
};
uint32_t val;
} gpio_pin27_reg_t;
/** Type of pin28 register
* GPIO28 configuration register
*/
typedef union {
struct {
/** pin28_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
uint32_t pin28_sync2_bypass:2;
/** pin28_pad_driver : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
uint32_t pin28_pad_driver:1;
/** pin28_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
uint32_t pin28_sync1_bypass:2;
uint32_t reserved_5:2;
/** pin28_int_type : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
uint32_t pin28_int_type:3;
/** pin28_wakeup_enable : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
uint32_t pin28_wakeup_enable:1;
uint32_t reserved_11:2;
/** pin28_int_ena : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
uint32_t pin28_int_ena:5;
uint32_t reserved_18:14;
};
uint32_t val;
} gpio_pin28_reg_t;
/** Group: Input Configuration Registers */
/** Type of func0_in_sel_cfg register
@ -661,186 +413,6 @@ typedef union {
uint32_t val;
} gpio_funcn_out_sel_cfg_reg_t;
/** Type of func25_out_sel_cfg register
* Configuration register for GPIO$n output
*/
typedef union {
struct {
/** func25_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO$n.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
uint32_t func25_out_sel:9;
/** func25_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
uint32_t func25_out_inv_sel:1;
/** func25_oe_sel : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
*/
uint32_t func25_oe_sel:1;
/** func25_oe_inv_sel : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
uint32_t func25_oe_inv_sel:1;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_func25_out_sel_cfg_reg_t;
/** Type of func26_out_sel_cfg register
* Configuration register for GPIO$n output
*/
typedef union {
struct {
/** func26_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO$n.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
uint32_t func26_out_sel:9;
/** func26_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
uint32_t func26_out_inv_sel:1;
/** func26_oe_sel : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
*/
uint32_t func26_oe_sel:1;
/** func26_oe_inv_sel : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
uint32_t func26_oe_inv_sel:1;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_func26_out_sel_cfg_reg_t;
/** Type of func27_out_sel_cfg register
* Configuration register for GPIO$n output
*/
typedef union {
struct {
/** func27_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO$n.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
uint32_t func27_out_sel:9;
/** func27_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
uint32_t func27_out_inv_sel:1;
/** func27_oe_sel : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
*/
uint32_t func27_oe_sel:1;
/** func27_oe_inv_sel : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
uint32_t func27_oe_inv_sel:1;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_func27_out_sel_cfg_reg_t;
/** Type of func28_out_sel_cfg register
* Configuration register for GPIO$n output
*/
typedef union {
struct {
/** func28_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO$n.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
uint32_t func28_out_sel:9;
/** func28_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
uint32_t func28_out_inv_sel:1;
/** func28_oe_sel : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
*/
uint32_t func28_oe_sel:1;
/** func28_oe_inv_sel : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
uint32_t func28_oe_inv_sel:1;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_func28_out_sel_cfg_reg_t;
/** Group: Clock Gate Register */
/** Type of clock_gate register
@ -896,20 +468,12 @@ typedef struct {
uint32_t reserved_0a8[3];
volatile gpio_status_next_reg_t status_next;
uint32_t reserved_0b8[3];
volatile gpio_pinn_reg_t pinn[25];
volatile gpio_pin25_reg_t pin25;
volatile gpio_pin26_reg_t pin26;
volatile gpio_pin27_reg_t pin27;
volatile gpio_pin28_reg_t pin28;
uint32_t reserved_138[99];
volatile gpio_pinn_reg_t pinn[22]; // 0-21 are fanned out, 22-24 are not fanned out but padded out, 25-28 are not padded out. Only 0-21 are available.
uint32_t reserved_11c[106];
volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; //0-255. reserved: 1-5, 18-26, 36-40, 44-45, 48-63, 70-71, 75-81, 84-96, 101-117, 122-255;
uint32_t reserved_4ac[256];
volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[25];
volatile gpio_func25_out_sel_cfg_reg_t func25_out_sel_cfg;
volatile gpio_func26_out_sel_cfg_reg_t func26_out_sel_cfg;
volatile gpio_func27_out_sel_cfg_reg_t func27_out_sel_cfg;
volatile gpio_func28_out_sel_cfg_reg_t func28_out_sel_cfg;
uint32_t reserved_b38[176];
volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[22];
uint32_t reserved_b1c[183];
volatile gpio_clock_gate_reg_t clock_gate;
volatile gpio_date_reg_t date;
} gpio_dev_t;

26
components/soc/esp32c61/include/soc/io_mux_reg.h
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@ -117,9 +117,6 @@ extern "C" {
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U_PAD_SPIHD
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U_PAD_SPICLK
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U_PAD_SPID
#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U_PAD_GPIO22
#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U_PAD_GPIO23
#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U_PAD_GPIO24
#define PIN_FUNC_GPIO 1
@ -137,13 +134,16 @@ extern "C" {
#define SPI_D_GPIO_NUM 21
#define SPI_Q_GPIO_NUM 16
#define USB_INT_PHY0_DM_GPIO_NUM 12
#define USB_INT_PHY0_DP_GPIO_NUM 13
#define MAX_RTC_GPIO_NUM 7
#define MAX_PAD_GPIO_NUM 30
#define MAX_GPIO_NUM 34
#define MAX_PAD_GPIO_NUM 21
#define MAX_GPIO_NUM 28
#define HIGH_IO_HOLD_BIT_SHIFT 32
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define PAD_POWER_SEL BIT(15)
#define PAD_POWER_SEL_V 0x1
#define PAD_POWER_SEL_M BIT(15)
@ -277,18 +277,6 @@ extern "C" {
#define FUNC_SPID_GPIO21 1
#define FUNC_SPID_SPID 0
#define PERIPHS_IO_MUX_U_PAD_GPIO22 (REG_IO_MUX_BASE + 0x58)
#define FUNC_GPIO22_GPIO22 1
#define FUNC_GPIO22_GPIO22_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO23 (REG_IO_MUX_BASE + 0x5C)
#define FUNC_GPIO23_GPIO23 1
#define FUNC_GPIO23_GPIO23_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO24 (REG_IO_MUX_BASE + 0x60)
#define FUNC_GPIO24_GPIO24 1
#define FUNC_GPIO24_GPIO24_0 0
/** IO_MUX_DATE_REG register
* Version control register
*/

6
components/soc/esp32c61/include/soc/io_mux_struct.h
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@ -129,12 +129,12 @@ typedef union {
typedef struct {
volatile io_mux_gpion_reg_t gpion[25];
uint32_t reserved_064[102];
volatile io_mux_gpion_reg_t gpion[22];
uint32_t reserved_058[105];
volatile io_mux_date_reg_t date;
} io_mux_dev_t;
extern io_mux_dev_t IO_MUX;
extern io_mux_dev_t IOMUX;
#ifndef __cplusplus
_Static_assert(sizeof(io_mux_dev_t) == 0x200, "Invalid size of io_mux_dev_t structure");

16
components/soc/esp32c61/include/soc/soc_caps.h
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@ -36,7 +36,6 @@
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1 //TODO: [ESP32C61] IDF-9274
// #define SOC_I2S_SUPPORTED 1 //TODO: [ESP32C61] IDF-9312, IDF-9313
// #define SOC_SDM_SUPPORTED 1 //TODO: [ESP32C61] IDF-9335
// #define SOC_GPSPI_SUPPORTED 1 //TODO: [ESP32C61] IDF-9299, IDF-9300, IDF-9301
// #define SOC_LEDC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9291
// #define SOC_I2C_SUPPORTED 1 //TODO: [ESP32C61] IDF-9296, IDF-9297
@ -181,9 +180,8 @@
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-C61 has 1 GPIO peripheral
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 25
#define SOC_GPIO_PIN_COUNT 22
// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 //TODO: [ESP32C61] IDF-9340
// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 //TODO: [ESP32C61] IDF-9340
// GPIO peripheral has the ETM extension
// #define SOC_GPIO_SUPPORT_ETM 1 //TODO: [ESP32C61] IDF-9340
@ -202,10 +200,10 @@
#define SOC_GPIO_IN_RANGE_MAX 21
#define SOC_GPIO_OUT_RANGE_MAX 21
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_21)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000003FFF80ULL
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
@ -369,12 +367,6 @@
#define SOC_SHA_SUPPORT_SHA224 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 4
#define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
#define SOC_SDM_CLK_SUPPORT_XTAL 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 6

2
components/soc/esp32c61/ld/esp32c61.peripherals.ld
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@ -26,7 +26,7 @@ PROVIDE ( GPSPI2 = 0x60081000 );
PROVIDE ( SHA = 0x60089000 );
PROVIDE ( ECC = 0x6008B000 );
PROVIDE ( ECDSA = 0x6008E000 );
PROVIDE ( IO_MUX = 0x60090000 );
PROVIDE ( IOMUX = 0x60090000 );
PROVIDE ( GPIO = 0x60091000 );
PROVIDE ( TCM_MEM_MONITOR = 0x60092000 );
PROVIDE ( PAU = 0x60093000 );

141
docs/en/api-reference/peripherals/gpio/esp32c61.inc 100644
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@ -0,0 +1,141 @@
.. This file gets included from other .rst files in this folder.
.. It contains target-specific snippets.
.. Comments and '---' lines act as delimiters.
..
.. This is necessary mainly because RST doesn't support substitutions
.. (defined in RST, not in Python) inside code blocks. If that is ever implemented,
.. These code blocks can be moved back to the main .rst files, with target-specific
.. file names being replaced by substitutions.
.. gpio-summary
The {IDF_TARGET_NAME} chip features 22 physical GPIO pins (GPIO0 ~ GPIO21). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions.
.. list-table::
:header-rows: 1
:widths: 8 12 12 20
* - GPIO
- Analog Function
- LP GPIO
- Comments
* - GPIO0
- ADC2_CH0
- LP_GPIO0
-
* - GPIO1
- ADC1_CH0
- LP_GPIO1
-
* - GPIO2
-
- LP_GPIO2
-
* - GPIO3
- ADC1_CH1
- LP_GPIO3
- Strapping pin
* - GPIO4
- ADC1_CH2
- LP_GPIO4
- Strapping pin
* - GPIO5
- ADC1_CH3
- LP_GPIO5
-
* - GPIO6
- ADC1_CH5
- LP_GPIO6
-
* - GPIO7
-
-
- Strapping pin
* - GPIO8
-
-
- Strapping pin
* - GPIO9
-
-
- Strapping pin
* - GPIO10
-
-
-
* - GPIO11
-
-
-
* - GPIO12
-
-
- USB-JTAG
* - GPIO13
-
-
- USB-JTAG
* - GPIO14
-
-
- SPI0/1
* - GPIO15
-
-
- SPI0/1
* - GPIO16
-
-
- SPI0/1
* - GPIO17
-
-
- SPI0/1
* - GPIO18
-
-
-
* - GPIO19
-
-
- SPI0/1
* - GPIO20
-
-
- SPI0/1
* - GPIO21
-
-
- SPI0/1
.. note::
- Strapping pin: GPIO3, GPIO4, GPIO7, GPIO8 and GPIO9 are strapping pins. For more information, please refer to `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__.
- SPI0/1: GPIO14 ~ GPIO17 and GPIO19 ~ GPIO21 are usually used for SPI flash and not recommended for other uses.
- USB-JTAG: GPIO12 and GPIO13 are used by USB-JTAG by default. If they are reconfigured to operate as normal GPIOs, USB-JTAG functionality will be disabled.
---

141
docs/zh_CN/api-reference/peripherals/gpio/esp32c61.inc 100644
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@ -0,0 +1,141 @@
.. This file gets included from other .rst files in this folder.
.. It contains target-specific snippets.
.. Comments and '---' lines act as delimiters.
..
.. This is necessary mainly because RST doesn't support substitutions
.. (defined in RST, not in Python) inside code blocks. If that is ever implemented,
.. These code blocks can be moved back to the main .rst files, with target-specific
.. file names being replaced by substitutions.
.. gpio-summary
{IDF_TARGET_NAME} 芯片具有 22 个物理 GPIO 管脚（GPIO0 ~ GPIO21）。每个管脚都可用作一个通用 IO，或连接一个内部的外设 信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输 出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。
下表提供了各管脚的详细信息，部分 GPIO 具有特殊的使用限制，具体可参考表中的注释列。
.. list-table::
:header-rows: 1
:widths: 8 12 12 20
* - GPIO
- 模拟功能
- LP GPIO
- 注释
* - GPIO0
- ADC2_CH0
- LP_GPIO0
-
* - GPIO1
- ADC1_CH0
- LP_GPIO1
-
* - GPIO2
-
- LP_GPIO2
-
* - GPIO3
- ADC1_CH1
- LP_GPIO3
- Strapping 管脚
* - GPIO4
- ADC1_CH2
- LP_GPIO4
- Strapping 管脚
* - GPIO5
- ADC1_CH3
- LP_GPIO5
-
* - GPIO6
- ADC1_CH5
- LP_GPIO6
-
* - GPIO7
-
-
- Strapping 管脚
* - GPIO8
-
-
- Strapping 管脚
* - GPIO9
-
-
- Strapping 管脚
* - GPIO10
-
-
-
* - GPIO11
-
-
-
* - GPIO12
-
-
- USB-JTAG
* - GPIO13
-
-
- USB-JTAG
* - GPIO14
-
-
- SPI0/1
* - GPIO15
-
-
- SPI0/1
* - GPIO16
-
-
- SPI0/1
* - GPIO17
-
-
- SPI0/1
* - GPIO18
-
-
-
* - GPIO19
-
-
- SPI0/1
* - GPIO20
-
-
- SPI0/1
* - GPIO21
-
-
- SPI0/1
.. note::
- Strapping 管脚：GPIO3、GPIO4、GPIO7、GPIO8 和 GPIO9 是 Strapping 管脚。更多信息请参考 `ESP32-C61 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_。
- SPI0/1：GPIO14 ~ GPIO17 和 GPIO19 ~ GPIO21 通常用于 SPI flash，不推荐用于其他用途。
- USB-JTAG：GPIO12 和 GPIO13 默认用于 USB-JTAG。如果将它们配置为普通 GPIO，驱动程序将禁用 USB-JTAG 功能。
---

4
examples/peripherals/gpio/generic_gpio/main/Kconfig.projbuild
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@ -5,7 +5,7 @@ menu "Example Configuration"
config GPIO_OUTPUT_0
int "GPIO output pin 0"
range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
default 8 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32C5
default 8 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32C5 || IDF_TARGET_ESP32C61
default 18
help
GPIO pin number to be used as GPIO_OUTPUT_IO_0.
@ -13,7 +13,7 @@ menu "Example Configuration"
config GPIO_OUTPUT_1
int "GPIO output pin 1"
range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
default 9 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32C5
default 9 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32C5 || IDF_TARGET_ESP32C61
default 19
help
GPIO pin number to be used as GPIO_OUTPUT_IO_1.