kopia lustrzana https://github.com/espressif/esp-idf
295 wiersze
14 KiB
C
295 wiersze
14 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
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/* Output enable in sleep mode */
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#define SLP_OE (BIT(0))
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#define SLP_OE_M (BIT(0))
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#define SLP_OE_V 1
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#define SLP_OE_S 0
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/* Pin used for wakeup from sleep */
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#define SLP_SEL (BIT(1))
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#define SLP_SEL_M (BIT(1))
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#define SLP_SEL_V 1
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#define SLP_SEL_S 1
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/* Pulldown enable in sleep mode */
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#define SLP_PD (BIT(2))
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#define SLP_PD_M (BIT(2))
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#define SLP_PD_V 1
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#define SLP_PD_S 2
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/* Pullup enable in sleep mode */
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#define SLP_PU (BIT(3))
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#define SLP_PU_M (BIT(3))
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#define SLP_PU_V 1
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#define SLP_PU_S 3
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/* Input enable in sleep mode */
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#define SLP_IE (BIT(4))
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#define SLP_IE_M (BIT(4))
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#define SLP_IE_V 1
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#define SLP_IE_S 4
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/* Drive strength in sleep mode */
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#define SLP_DRV 0x3
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#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
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#define SLP_DRV_V 0x3
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#define SLP_DRV_S 5
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/* Pulldown enable */
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#define FUN_PD (BIT(7))
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#define FUN_PD_M (BIT(7))
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#define FUN_PD_V 1
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#define FUN_PD_S 7
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/* Pullup enable */
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#define FUN_PU (BIT(8))
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#define FUN_PU_M (BIT(8))
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#define FUN_PU_V 1
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#define FUN_PU_S 8
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/* Input enable */
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#define FUN_IE (BIT(9))
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#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
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#define FUN_IE_V 1
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#define FUN_IE_S 9
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/* Drive strength */
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#define FUN_DRV 0x3
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#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
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#define FUN_DRV_V 0x3
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#define FUN_DRV_S 10
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/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
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#define MCU_SEL 0x7
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#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
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#define MCU_SEL_V 0x7
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#define MCU_SEL_S 12
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/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
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#define FILTER_EN (BIT(15))
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#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
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#define FILTER_EN_V 1
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#define FILTER_EN_S 15
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#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
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#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
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#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
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#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
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#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
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#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
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#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
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#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
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#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
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#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
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#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
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#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
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#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
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#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
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#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
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#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
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#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
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#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
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#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN)
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#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN)
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#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_P
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#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_N
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#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_U_PAD_GPIO2
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#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_U_PAD_MTMS
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#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_U_PAD_MTDI
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#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_U_PAD_MTCK
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#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_U_PAD_MTDO
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#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_U_PAD_GPIO7
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#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_U_PAD_GPIO8
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#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_U_PAD_GPIO9
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#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_U_PAD_U0RXD
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#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_U_PAD_U0TXD
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#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_U_PAD_GPIO12
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#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_U_PAD_GPIO13
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#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_U_PAD_SPICS1
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#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_U_PAD_SPICS0
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#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_U_PAD_SPIQ
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#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_U_PAD_SPIWP
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#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_U_PAD_VDD_SPI
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#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U_PAD_SPIHD
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#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U_PAD_SPICLK
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#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U_PAD_SPID
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#define PIN_FUNC_GPIO 1
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#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
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#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
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#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
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#define U0RXD_GPIO_NUM 10
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#define U0TXD_GPIO_NUM 11
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#define SPI_HD_GPIO_NUM 19
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#define SPI_WP_GPIO_NUM 17
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#define SPI_CS0_GPIO_NUM 15
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#define SPI_CLK_GPIO_NUM 20
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#define SPI_D_GPIO_NUM 21
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#define SPI_Q_GPIO_NUM 16
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#define USB_INT_PHY0_DM_GPIO_NUM 12
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#define USB_INT_PHY0_DP_GPIO_NUM 13
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#define MAX_RTC_GPIO_NUM 7
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#define MAX_PAD_GPIO_NUM 21
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#define MAX_GPIO_NUM 28
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#define HIGH_IO_HOLD_BIT_SHIFT 32
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#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
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#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
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#define PAD_POWER_SEL BIT(15)
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#define PAD_POWER_SEL_V 0x1
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#define PAD_POWER_SEL_M BIT(15)
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#define PAD_POWER_SEL_S 15
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#define PAD_POWER_SWITCH_DELAY 0x7
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#define PAD_POWER_SWITCH_DELAY_V 0x7
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#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
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#define PAD_POWER_SWITCH_DELAY_S 12
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//TODO: [ESP32C61] IDF-9316, copy from verify
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#define IO_MUX_CLK_OUT3 0x0000000F
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#define IO_MUX_CLK_OUT3_M ((IO_MUX_CLK_OUT3_V)<<(IO_MUX_CLK_OUT3_S))
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#define IO_MUX_CLK_OUT3_V 0xF
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#define IO_MUX_CLK_OUT3_S 8
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#define IO_MUX_CLK_OUT2 0x0000000F
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#define IO_MUX_CLK_OUT2_M ((IO_MUX_CLK_OUT2_V)<<(IO_MUX_CLK_OUT2_S))
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#define IO_MUX_CLK_OUT2_V 0xF
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#define IO_MUX_CLK_OUT2_S 4
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#define IO_MUX_CLK_OUT1 0x0000000F
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#define IO_MUX_CLK_OUT1_M ((IO_MUX_CLK_OUT1_V)<<(IO_MUX_CLK_OUT1_S))
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#define IO_MUX_CLK_OUT1_V 0xF
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#define IO_MUX_CLK_OUT1_S 0
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#define CLK_OUT3 IO_MUX_CLK_OUT3
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#define CLK_OUT3_V IO_MUX_CLK_OUT3_V
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#define CLK_OUT3_S IO_MUX_CLK_OUT3_S
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#define CLK_OUT3_M IO_MUX_CLK_OUT3_M
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#define CLK_OUT2 IO_MUX_CLK_OUT2
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#define CLK_OUT2_V IO_MUX_CLK_OUT2_V
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#define CLK_OUT2_S IO_MUX_CLK_OUT2_S
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#define CLK_OUT2_M IO_MUX_CLK_OUT2_M
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#define CLK_OUT1 IO_MUX_CLK_OUT1
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#define CLK_OUT1_V IO_MUX_CLK_OUT1_V
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#define CLK_OUT1_S IO_MUX_CLK_OUT1_S
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#define CLK_OUT1_M IO_MUX_CLK_OUT1_M
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// definitions above are inherited from previous version of code, should double check
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// definitions below are generated from pin_txt.csv
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#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_P (REG_IO_MUX_BASE + 0x0)
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#define FUNC_XTAL_32K_P_GPIO0 1
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#define FUNC_XTAL_32K_P_GPIO0_0 0
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#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_N (REG_IO_MUX_BASE + 0x4)
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#define FUNC_XTAL_32K_N_GPIO1 1
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#define FUNC_XTAL_32K_N_GPIO1_0 0
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#define PERIPHS_IO_MUX_U_PAD_GPIO2 (REG_IO_MUX_BASE + 0x8)
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#define FUNC_GPIO2_FSPIQ 2
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#define FUNC_GPIO2_GPIO2 1
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#define FUNC_GPIO2_GPIO2_0 0
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#define PERIPHS_IO_MUX_U_PAD_MTMS (REG_IO_MUX_BASE + 0xC)
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#define FUNC_MTMS_FSPIHD 2
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#define FUNC_MTMS_GPIO3 1
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#define FUNC_MTMS_MTMS 0
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#define PERIPHS_IO_MUX_U_PAD_MTDI (REG_IO_MUX_BASE + 0x10)
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#define FUNC_MTDI_FSPIWP 2
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#define FUNC_MTDI_GPIO4 1
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#define FUNC_MTDI_MTDI 0
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#define PERIPHS_IO_MUX_U_PAD_MTCK (REG_IO_MUX_BASE + 0x14)
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#define FUNC_MTCK_GPIO5 1
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#define FUNC_MTCK_MTCK 0
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#define PERIPHS_IO_MUX_U_PAD_MTDO (REG_IO_MUX_BASE + 0x18)
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#define FUNC_MTDO_FSPICLK 2
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#define FUNC_MTDO_GPIO6 1
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#define FUNC_MTDO_MTDO 0
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#define PERIPHS_IO_MUX_U_PAD_GPIO7 (REG_IO_MUX_BASE + 0x1C)
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#define FUNC_GPIO7_FSPID 2
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#define FUNC_GPIO7_GPIO7 1
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#define FUNC_GPIO7_GPIO7_0 0
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#define PERIPHS_IO_MUX_U_PAD_GPIO8 (REG_IO_MUX_BASE + 0x20)
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#define FUNC_GPIO8_FSPICS0 2
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#define FUNC_GPIO8_GPIO8 1
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#define FUNC_GPIO8_GPIO8_0 0
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#define PERIPHS_IO_MUX_U_PAD_GPIO9 (REG_IO_MUX_BASE + 0x24)
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#define FUNC_GPIO9_GPIO9 1
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#define FUNC_GPIO9_GPIO9_0 0
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#define PERIPHS_IO_MUX_U_PAD_U0RXD (REG_IO_MUX_BASE + 0x28)
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#define FUNC_U0RXD_GPIO10 1
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#define FUNC_U0RXD_U0RXD 0
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#define PERIPHS_IO_MUX_U_PAD_U0TXD (REG_IO_MUX_BASE + 0x2C)
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#define FUNC_U0TXD_GPIO11 1
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#define FUNC_U0TXD_U0TXD 0
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#define PERIPHS_IO_MUX_U_PAD_GPIO12 (REG_IO_MUX_BASE + 0x30)
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#define FUNC_GPIO12_GPIO12 1
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#define FUNC_GPIO12_GPIO12_0 0
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#define PERIPHS_IO_MUX_U_PAD_GPIO13 (REG_IO_MUX_BASE + 0x34)
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#define FUNC_GPIO13_GPIO13 1
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#define FUNC_GPIO13_GPIO13_0 0
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#define PERIPHS_IO_MUX_U_PAD_SPICS1 (REG_IO_MUX_BASE + 0x38)
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#define FUNC_SPICS1_GPIO14 1
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#define FUNC_SPICS1_SPICS1 0
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#define PERIPHS_IO_MUX_U_PAD_SPICS0 (REG_IO_MUX_BASE + 0x3C)
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#define FUNC_SPICS0_GPIO15 1
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#define FUNC_SPICS0_SPICS0 0
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#define PERIPHS_IO_MUX_U_PAD_SPIQ (REG_IO_MUX_BASE + 0x40)
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#define FUNC_SPIQ_GPIO16 1
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#define FUNC_SPIQ_SPIQ 0
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#define PERIPHS_IO_MUX_U_PAD_SPIWP (REG_IO_MUX_BASE + 0x44)
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#define FUNC_SPIWP_GPIO17 1
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#define FUNC_SPIWP_SPIWP 0
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#define PERIPHS_IO_MUX_U_PAD_VDD_SPI (REG_IO_MUX_BASE + 0x48)
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#define FUNC_VDD_SPI_GPIO18 1
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#define FUNC_VDD_SPI_GPIO18_0 0
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#define PERIPHS_IO_MUX_U_PAD_SPIHD (REG_IO_MUX_BASE + 0x4C)
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#define FUNC_SPIHD_GPIO19 1
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#define FUNC_SPIHD_SPIHD 0
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#define PERIPHS_IO_MUX_U_PAD_SPICLK (REG_IO_MUX_BASE + 0x50)
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#define FUNC_SPICLK_GPIO20 1
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#define FUNC_SPICLK_SPICLK 0
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#define PERIPHS_IO_MUX_U_PAD_SPID (REG_IO_MUX_BASE + 0x54)
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#define FUNC_SPID_GPIO21 1
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#define FUNC_SPID_SPID 0
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/** IO_MUX_DATE_REG register
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* Version control register
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*/
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#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0x1fc)
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/** IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 36774288;
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* Version control register
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*/
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#define IO_MUX_REG_DATE 0x0FFFFFFFU
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#define IO_MUX_REG_DATE_M (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S)
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#define IO_MUX_REG_DATE_V 0x0FFFFFFFU
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#define IO_MUX_REG_DATE_S 0
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#ifdef __cplusplus
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}
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#endif
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