kopia lustrzana https://github.com/espressif/esp-idf
490 wiersze
16 KiB
C
490 wiersze
16 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Configuration Registers */
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/** Type of strap register
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* Strapping pin register
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*/
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typedef union {
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struct {
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/** strapping : RO; bitpos: [15:0]; default: 0;
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* Represents the values of GPIO strapping pins.
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*
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* - bit0 ~ bit1: invalid
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* - bit2: GPIO8
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* - bit3: GPIO9
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* - bit4: GPIO7
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* - bit5 ~ bit15: invalid
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*/
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uint32_t strapping:16;
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uint32_t reserved_16:16;
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};
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uint32_t val;
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} gpio_strap_reg_t;
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/** Type of out register
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* GPIO output register
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*/
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typedef union {
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struct {
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/** out_data_orig : R/W/SC/WTC; bitpos: [28:0]; default: 0;
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* Configures the output value of GPIO0 ~ 24 output in simple GPIO output mode.\\
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* 0: Low level\\
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* 1: High level\\
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* The value of bit0 ~ bit24 correspond to the output value of GPIO0 ~ GPIO24
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* respectively. Bit25 ~ bit31 are invalid.\\
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*/
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uint32_t out_data_orig:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_out_reg_t;
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/** Type of out_w1ts register
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* GPIO output set register
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*/
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typedef union {
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struct {
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/** out_w1ts : WT; bitpos: [28:0]; default: 0;
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* Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~
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* GPIO24.\\
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* 0: Not set\\
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* 1: The corresponding bit in GPIO_OUT_REG will be set to 1\\
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* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
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* Recommended operation: use this register to set GPIO_OUT_REG. \\
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*/
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uint32_t out_w1ts:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_out_w1ts_reg_t;
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/** Type of out_w1tc register
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* GPIO output clear register
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*/
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typedef union {
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struct {
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/** out_w1tc : WT; bitpos: [28:0]; default: 0;
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* Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0 ~
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* GPIO24 output.\\
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* 0: Not clear\\
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* 1: The corresponding bit in GPIO_OUT_REG will be cleared.\\
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* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
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* Recommended operation: use this register to clear GPIO_OUT_REG. \\
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*/
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uint32_t out_w1tc:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_out_w1tc_reg_t;
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/** Type of enable register
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* GPIO output enable register
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*/
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typedef union {
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struct {
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/** enable_data : R/W/WTC; bitpos: [28:0]; default: 0;
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* Configures whether or not to enable the output of GPIO0 ~ GPIO24.\\
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* 0: Not enable\\
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* 1: Enable\\
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* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\
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*/
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uint32_t enable_data:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_enable_reg_t;
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/** Type of enable_w1ts register
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* GPIO output enable set register
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*/
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typedef union {
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struct {
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/** enable_w1ts : WT; bitpos: [28:0]; default: 0;
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* Configures whether or not to set the output enable register GPIO_ENABLE_REG of
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* GPIO0 ~ GPIO24.\\
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* 0: Not set\\
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* 1: The corresponding bit in GPIO_ENABLE_REG will be set to 1\\
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* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
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* Recommended operation: use this register to set GPIO_ENABLE_REG.\\
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*/
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uint32_t enable_w1ts:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_enable_w1ts_reg_t;
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/** Type of enable_w1tc register
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* GPIO output enable clear register
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*/
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typedef union {
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struct {
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/** enable_w1tc : WT; bitpos: [28:0]; default: 0;
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* Configures whether or not to clear the output enable register GPIO_ENABLE_REG of
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* GPIO0 ~ GPIO24. \\
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* 0: Not clear\\
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* 1: The corresponding bit in GPIO_ENABLE_REG will be cleared\\
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* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
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* Recommended operation: use this register to clear GPIO_ENABLE_REG.\\
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*/
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uint32_t enable_w1tc:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_enable_w1tc_reg_t;
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/** Type of in register
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* GPIO input register
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*/
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typedef union {
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struct {
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/** in_data_next : RO; bitpos: [28:0]; default: 0;
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* Represents the input value of GPIO0 ~ GPIO24. Each bit represents a pin input
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* value:\\
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* 0: Low level\\
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* 1: High level\\
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* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\
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*/
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uint32_t in_data_next:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_in_reg_t;
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/** Group: Interrupt Status Registers */
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/** Type of status register
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* GPIO interrupt status register
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*/
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typedef union {
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struct {
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/** status_interrupt : R/W/WTC; bitpos: [28:0]; default: 0;
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* The interrupt status of GPIO0 ~ GPIO24, can be configured by the software.
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*
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* - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
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* - Each bit represents the status of its corresponding GPIO:
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*
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* - 0: Represents the GPIO does not generate the interrupt configured by
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* GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software.
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* - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE,
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* or this bit is configured to 1 by the software.
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*
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*/
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uint32_t status_interrupt:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_status_reg_t;
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/** Type of status_w1ts register
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* GPIO interrupt status set register
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*/
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typedef union {
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struct {
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/** status_w1ts : WT; bitpos: [28:0]; default: 0;
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* Configures whether or not to set the interrupt status register
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* GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24.
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*
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* - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
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* - If the value 1 is written to a bit here, the corresponding bit in
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* GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this
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* register to set GPIO_STATUS_INTERRUPT.
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*/
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uint32_t status_w1ts:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_status_w1ts_reg_t;
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/** Type of status_w1tc register
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* GPIO interrupt status clear register
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*/
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typedef union {
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struct {
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/** status_w1tc : WT; bitpos: [28:0]; default: 0;
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* Configures whether or not to clear the interrupt status register
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* GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24.
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*
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* - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
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* - If the value 1 is written to a bit here, the corresponding bit in
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* GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this
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* register to clear GPIO_STATUS_INTERRUPT.
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*/
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uint32_t status_w1tc:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_status_w1tc_reg_t;
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/** Type of procpu_int register
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* CPU interrupt status register
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*/
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typedef union {
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struct {
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/** procpu_int : RO; bitpos: [28:0]; default: 0;
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* Represents the CPU interrupt status of GPIO0 ~ GPIO24. Each bit represents:\\
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* 0: Represents CPU interrupt is not enabled, or the GPIO does not generate the
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* interrupt configured by GPIO_PIN$n_INT_TYPE.\\
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* 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
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* after the CPU interrupt is enabled.\\
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* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. This
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* interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high)
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* enable signal (bit13 of GPIO_PIN$n_REG). \\
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*/
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uint32_t procpu_int:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_procpu_int_reg_t;
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/** Type of status_next register
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* GPIO interrupt source register
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*/
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typedef union {
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struct {
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/** status_interrupt_next : RO; bitpos: [28:0]; default: 0;
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* Represents the interrupt source signal of GPIO0 ~ GPIO24.\\
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* Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. Each
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* bit represents:\\
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* 0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.\\
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* 1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.\\
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* The interrupt could be rising edge interrupt, falling edge interrupt, level
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* sensitive interrupt and any edge interrupt.\\
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*/
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uint32_t status_interrupt_next:29;
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uint32_t reserved_29:3;
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};
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uint32_t val;
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} gpio_status_next_reg_t;
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/** Group: Pin Configuration Registers */
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/** Type of pinn register
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* GPIOn configuration register
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*/
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typedef union {
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struct {
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/** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
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* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
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* operating clock for the second-level synchronization.\\
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* 0: Not synchronize\\
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* 1: Synchronize on falling edge\\
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* 2: Synchronize on rising edge\\
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* 3: Synchronize on rising edge\\
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*/
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uint32_t pinn_sync2_bypass:2;
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/** pinn_pad_driver : R/W; bitpos: [2]; default: 0;
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* Configures to select pin drive mode. \\
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* 0: Normal output\\
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* 1: Open drain output \\
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*/
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uint32_t pinn_pad_driver:1;
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/** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
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* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
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* operating clock for the first-level synchronization.\\
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* 0: Not synchronize\\
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* 1: Synchronize on falling edge\\
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* 2: Synchronize on rising edge\\
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* 3: Synchronize on rising edge\\
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*/
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uint32_t pinn_sync1_bypass:2;
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uint32_t reserved_5:2;
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/** pinn_int_type : R/W; bitpos: [9:7]; default: 0;
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* Configures GPIO interrupt type.\\
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* 0: GPIO interrupt disabled\\
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* 1: Rising edge trigger\\
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* 2: Falling edge trigger\\
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* 3: Any edge trigger\\
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* 4: Low level trigger\\
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* 5: High level trigger\\
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*/
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uint32_t pinn_int_type:3;
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/** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0;
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* Configures whether or not to enable GPIO wake-up function.\\
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* 0: Disable\\
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* 1: Enable\\
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* This function only wakes up the CPU from Light-sleep. \\
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*/
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uint32_t pinn_wakeup_enable:1;
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uint32_t reserved_11:2;
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/** pinn_int_ena : R/W; bitpos: [17:13]; default: 0;
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* Configures whether or not to enable CPU interrupt.
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*
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* - bit13: Configures whether or not to enable CPU interrupt:\\
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* 0: Disable\\
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* 1: Enable\\
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* - bit14 ~ bit17: invalid
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*/
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uint32_t pinn_int_ena:5;
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uint32_t reserved_18:14;
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};
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uint32_t val;
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} gpio_pinn_reg_t;
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/** Group: Input Configuration Registers */
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/** Type of func0_in_sel_cfg register
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* Configuration register for input signal 0
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*/
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typedef union {
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struct {
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/** func_in_sel : R/W; bitpos: [5:0]; default: 48;
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* Configures to select a pin from the 25 GPIO pins to connect the input signal 0.\\
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* 0: Select GPIO0\\
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* 1: Select GPIO1\\
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* ......\\
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* 23: Select GPIO23\\
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* 24: Select GPIO24\\
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* Or\\
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* 0x20: A constantly high input\\
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* 0x30: A constantly low input\\
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*/
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uint32_t func_in_sel:6;
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/** func_in_inv_sel : R/W; bitpos: [6]; default: 0;
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* Configures whether or not to invert the input value.\\
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* 0: Not invert\\
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* 1: Invert\\
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*/
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uint32_t func_in_inv_sel:1;
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/** sig_in_sel : R/W; bitpos: [7]; default: 0;
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* Configures whether or not to route signals via GPIO matrix.\\
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* 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
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* IO MUX.\\
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* 1: Route signals via GPIO matrix.\\
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*/
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uint32_t sig_in_sel:1;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} gpio_func_in_sel_cfg_reg_t;
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/** Group: Output Configuration Registers */
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/** Type of funcn_out_sel_cfg register
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* Configuration register for GPIOn output
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*/
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typedef union {
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struct {
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/** funcn_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
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* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
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* output from GPIOn.\\
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* 0: Select signal 0\\
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* 1: Select signal 1\\
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* ......\\
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* 254: Select signal 254\\
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* 255: Select signal 255\\
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* Or\\
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* 256: Bit n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
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* output enable.
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*
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* For the detailed signal list, see Table <a
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* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
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* "
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*/
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uint32_t funcn_out_sel:9;
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/** funcn_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
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* Configures whether or not to invert the output value.\\
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* 0: Not invert\\
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* 1: Invert\\
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*/
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uint32_t funcn_out_inv_sel:1;
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/** funcn_oe_sel : R/W; bitpos: [10]; default: 0;
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* Configures to select the source of output enable signal.\\
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* 0: Use output enable signal from peripheral.\\
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* 1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG. \\
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*/
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uint32_t funcn_oe_sel:1;
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/** funcn_oe_inv_sel : R/W; bitpos: [11]; default: 0;
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* Configures whether or not to invert the output enable signal.\\
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* 0: Not invert\\
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* 1: Invert\\
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*/
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uint32_t funcn_oe_inv_sel:1;
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uint32_t reserved_12:20;
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};
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uint32_t val;
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} gpio_funcn_out_sel_cfg_reg_t;
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/** Group: Clock Gate Register */
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/** Type of clock_gate register
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* GPIO clock gate register
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*/
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typedef union {
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struct {
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/** clk_en : R/W; bitpos: [0]; default: 1;
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* Configures whether or not to enable clock gate.\\
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* 0: Not enable\\
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* 1: Enable, the clock is free running. \\
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*/
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uint32_t clk_en:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} gpio_clock_gate_reg_t;
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/** Group: Version Register */
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/** Type of date register
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* GPIO version register
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*/
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typedef union {
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struct {
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/** date : R/W; bitpos: [27:0]; default: 37753392;
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* Version control register. \\
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*/
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uint32_t date:28;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} gpio_date_reg_t;
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typedef struct {
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volatile gpio_strap_reg_t strap;
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volatile gpio_out_reg_t out;
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volatile gpio_out_w1ts_reg_t out_w1ts;
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volatile gpio_out_w1tc_reg_t out_w1tc;
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uint32_t reserved_010[9];
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volatile gpio_enable_reg_t enable;
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volatile gpio_enable_w1ts_reg_t enable_w1ts;
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volatile gpio_enable_w1tc_reg_t enable_w1tc;
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uint32_t reserved_040[9];
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volatile gpio_in_reg_t in;
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uint32_t reserved_068[3];
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volatile gpio_status_reg_t status;
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volatile gpio_status_w1ts_reg_t status_w1ts;
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volatile gpio_status_w1tc_reg_t status_w1tc;
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uint32_t reserved_080[9];
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volatile gpio_procpu_int_reg_t procpu_int;
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uint32_t reserved_0a8[3];
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volatile gpio_status_next_reg_t status_next;
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uint32_t reserved_0b8[3];
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volatile gpio_pinn_reg_t pinn[22]; // 0-21 are fanned out, 22-24 are not fanned out but padded out, 25-28 are not padded out. Only 0-21 are available.
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uint32_t reserved_11c[106];
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volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; //0-255. reserved: 1-5, 18-26, 36-40, 44-45, 48-63, 70-71, 75-81, 84-96, 101-117, 122-255;
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uint32_t reserved_4ac[256];
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volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[22];
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uint32_t reserved_b1c[183];
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volatile gpio_clock_gate_reg_t clock_gate;
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volatile gpio_date_reg_t date;
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} gpio_dev_t;
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extern gpio_dev_t GPIO;
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#ifndef __cplusplus
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_Static_assert(sizeof(gpio_dev_t) == 0xe00, "Invalid size of gpio_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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