kopia lustrzana https://github.com/cariboulabs/cariboulite
116 wiersze
2.8 KiB
Verilog
116 wiersze
2.8 KiB
Verilog
module complex_fifo #(
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parameter ADDR_WIDTH = 10,
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parameter DATA_WIDTH = 16
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)
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(
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input wire wr_rst_b_i,
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input wire wr_clk_i,
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input wire wr_en_i,
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input wire [2*DATA_WIDTH-1:0] wr_data_i,
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input wire rd_rst_b_i,
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input wire rd_clk_i,
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input wire rd_en_i,
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output reg [2*DATA_WIDTH-1:0] rd_data_o,
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output reg full_o,
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output reg empty_o,
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);
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reg [ADDR_WIDTH-1:0] wr_addr;
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reg [ADDR_WIDTH-1:0] wr_addr_gray;
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reg [ADDR_WIDTH-1:0] wr_addr_gray_rd;
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reg [ADDR_WIDTH-1:0] wr_addr_gray_rd_r;
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reg [ADDR_WIDTH-1:0] rd_addr;
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reg [ADDR_WIDTH-1:0] rd_addr_gray;
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reg [ADDR_WIDTH-1:0] rd_addr_gray_wr;
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reg [ADDR_WIDTH-1:0] rd_addr_gray_wr_r;
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// Initial conditions
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initial begin
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wr_addr <= 0;
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wr_addr_gray <= 0;
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full_o <= 0;
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rd_addr <= 0;
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rd_addr_gray <= 0;
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empty_o <= 1'b1;
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end
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function [ADDR_WIDTH-1:0] gray_conv;
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input [ADDR_WIDTH-1:0] in;
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begin
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gray_conv = {in[ADDR_WIDTH-1], in[ADDR_WIDTH-2:0] ^ in[ADDR_WIDTH-1:1]};
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end
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endfunction
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always @(posedge wr_clk_i/* or negedge wr_rst_b_i*/) begin
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if (wr_rst_b_i == 1'b0) begin
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wr_addr <= 0;
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wr_addr_gray <= 0;
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end else if (wr_en_i) begin
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wr_addr <= wr_addr + 1'b1;
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wr_addr_gray <= gray_conv(wr_addr + 1'b1);
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end
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end
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// synchronize read address to write clock domain
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always @(posedge wr_clk_i) begin
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rd_addr_gray_wr <= rd_addr_gray;
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rd_addr_gray_wr_r <= rd_addr_gray_wr;
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end
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always @(posedge wr_clk_i/* or negedge wr_rst_b_i*/) begin
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if (wr_rst_b_i == 1'b0) begin
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full_o <= 0;
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end else if (wr_en_i) begin
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full_o <= gray_conv(wr_addr + 2) == rd_addr_gray_wr_r;
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end else begin
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full_o <= full_o & (gray_conv(wr_addr + 1'b1) == rd_addr_gray_wr_r);
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end
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end
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always @(posedge rd_clk_i/* or negedge rd_rst_b_i*/) begin
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if (rd_rst_b_i == 1'b0) begin
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rd_addr <= 0;
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rd_addr_gray <= 0;
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end else if (rd_en_i) begin
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rd_addr <= rd_addr + 1'b1;
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rd_addr_gray <= gray_conv(rd_addr + 1'b1);
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end
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end
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// synchronize write address to read clock domain
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always @(posedge rd_clk_i) begin
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wr_addr_gray_rd <= wr_addr_gray;
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wr_addr_gray_rd_r <= wr_addr_gray_rd;
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end
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always @(posedge rd_clk_i/* or negedge rd_rst_b_i*/) begin
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if (rd_rst_b_i == 1'b0) begin
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empty_o <= 1'b1;
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end else if (rd_en_i) begin
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empty_o <= gray_conv(rd_addr + 1) == wr_addr_gray_rd_r;
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end else begin
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empty_o <= empty_o & (gray_conv(rd_addr) == wr_addr_gray_rd_r);
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end
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end
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always @(posedge rd_clk_i) begin
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if (rd_en_i) begin
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rd_data_o[15:0] <= mem_q[rd_addr][15:0];
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rd_data_o[31:16] <= mem_i[rd_addr][15:0];
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end
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end
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always @(posedge wr_clk_i) begin
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if (wr_en_i) begin
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mem_q[wr_addr] <= wr_data_i[15:0];
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mem_i[wr_addr] <= wr_data_i[31:16];
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end
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end
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reg [DATA_WIDTH-1:0] mem_i[(1<<ADDR_WIDTH)-1:0];
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reg [DATA_WIDTH-1:0] mem_q[(1<<ADDR_WIDTH)-1:0];
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endmodule
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