kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
59 wiersze
3.1 KiB
Tcl
59 wiersze
3.1 KiB
Tcl
## ================================================================================
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## Legal Notice: Copyright (C) 2021 Intel Corporation. All rights reserved.
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## Any megafunction design, and related net list (encrypted or decrypted),
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## support information, device programming or simulation file, and any other
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## associated documentation or information provided by Intel or a partner
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## under Intel's Megafunction Partnership Program may be used only to
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## program PLD devices (but not masked PLD devices) from Intel. Any other
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## use of such megafunction design, net list, support information, device
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## programming or simulation file, or any other related documentation or
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## information is prohibited for any other purpose, including, but not
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## limited to modification, reverse engineering, de-compiling, or use with
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## any other silicon devices, unless such use is explicitly licensed under
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## a separate agreement with Intel or a megafunction partner. Title to
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## the intellectual property, including patents, copyrights, trademarks,
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## trade secrets, or maskworks, embodied in any such megafunction design,
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## net list, support information, device programming or simulation file, or
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## any other related documentation or information provided by Intel or a
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## megafunction partner, remains with Intel, the megafunction partner, or
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## their respective licensors. No other licenses, including any licenses
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## needed under any third party's intellectual property, are provided herein.
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## ================================================================================
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##
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# Testbench simulation files
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set testbench_files [glob -nocomplain -- *.hex]
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set input_files [glob -nocomplain -- *input.txt]
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set file_dir [file dirname [info script]]
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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# Set test bench name
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set_global_assignment -name EDA_TEST_BENCH_NAME tb -section_id eda_simulation
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# Test bench settings
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set_global_assignment -name EDA_DESIGN_INSTANCE_NAME DUT -section_id tb
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set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME work.tx_ciccomp_tb -section_id tb
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set_global_assignment -name EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY work -section_id tb
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# Add Testbench files
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foreach i $testbench_files {
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set_global_assignment -name EDA_TEST_BENCH_FILE $i -section_id tb -library work
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}
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if {[file exists $file_dir/tx_ciccomp_coef_reload.txt]} {
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set_global_assignment -name EDA_TEST_BENCH_FILE $file_dir/tx_ciccomp_coef_reload.txt -section_id tb -library work
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}
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if {[file exists $file_dir/tx_ciccomp_coef_reload_rtl.txt]} {
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set_global_assignment -name EDA_TEST_BENCH_FILE $file_dir/tx_ciccomp_coef_reload_rtl.txt -section_id tb -library work
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}
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set_global_assignment -name EDA_TEST_BENCH_FILE $file_dir/tx_ciccomp_input.txt -section_id tb -library work
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set_global_assignment -name EDA_TEST_BENCH_FILE $file_dir/tx_ciccomp_tb.vhd -section_id tb -library work
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# Specify testbench mode for nativelink
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set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
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# Specify active testbench for nativelink
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set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb -section_id eda_simulation
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