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# Testbench simulation files
set testbench_files [glob -nocomplain -- *.hex]
set input_files [glob -nocomplain -- *input.txt]
set file_dir [file dirname [info script]]

set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation

# Set test bench name
set_global_assignment -name EDA_TEST_BENCH_NAME tb -section_id eda_simulation

# Test bench settings
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME DUT -section_id tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME work.tx_ciccomp_tb -section_id tb
set_global_assignment -name EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY work -section_id tb

# Add Testbench files 
foreach i $testbench_files {
  set_global_assignment -name EDA_TEST_BENCH_FILE $i -section_id tb -library work
}

if {[file exists $file_dir/tx_ciccomp_coef_reload.txt]} {
  set_global_assignment -name EDA_TEST_BENCH_FILE $file_dir/tx_ciccomp_coef_reload.txt -section_id tb -library work
}
if {[file exists $file_dir/tx_ciccomp_coef_reload_rtl.txt]} {
  set_global_assignment -name EDA_TEST_BENCH_FILE $file_dir/tx_ciccomp_coef_reload_rtl.txt -section_id tb -library work
}
set_global_assignment -name EDA_TEST_BENCH_FILE $file_dir/tx_ciccomp_input.txt -section_id tb -library work

set_global_assignment -name EDA_TEST_BENCH_FILE $file_dir/tx_ciccomp_tb.vhd -section_id tb -library work

# Specify testbench mode for nativelink
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation

# Specify active testbench for nativelink
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb -section_id eda_simulation