| .. |
|
.qsys_edit
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
DEBUG
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
DEBUG2
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
clock_buffer
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
nco
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
rx_cic
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
rx_ciccomp
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
rx_ciccomp_sim
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
tx_cic
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
tx_ciccomp
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
tx_ciccomp_sim
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
tx_nco
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
ADC_Latch.bsf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
ADC_Latch.qip
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
ADC_Latch.v
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
DAC_corrector.bsf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
DAC_corrector.v
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
DEBUG.qsys
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
DEBUG.sopcinfo
|
Update VCXO corrector PLL
|
2022-02-06 13:43:50 +03:00 |
|
DEBUG2.qsys
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
DEBUG2.sopcinfo
|
Update VCXO corrector PLL
|
2022-02-06 13:43:50 +03:00 |
|
Debug_Probes.spf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
MAIN_PLL.bsf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
MAIN_PLL.ppf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
MAIN_PLL.qip
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
MAIN_PLL.v
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
SDC.sdc
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
WOLF-LITE.bdf
|
Update VCXO corrector PLL
|
2022-02-06 13:43:50 +03:00 |
|
WOLF-LITE.cof
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
WOLF-LITE.qpf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
WOLF-LITE.qsf
|
VCXO PWM
|
2022-02-06 12:19:39 +03:00 |
|
WOLF-LITE.qws
|
Update VCXO corrector PLL
|
2022-02-06 13:43:50 +03:00 |
|
WOLF-LITE.srf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
WOLF-LITE_description.txt
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
WOLF_assignment_defaults.qdf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
WOLF_description.txt
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
auto_convert.tcl
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
clock_buffer.qsys
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
clock_buffer.sopcinfo
|
Update VCXO corrector PLL
|
2022-02-06 13:43:50 +03:00 |
|
dac_null.bsf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
dac_null.qip
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
dac_null.v
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
data_shifter.bsf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
data_shifter.v
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
dcdc_pll.bsf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
dcdc_pll.ppf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
dcdc_pll.qip
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
dcdc_pll.v
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
diffclock_buff.bsf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
diffclock_buff.qip
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
diffclock_buff.v
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
mixer.bsf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
mixer.qip
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
mixer.v
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
mux1.bsf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
mux1.qip
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
mux1.v
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
mux14.bsf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
mux14.qip
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
mux14.v
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
mux16.bsf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
mux16.qip
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
mux16.v
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
nco.qsys
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
nco.sopcinfo
|
Update VCXO corrector PLL
|
2022-02-06 13:43:50 +03:00 |
|
rx_cic.qsys
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
rx_cic.sopcinfo
|
Update VCXO corrector PLL
|
2022-02-06 13:43:50 +03:00 |
|
rx_ciccomp.bsf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
rx_ciccomp.cmp
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
rx_ciccomp.qip
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
rx_ciccomp.sip
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
rx_ciccomp.spd
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
rx_ciccomp.v
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
rx_ciccomp_sim.f
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
spi_interface.bsf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
spi_interface.v
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
stm32_interface.bsf
|
VCXO PWM
|
2022-02-06 12:19:39 +03:00 |
|
stm32_interface.v
|
VCXO PWM
|
2022-02-06 12:19:39 +03:00 |
|
tx_cic.qsys
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
tx_cic.sopcinfo
|
Update VCXO corrector PLL
|
2022-02-06 13:43:50 +03:00 |
|
tx_ciccomp.bsf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
tx_ciccomp.cmp
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
tx_ciccomp.qip
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
tx_ciccomp.sip
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
tx_ciccomp.spd
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
tx_ciccomp.v
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
tx_ciccomp_sim.f
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
tx_mixer.bsf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
tx_mixer.qip
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
tx_mixer.v
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
tx_nco.qsys
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
tx_nco.sopcinfo
|
Update VCXO corrector PLL
|
2022-02-06 13:43:50 +03:00 |
|
tx_pll.bsf
|
Update VCXO corrector PLL
|
2022-02-06 13:43:50 +03:00 |
|
tx_pll.ppf
|
Update VCXO corrector PLL
|
2022-02-06 13:43:50 +03:00 |
|
tx_pll.qip
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
tx_pll.v
|
Update VCXO corrector PLL
|
2022-02-06 13:43:50 +03:00 |
|
tx_summator.bsf
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
tx_summator.qip
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
tx_summator.v
|
F61.440
|
2021-10-26 20:53:31 +03:00 |
|
vcxo_controller.bsf
|
VCXO PWM
|
2022-02-06 12:19:39 +03:00 |
|
vcxo_controller.v
|
VCXO PWM
|
2022-02-06 12:19:39 +03:00 |
bbe7b23df7