kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
177 wiersze
6.4 KiB
Tcl
177 wiersze
6.4 KiB
Tcl
## ================================================================================
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## Legal Notice: Copyright (C) 1991-2021 Altera Corporation. All rights reserved.
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## Any megafunction design, and related net list (encrypted or decrypted),
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## support information, device programming or simulation file, and any other
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## associated documentation or information provided by Altera or a partner
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## under Altera's Megafunction Partnership Program may be used only to
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## program PLD devices (but not masked PLD devices) from Altera. Any other
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## use of such megafunction design, net list, support information, device
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## programming or simulation file, or any other related documentation or
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## information is prohibited for any other purpose, including, but not
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## limited to modification, reverse engineering, de-compiling, or use with
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## any other silicon devices, unless such use is explicitly licensed under
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## a separate agreement with Altera or a megafunction partner. Title to
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## the intellectual property, including patents, copyrights, trademarks,
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## trade secrets, or maskworks, embodied in any such megafunction design,
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## net list, support information, device programming or simulation file, or
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## any other related documentation or information provided by Altera or a
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## megafunction partner, remains with Altera, the megafunction partner, or
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## their respective licensors. No other licenses, including any licenses
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## needed under any third party's intellectual property, are provided herein.
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## ================================================================================
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##
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transcript on
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write transcript rx_ciccomp_transcript
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# START MEGAWIZARD INSERT VARIABLES
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set top_entity rx_ciccomp
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set timing_resolution "1ps"
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set core_version 18.1
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set device_family "Cyclone IV E"
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set quartus_rootdir C:/intelfpga/18.1/quartus/
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# Change to "gate_level" for gate-level sim
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set sim_type "rtl"
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# END MEGAWIZARD INSERT VARIABLES
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set q_sim_lib [file join $quartus_rootdir eda sim_lib]
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# Close existing ModelSim simulation
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quit -sim
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if {[file exists [file join simulation modelsim ${top_entity}.vo]] && [string match "gate_level" $sim_type]} {
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puts "Info: Gate Level ${top_entity}.vo found"
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set language_ext "vo"
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set use_ipfs 1
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set flow "gate_level"
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} elseif {[file exists [file join simulation modelsim ${top_entity}.vho]] && [string match "gate_level" $sim_type]} {
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puts "Info: Gate Level ${top_entity}.vho found"
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set language_ext "vho"
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set use_ipfs 1
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set flow "gate_level"
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} else {
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puts "Info: RTL simulation."
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set use_ipfs 0
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set flow "rtl"
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}
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if {[string match $flow "gate_level"] } {
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file copy ${top_entity}_input.txt simulation/modelsim
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cd simulation/modelsim
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}
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regsub {[ ]+} $device_family "" temp_device_family
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regsub {[ ]+} $temp_device_family "" temp_device_family2
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set device_lib_name [string tolower $temp_device_family2]
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set libs [list \
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$device_lib_name \
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altera \
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work]
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foreach {lib} $libs {
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if {[file exist $lib]} {
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catch {eval "file delete -force -- $lib"} fid
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puts "file delete command returned $fid\n"
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}
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if {[file exist $lib] == 0} {
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vlib $lib
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vmap $lib $lib
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}
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}
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# RTL Simulation
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# Compile all required simulation library files
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set quartus_libs [list \
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altera_mf {altera_mf_components altera_mf} {} {} "$q_sim_lib" \
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lpm {220pack 220model} {220model} {} "$q_sim_lib" \
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sgate {sgate_pack sgate} {sgate} {} "$q_sim_lib" \
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altera_lnsim {altera_lnsim_components} {} {mentor/altera_lnsim_for_vhdl} "$q_sim_lib" \
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twentynm {twentynm_atoms twentynm_components} {} {} "$q_sim_lib" \
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]
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foreach {lib file_vhdl_list file_verilog_list file_sysverilog_list src_files_loc} $quartus_libs {
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if {[file exist $lib]} {
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catch {eval "file delete -force -- $lib"} fid
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puts "file delete command returned $fid\n"
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}
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if {[file exist $lib] == 0} {
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vlib $lib
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vmap $lib $lib
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}
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foreach file_item $file_vhdl_list {
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catch {vcom -quiet -explicit -93 -work $lib [file join $src_files_loc ${file_item}.vhd]} err_msg
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if {![string match "" $err_msg]} {return $err_msg}
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}
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foreach file_item $file_verilog_list {
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catch {vlog -work $lib [file join $src_files_loc ${file_item}.v]} err_msg
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if {![string match "" $err_msg]} {return $err_msg}
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}
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foreach file_item $file_sysverilog_list {
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catch {vlog -work $lib [file join $src_files_loc ${file_item}.sv]} err_msg
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if {![string match "" $err_msg]} {return $err_msg}
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}
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}
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vcom -93 -work altera $q_sim_lib/altera_primitives_components.vhd
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vcom -93 -work altera $q_sim_lib/altera_primitives.vhd
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# Compile all FIR Compiler II RTL files
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vlog -work work altera_avalon_sc_fifo.v
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vcom -work work dspba_library_package.vhd
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vcom -work work dspba_library.vhd
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vcom -work work auk_dspip_roundsat_hpfir.vhd
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vcom -work work auk_dspip_math_pkg_hpfir.vhd
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vcom -work work auk_dspip_lib_pkg_hpfir.vhd
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vcom -work work auk_dspip_avalon_streaming_controller_hpfir.vhd
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vcom -work work auk_dspip_avalon_streaming_sink_hpfir.vhd
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vcom -work work auk_dspip_avalon_streaming_source_hpfir.vhd
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set file_list [glob ${top_entity}_rtl*.vhd]
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foreach cur_file $file_list {
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vcom -work work $cur_file
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}
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vcom -work work ${top_entity}_ast.vhd
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vcom -work work ${top_entity}.vhd
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vcom -93 -work work ${top_entity}_tb.vhd
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# Prepare simulation command
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set vsim_cmd vsim
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if {[string match $flow "rtl"]} {
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lappend vsim_cmd "-L" "$device_lib_name" "-L" "altera_mf" "-L" "lpm" "-L" "sgate" "-L" "altera" "-L" "altera_lnsim" "-L" "work"
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} else {
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lappend vsim_cmd "-L" "$device_lib_name" "-L" "altera" "-L" "work"
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if {[string match $language_ext "vho"]} {
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if {[file exists ${top_entity}_vhd.sdo]} {
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lappend vsim_cmd "-sdftyp" "/${top_entity}_tb/DUT=${top_entity}_vhd.sdo"}
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}
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if {[string match $language_ext "vo"]} {
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if {[file exists ${top_entity}_v.sdo]} {
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lappend vsim_cmd "-sdftyp" "/${top_entity}_tb/DUT=${top_entity}_v.sdo"}
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}
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}
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lappend vsim_cmd "work.${top_entity}_tb" "-t" "$timing_resolution"
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catch { eval $vsim_cmd } vsim_msg
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puts $vsim_msg
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if {[file exists "wave.do"]} {
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do wave.do
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} else {
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add wave sim:/${top_entity}_tb/*
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}
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# Start simulation silently
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set StdArithNoWarnings 1
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run 0 ns
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set StdArithNoWarnings 0
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catch {run -all} run_msg
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puts $run_msg
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