kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
14 wiersze
329 B
VHDL
14 wiersze
329 B
VHDL
component clock_buffer is
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port (
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inclk : in std_logic := 'X'; -- inclk
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outclk : out std_logic -- outclk
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);
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end component clock_buffer;
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u0 : component clock_buffer
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port map (
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inclk => CONNECTED_TO_inclk, -- altclkctrl_input.inclk
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outclk => CONNECTED_TO_outclk -- altclkctrl_output.outclk
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);
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