kopia lustrzana https://github.com/ArjanteMarvelde/uSDR-pico
ArjanteMarvelde
rodzic
53e7c155f5
commit
caaf154a13
7
dsp.c
7
dsp.c
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@ -338,13 +338,14 @@ bool __not_in_flash_func(dsp_callback)(repeating_timer_t *t)
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// Crude AGC mechanism **TO BE IMPROVED**
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if (!tx_enabled)
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{
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// Approximate amplitude, with alpha max + beta min function
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uint32_t i=adc_level[1],q=adc_level[0];
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if (i>q)
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temp = (MAX(i,((29*i/32) + (61*q/128))))>>LSH;
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else
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temp = (MAX(q,((29*q/32) + (61*i/128))))>>LSH;
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s_rssi = MAX(1,temp);
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rx_agc = AGC_TOP/s_rssi; // calculate required AGC factor
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rx_agc = AGC_TOP/s_rssi; // calculate scaling factor
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if (rx_agc==0) rx_agc=1;
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}
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@ -363,7 +364,7 @@ bool __not_in_flash_func(dsp_callback)(repeating_timer_t *t)
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pwm_set_gpio_level(22, A_buf[dsp_active][dsp_tick] + DAC_BIAS); // Output A to DAC
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}
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// When sample buffer is full, move pointer and signal DSP loop
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// When sample buffer is full, move pointer to next and signal the DSP loop
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if (++dsp_tick >= BUFSIZE) // Increment tick and check range
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{
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dsp_tick = 0; // Reset counter
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@ -505,7 +506,7 @@ void __not_in_flash_func(dsp_loop)()
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rx(); // Do RX signal processing
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}
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/////// This is a trap, ptt remains active after once asserted
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/////// This is a trap, ptt remains active after once asserted: to be checked!
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tx_enabled = vox_active || ptt_active; // Check RX or TX
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#if DSP_FFT == 1
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289
si5351.c
289
si5351.c
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@ -9,30 +9,35 @@
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Si5351 principle of operation:
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==============================
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Crystal frequency <Fxtal> (usually 25MHz) is multiplied in a PLL by <MSN> to obtain <Fvco>.
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PLL A and B have independent MSN values, the <Fout> on channel <i> can be derived from either.
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<Fvco> must be between 600MHz and 900MHz, but the spec is more relaxed in reality.
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<Fvco> is divided by <MSi> and <Ri> to obtain the output frequency <Fout>.
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<MSi> and <Ri> are selected to be in the ballpark of desired frequency range.
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<MSN> is then used for tuning <Fout>.
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Only certain values of <MSi> and <Ri> are allowed when quadrature output is required.
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Crystal frequency Fxtal (usually 25MHz) is multiplied in a PLL by MSN to obtain Fvco.
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PLLs A and B have independent MSN values, leading to two Fvco frequencies.
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The output Fout on each channel (i) can be derived from either Fvco.
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Fvco must be between 600MHz and 900MHz, but the spec is more relaxed in reality.
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In the second stage, an Fvco is divided by MSi and Ri to obtain the output frequency Fout.
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Only certain values of MSi and Ri are allowed when quadrature output is required.
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Tuning stragtegy:
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MSi and Ri are selected to be in the ballpark of desired frequency range.
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MSN is then used for tuning Fout.
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+-------+ +-------+ +------+
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- Fxtal --> | * MSN | -- Fvco --> | / MSi | --> | / Ri | -- Fout -->
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+-------+ +-------+ +------+
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Details:
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========
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---Derivation of Fout---
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+-------+ +-------+ +------+
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Fxtal --> | * MSN | -- Fvco --> | / MSi | --> | / Ri | -- Fout -->
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+-------+ +-------+ +------+
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MSN determines: Fvco = Fxtal * (MSN) , where MSN = a + b/c
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MSi and Ri determine: Fout = Fvco / (Ri*MSi) , where MSi = a + b/c (different a, b and c)
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MSi and Ri determine: Fout = Fvco / (Ri*MSi) , where MSi = a + b/c (note: different a, b and c)
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---Derivation of the register values, that determine MSN and MSi---
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P1 = 128*a + Floor(128*b/c) - 512
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P2 = 128*b - c*Floor(128*b/c) (P2 = 0 for MSi integer mode, or calculated for MSN tuning)
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P3 = c (P3 = 1 for MSi integer mode, or P3 = 1000000 for MSN tuning)
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P1 = 128*a + Floor(128*b/c) - 512 (P1 = calculated for MSN tuning, P1 = 750MHz/Fout for MSi integer mode)
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P2 = 128*b - c*Floor(128*b/c) (P2 = calculated for MSN tuning, P2 = 0 for MSi integer mode)
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P3 = c (P3 = c = 1000000 for MSN tuning, P3 = 1 for MSi integer mode)
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This VFO implementation assumes PLLA is used for VFO0 (clk0 and clk1), and PLLB is used for VFO1 (clk2)
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This VFO implementation assumes PLLA is used for VFO 0 (clk0 and clk1), and PLLB is used for VFO 1 (clk2)
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The algorithm to get from required Fout to synthesizer settings:
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| calculate new <MSN> from the desired <Fout>, based on the current <Ri> and <MSi>
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@ -46,28 +51,35 @@ Details:
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| reset PLL
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(this all assumes that the current settings are consistent, i.e. must be initialized at startup)
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Some boundary values:
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Ri MSi Lo MHz Hi MHz
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1 4 150.000000 225.000000
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1 126 4.761905 7.142857
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32 4 4.687500 7.031250
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32 126 0.148810 0.223214
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128 4 1.171875 1.757813
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128 126 0.037202 0.055804
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Calculate MSi:
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MSi = 750MHz/(Fout*Ri) // Target for mid-band, i.e. Fvco=750MHz
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MSi &= 0xfe // Make it even, minimum is 4 in case of integer mode
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MSi: target for mid-band, i.e. Fvco=750MHz
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MSi = 750MHz/(Fout*Ri)
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MSi &= 0xfe // Make it even
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Calculate MSN:
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MSN = MSi*Ri*Fout/Fxtal (spec mandates between 24 and 36, but could be stretched)
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Some boundary values, assuming 600M < Fvco < 900M.
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With low end 400M, Low MHz is multiplied with 2/3.
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------------+--------------+-----------------------+
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Ri MSi : a b c | Low MHz High MHz
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1 4 : 4 0 1 | 150.000000 225.000000
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1 126 : 126 0 1 | 4.761905 7.142857
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32 4 : 4 0 1 | 4.687500 7.031250
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32 126 : 126 0 1 | 0.148810 0.223214
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128 4 : 4 0 1 | 1.171875 1.757813
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128 126 : 126 0 1 | 0.037202 0.055804
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MSN = MSi*Ri*Fout/Fxtal (should be between 24 and 36)
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NOTE: Phase offsets
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The PHOFF is given as a multiple of 1/(4*Fvco), so when MSi == PHOFF the shift will be 90deg.
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It also implies that MSi must be an integer, and Ri == 1.
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Only use MSi even-integers, i.e. d=[4, 6, 8..126], e=0 and f=100000, and set INT bits in reg 22, 23.
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Only use MSi even-integers, i.e. a=[4, 6, 8..126], b=0 and c=100000, and set INT bits in reg 22, 23.
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Quadrature Phase offsets (i.e. delay):
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- Offset for MS0 (reg 165) must be 0 (cosine),
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- Offset for MS1 (reg 166) must be equal to divider MS1 for 90 deg (sine),
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- Phase offset for MS0 (reg 165) must be 0 (cos: delay = 0),
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- Phase offset for MS1 (reg 166) must be equal to divider MS1 for 90 deg (sin: delay = MSi / 4*Fvco),
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- Set INV bit (reg 17) to add 180 deg.
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NOTE: Phase offsets only work when Ri = 1,
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This implies that minimum Fout is 4.762MHz at Fvco = 600MHz.
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Additional flip/flop dividers are needed to get down to 80m band frequencies, or Fvco must be tuned below spec.
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@ -180,7 +192,7 @@ Control Si5351 (see AN619):
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#define SI_XTAL_FREQ 25001414UL // Replace with measured crystal frequency of XTAL for CL = 10pF (default)
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#define SI_MSN_LO ((0.6e9)/SI_XTAL_FREQ)
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#define SI_MSN_LO ((0.4e9)/SI_XTAL_FREQ) // Should be 600M, but 400MHz works too
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#define SI_MSN_HI ((0.9e9)/SI_XTAL_FREQ)
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#define SI_PLL_C 1000000UL // Parameter c for PLL-A and -B setting
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@ -190,7 +202,7 @@ typedef struct
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uint32_t freq; // type can hold up to 4GHz
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uint8_t flag; // flag != 0 when update needed
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uint8_t phase; // in quarter waves (0, 1, 2, 3)
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uint8_t ri; // Ri (1 .. 128)
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uint8_t ri; // Ri (1 .. 128), but should be 1 for VFO 0
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uint8_t msi; // MSi parameter a (4, 6, 8 .. 126)
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double msn; // MSN (24.0 .. 35.9999)
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} vfo_t;
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@ -230,11 +242,11 @@ void si_enable(int i, bool en)
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data[0] = SI_CLK_OE;
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if (i==0)
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{
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data[1] = en ? data[1]&~SI_VFO0_DISABLE : data[1]|SI_VFO0_DISABLE;
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data[1] = en ? data[1]&~SI_VFO0_DISABLE : data[1]|SI_VFO0_DISABLE; // clk0 and clk1
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}
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else
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{
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data[1] = en ? data[1]&~SI_VFO1_DISABLE : data[1]|SI_VFO1_DISABLE;
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data[1] = en ? data[1]&~SI_VFO1_DISABLE : data[1]|SI_VFO1_DISABLE; // clk2
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}
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i2c_write_blocking(i2c0, I2C_VFO, &data[0], 2, false);
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}
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@ -258,19 +270,26 @@ int si_getreg(uint8_t *data, uint8_t reg, uint8_t len)
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* Set up MSN PLL divider for vfo[i], assuming MSN has been set in vfo[i]
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* Optimize for speed, this may be called with short intervals
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* See also SiLabs AN619 section 3.2
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* VFO 0 refers to PLL a, VFO 1 refers to PLL B
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MSN = a + b/c
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c = 1000000 (Fxtal/c step size)
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P1 = 128*a + Floor(128*b/c) - 512
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P2 = 128*b - c*Floor(128*b/c)
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P3 = c
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*/
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void si_setmsn(int i)
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{
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uint8_t data[16]; // I2C trx buffer
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uint32_t P1, P2; // MSN parameters
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uint32_t A;
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uint32_t B;
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uint32_t P1, P2; // MSN parameters, P3 is SI_PLL_C
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uint32_t A, B;
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if ((i<0)||(i>1)) return; // Check VFO range
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A = (uint32_t)(floor(vfo[i].msn)); // A is integer part of MSN
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B = (uint32_t)((vfo[i].msn - (double)A) * SI_PLL_C); // B is C * fraction part of MSN (C is a constant)
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P2 = (uint32_t)(floor((double)(128 * B) / (double)SI_PLL_C));
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P2 = (uint32_t)(floor((double)(128 * B) / (double)SI_PLL_C)); // use P2 for intermediate result..
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P1 = (uint32_t)(128 * A + P2 - 512);
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P2 = (uint32_t)(128 * B - SI_PLL_C * P2);
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@ -293,7 +312,13 @@ void si_setmsn(int i)
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/*
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* Set up registers with MS and R divider for vfo[i], assuming values have been set in vfo[i]
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* In this implementation we only use integer mode, i.e. b=0 and P3=1
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* See also SiLabs AN619 section 4.1
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MSi = a + b/c
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c = 1, b=0
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P1 = 128*a - 512
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P2 = 0
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P3 = c
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*/
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void si_setmsi(uint8_t i)
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{
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@ -301,7 +326,7 @@ void si_setmsi(uint8_t i)
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uint32_t P1;
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uint8_t R;
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i=(i>0?1:0);
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if ((i<0)||(i>1)) return; // Check VFO range
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P1 = (uint32_t)(128*(uint32_t)floor(vfo[i].msi) - 512);
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R = vfo[i].ri;
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@ -321,13 +346,13 @@ void si_setmsi(uint8_t i)
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data[8] = 0x00;
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i2c_write_blocking(i2c0, I2C_VFO, data, 9, false);
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// If vfo[0] also set clk 1
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// If vfo[0] also set clk 1 and phase offset, (integer mode and high drive current for low phase noise).
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if (i==0)
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{
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data[0] = SI_SYNTH_MS1; // Same data in synthesizer
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i2c_write_blocking(i2c0, I2C_VFO, data, 9, false);
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if (vfo[0].phase&1) // Phase is either 90 or 270 deg?
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if (vfo[0].phase&(PH000|PH270)) // Phase is either 90 or 270 deg?
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{
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data[0] = SI_CLK1_PHOFF;
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data[1] = vfo[0].msi; // offset == MSi for 90deg
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@ -339,12 +364,24 @@ void si_setmsi(uint8_t i)
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data[1] = 0; // offset == 0 for 0deg
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i2c_write_blocking(i2c0, I2C_VFO, data, 2, false);
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}
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if (vfo[0].phase&2) // Phase is 180 or 270 deg?
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if (vfo[0].phase&(PH180|PH270)) // Phase is 180 or 270 deg?
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{
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data[0] = SI_CLK1_CTL; // Then set the invert flag
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data[1] = 0x5d; // CLK1: INT, PLLA, INV, MS, 8mA
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data[0] = SI_CLK1_CTL; // set the invert flag
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data[1] = 0x1f; // CLK1: nonINT, PLLA, INV, MS, 8mA
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i2c_write_blocking(i2c0, I2C_VFO, data, 2, false);
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}
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else
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{
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data[0] = SI_CLK1_CTL; // clear the invert flag
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data[1] = 0x0f; // CLK1: nonINT, PLLA, nonINV, MS, 8mA
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i2c_write_blocking(i2c0, I2C_VFO, data, 2, false);
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}
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}
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else
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{
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data[0] = SI_CLK2_CTL; // set the invert flag
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data[1] = 0x2f; // CLK2: nonINT, PLLB, nonINV, MS, 8mA
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i2c_write_blocking(i2c0, I2C_VFO, data, 2, false);
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}
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// Reset associated PLL
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@ -355,10 +392,13 @@ void si_setmsi(uint8_t i)
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/*
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* This function needs to be invoked at regular intervals, e.g. 10x per sec. See hmi.c
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* For each vfo, calculate required MSN setting, MSN = MSi*Ri*Fout/Fxtal
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* If in range, just set MSN registers
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* If not in range, recalculate MSi and Ri and also MSN
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* Set MSN, MSi and Ri registers (implicitly resets PLL)
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* If still in range,
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* then just set MSN registers
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* else,
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* recalculate MSi and Ri as well
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* set MSN, MSi and Ri registers (implicitly resets PLL)
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*/
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void si_evaluate(void)
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{
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@ -369,20 +409,22 @@ void si_evaluate(void)
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msn = (double)(vfo[0].msi); // Re-calculate MSN
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msn = msn * (double)(vfo[0].ri);
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msn = msn * (double)(vfo[0].freq) / SI_XTAL_FREQ;
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if ((msn>=SI_MSN_LO)&&(msn<SI_MSN_HI))
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if ((msn>=SI_MSN_LO)&&(msn<SI_MSN_HI)) // Check MSN range
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{
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vfo[0].msn = msn;
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si_setmsn(0);
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}
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else
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{
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// Pre-scale Ri, stretch down Ri=1 range
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if (vfo[0].freq<1000000)
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vfo[0].ri = 128;
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else if (vfo[0].freq<3000000)
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// Pre-scale Ri, stretch down Ri=1 range to 3MHz
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// Otherwise use just 32 and 128
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if (vfo[0].freq>3000000)
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vfo[0].ri = 1;
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else if (vfo[0].freq>1000000)
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vfo[0].ri = 32;
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else
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vfo[0].ri = 1;
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vfo[0].ri = 128;
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// Set MSi
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if ((vfo[0].freq >= 3000000)&&(vfo[0].freq < 6000000)) // Handle Low end of Ri=1 range
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@ -402,6 +444,40 @@ void si_evaluate(void)
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}
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if (vfo[1].flag)
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{
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msn = (double)(vfo[1].msi); // Re-calculate MSN
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msn = msn * (double)(vfo[1].ri);
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msn = msn * (double)(vfo[1].freq) / SI_XTAL_FREQ;
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if ((msn>=SI_MSN_LO)&&(msn<SI_MSN_HI)) // Check MSN range
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{
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vfo[1].msn = msn;
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si_setmsn(1);
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}
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else
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{
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// Pre-scale Ri, stretch down Ri=1 range to 3MHz
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// Otherwise use just 32 and 128
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if (vfo[1].freq>3000000)
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vfo[1].ri = 1;
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else if (vfo[1].freq>1000000)
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vfo[1].ri = 32;
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else
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vfo[1].ri = 128;
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// Set MSi
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if ((vfo[1].freq >= 3000000)&&(vfo[1].freq < 6000000)) // Handle Low end of Ri=1 range
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vfo[1].msi = (uint8_t)126; // Maximum MSi on Fvco=(4x126)MHz
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else // Or calculate MSi on Fvco=750MHz
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vfo[1].msi = (uint8_t)(750000000UL / (vfo[1].freq * vfo[1].ri)) & 0x000000fe;
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msn = (double)(vfo[1].msi); // Re-calculate MSN
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msn = msn * (double)(vfo[1].ri);
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msn = msn * (double)(vfo[1].freq) / SI_XTAL_FREQ;
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vfo[1].msn = msn;
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si_setmsn(1);
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si_setmsi(1);
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}
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vfo[1].flag = 0;
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}
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}
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@ -409,92 +485,39 @@ void si_evaluate(void)
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/*
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* Initialize the Si5351 VFO registers
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* Hard initialize Synth registers to: 7.074MHz, CLK1 90 deg ahead, PLLA for CLK 0&1, PLLB for CLK2
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| Ri=1,
|
||||
| MSi=68, P1=8192, P2=0, P3=1
|
||||
| MSN=27.2 P1=2969, P2=600000, P3=1000000
|
||||
*/
|
||||
void si_init(void)
|
||||
{
|
||||
uint8_t data[16]; // I2C trx buffer
|
||||
|
||||
vfo[0].freq = 10000000; // Check this, should be 7074000?
|
||||
vfo[0].flag = 0;
|
||||
vfo[0].phase = 1;
|
||||
vfo[0].ri = 1;
|
||||
vfo[0].msi = 68;
|
||||
vfo[0].msn = 27.2;
|
||||
vfo[1].freq = 10000000; // Check this, should be 7074000?
|
||||
vfo[1].flag = 0;
|
||||
vfo[1].phase = 0;
|
||||
vfo[1].ri = 1;
|
||||
vfo[1].msi = 68;
|
||||
vfo[1].msn = 27.2;
|
||||
|
||||
// PLLA: MSN P1=0x00000b99, P2=0x000927c0, P3=0x000f4240
|
||||
data[0] = SI_SYNTH_PLLA;
|
||||
data[1] = 0x42; // MSNA_P3[15:8]
|
||||
data[2] = 0x40; // MSNA_P3[7:0]
|
||||
data[3] = 0x00; // 0b000000 , MSNA_P1[17:16]
|
||||
data[4] = 0x0b; // MSNA_P1[15:8]
|
||||
data[5] = 0x99; // MSNA_P1[7:0]
|
||||
data[6] = 0xf9; // MSNA_P3[19:16] , MSNA_P2[19:16]
|
||||
data[7] = 0x27; // MSNA_P2[15:8]
|
||||
data[8] = 0xc0; // MSNA_P2[7:0]
|
||||
i2c_write_blocking(i2c0, I2C_VFO, data, 9, false);
|
||||
|
||||
|
||||
// PLLB: MSN P1=0x00000b99, P2=0x000927c0, P3=0x000f4240
|
||||
data[0] = SI_SYNTH_PLLB; // Same content
|
||||
i2c_write_blocking(i2c0, I2C_VFO, data, 9, false);
|
||||
|
||||
// MS0 P1=0x00002000, P2=0x00000000, P3=0x00000001, R=1
|
||||
data[0] = SI_SYNTH_MS0;
|
||||
data[1] = 0x00; // MS0_P3[15:8]
|
||||
data[2] = 0x01; // MS0_P3[7:0]
|
||||
data[3] = 0x00; // 0b0, R0_DIV[2:0] , MS0_DIVBY4[1:0] , MS0_P1[17:16]
|
||||
data[4] = 0x20; // MS0_P1[15:8]
|
||||
data[5] = 0x00; // MS0_P1[7:0]
|
||||
data[6] = 0x00; // MS0_P3[19:16] , MS0_P2[19:16]
|
||||
data[7] = 0x00; // MS0_P2[15:8]
|
||||
data[8] = 0x00; // MS0_P2[7:0]
|
||||
i2c_write_blocking(i2c0, I2C_VFO, data, 9, false);
|
||||
|
||||
// MS1 P1=0x00002000, P2=0x00000000, P3=0x00000001, R=1
|
||||
data[0] = SI_SYNTH_MS1; // Same content
|
||||
i2c_write_blocking(i2c0, I2C_VFO, data, 9, false);
|
||||
|
||||
// MS2 P1=0x00002000, P2=0x00000000, P3=0x00000001, R=1
|
||||
data[0] = SI_SYNTH_MS2; // Same content
|
||||
i2c_write_blocking(i2c0, I2C_VFO, data, 9, false);
|
||||
|
||||
// Phase offsets for 3 clocks
|
||||
data[0] = SI_CLK0_PHOFF;
|
||||
data[1] = 0x00; // CLK0: phase 0 deg
|
||||
data[2] = 0x44; // CLK1: phase 90 deg (=MSi)
|
||||
data[3] = 0x00; // CLK2: phase 0 deg
|
||||
i2c_write_blocking(i2c0, I2C_VFO, data, 4, false);
|
||||
|
||||
// Output port settings for 3 clocks
|
||||
data[0] = SI_CLK0_CTL;
|
||||
data[1] = 0x4d; // CLK0: INT, PLLA, nonINV, MS, 4mA
|
||||
data[2] = 0x4d; // CLK1: INT, PLLA, nonINV, MS, 4mA
|
||||
data[3] = 0x6f; // CLK2: INT, PLLB, nonINV, MS, 8mA
|
||||
i2c_write_blocking(i2c0, I2C_VFO, data, 4, false);
|
||||
|
||||
// Disable spread spectrum (startup state is undefined)
|
||||
data[0] = SI_SS_EN;
|
||||
data[1] = 0x00;
|
||||
i2c_write_blocking(i2c0, I2C_VFO, data, 2, false);
|
||||
|
||||
// Reset both PLL
|
||||
data[0] = SI_PLL_RESET;
|
||||
data[1] = 0xa0;
|
||||
i2c_write_blocking(i2c0, I2C_VFO, data, 2, false);
|
||||
// Initialize VFO values
|
||||
vfo[0].freq = 7074000;
|
||||
vfo[0].flag = 0;
|
||||
vfo[0].phase = PH090;
|
||||
vfo[0].ri = 1;
|
||||
vfo[0].msi = 106;
|
||||
vfo[0].msn = ((double)vfo[0].freq*vfo[0].msi)/(double)SI_XTAL_FREQ;
|
||||
|
||||
vfo[1].freq = 10000000;
|
||||
vfo[1].flag = 0;
|
||||
vfo[1].phase = PH000;
|
||||
vfo[1].ri = 1;
|
||||
vfo[1].msi = 76;
|
||||
vfo[1].msn = ((double)vfo[1].freq*vfo[1].msi)/(double)SI_XTAL_FREQ;
|
||||
|
||||
// Commit settings
|
||||
si_setmsn(0);
|
||||
si_setmsi(0);
|
||||
si_setmsn(1);
|
||||
si_setmsi(1);
|
||||
|
||||
// Enable only VFO0 outputs
|
||||
data[0] = SI_CLK_OE;
|
||||
data[1] = ~SI_VFO0_DISABLE;
|
||||
i2c_write_blocking(i2c0, I2C_VFO, data, 2, false);
|
||||
// Enable only VFO 0 outputs
|
||||
si_enable(0, true);
|
||||
si_enable(1, false);
|
||||
}
|
||||
|
||||
|
|
|
|||
9
si5351.h
9
si5351.h
|
|
@ -10,13 +10,18 @@
|
|||
* VFO 0 is a quadrature clock on outputs 0 and 1,
|
||||
* VFO 1 is a regular clock on output 2.
|
||||
*
|
||||
* The quadrature clock allows to set shared frequency and phase offsets of 0, 90, 180 and 270 deg
|
||||
* The regular clock just allows to set frequency, phase is ignored
|
||||
* VFO 0 allows to set frequency and phase offsets of 0-90-180-270 deg (delay clk1 wrt clk0)
|
||||
* VFO 1 just allows to set frequency, phase is ignored
|
||||
*
|
||||
* Use the 'set' functions to change VFO settings.
|
||||
* Make regular calls to the 'evaluate' function to commit the changes (if any).
|
||||
* To get smooth tuning, a suggested interval is 0.1sec, e.g. from a timer loop
|
||||
*
|
||||
* See si5351.c for more information
|
||||
*
|
||||
*/
|
||||
|
||||
// Phase definitions for si_setphase()
|
||||
#define PH000 0
|
||||
#define PH090 1
|
||||
#define PH180 2
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue