kopia lustrzana https://github.com/ArjanteMarvelde/uSDR-pico
V3.03
Added automatic bandfilter switching Optimized si5351 driver a bitpull/13/head
ArjanteMarvelde
rodzic
de115a043c
commit
53e7c155f5
9
dsp.h
9
dsp.h
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@ -7,10 +7,15 @@
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* Author: Arjan te Marvelde
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*
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* See dsp.c for more information
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*
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* HERE THE SELECTION BETWEEN TIME OR FREQUENCY DOMAIN PROCESSING IS MADE
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* DO THIS BY SETTING THE #define DSP_FFT TO 0 OR TO 1 RESPECTIVELY
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*
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*/
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// 1 for FFT, 0 for time domain processing
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#define DSP_FFT 0
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#define DSP_FFT 1
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/*
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43
hmi.c
43
hmi.c
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@ -115,11 +115,12 @@ char hmi_o_vox [HMI_NVOX][8] = {"NoVOX","VOX-L","VOX-M","VOX-H"}; // Indexed b
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char hmi_o_bpf [HMI_NBPF][8] = {"<2.5","2-6","5-12","10-24","20-40"}; // Indexed by
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// Map option to setting
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int hmi_mode[4] = {MODE_USB, MODE_LSB, MODE_AM, MODE_CW};
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int hmi_agc[3] = {AGC_NONE, AGC_SLOW, AGC_FAST};
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int hmi_pre[5] = {REL_ATT_30, REL_ATT_20, REL_ATT_10, REL_ATT_00, REL_PRE_10};
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int hmi_vox[4] = {VOX_OFF, VOX_LOW, VOX_MEDIUM, VOX_HIGH};
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int hmi_bpf[5] = {REL_LPF2, REL_BPF6, REL_BPF12, REL_BPF24, REL_BPF40};
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int hmi_mode[HMI_NMODE] = {MODE_USB, MODE_LSB, MODE_AM, MODE_CW};
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int hmi_agc[HMI_NAGC] = {AGC_NONE, AGC_SLOW, AGC_FAST};
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int hmi_pre[HMI_NPRE] = {REL_ATT_30, REL_ATT_20, REL_ATT_10, REL_ATT_00, REL_PRE_10};
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int hmi_vox[HMI_NVOX] = {VOX_OFF, VOX_LOW, VOX_MEDIUM, VOX_HIGH};
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int hmi_bpf[HMI_NBPF] = {REL_LPF2, REL_BPF6, REL_BPF12, REL_BPF24, REL_BPF40};
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int hmi_state, hmi_option; // Current state and menu option selection
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int hmi_sub[HMI_NSTATES] = {4,0,0,3,0,2}; // Stored option selection per state
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@ -159,7 +160,7 @@ void hmi_handler(uint8_t event)
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switch (event)
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{
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case HMI_E_ENTER: // Commit current value
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SI_SETFREQ(0, HMI_MULFREQ*(hmi_freq-FC_OFFSET)); // Commit frequency
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si_setfreq(0, HMI_MULFREQ*(hmi_freq-FC_OFFSET)); // Commit frequency
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break;
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case HMI_E_ESCAPE: // Enter submenus
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hmi_sub[hmi_state] = hmi_option; // Store selection (i.e. digit)
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@ -291,8 +292,8 @@ void hmi_init(void)
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hmi_option = 4; // Active kHz digit
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hmi_freq = 7074000UL; // Initial frequency
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SI_SETFREQ(0, HMI_MULFREQ*(hmi_freq-FC_OFFSET)); // Set freq to 7074 kHz (depends on mixer type)
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SI_SETPHASE(0, 1); // Set phase to 90deg (depends on mixer type)
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si_setfreq(0, HMI_MULFREQ*(hmi_freq-FC_OFFSET)); // Set freq to 7074 kHz (depends on mixer type)
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si_setphase(0, 1); // Set phase to 90deg (depends on mixer type)
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ptt_state = PTT_DEBOUNCE;
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ptt_active = false;
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@ -311,6 +312,7 @@ void hmi_init(void)
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*/
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void hmi_evaluate(void)
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{
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int band;
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char s[32];
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// Print top line of display
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@ -373,11 +375,28 @@ void hmi_evaluate(void)
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if (ptt_state == 0) // Set PTT when debounced level low
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ptt_active = true;
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/* Set parameters corresponding to latest entered option value */
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SI_SETFREQ(0, HMI_MULFREQ*(hmi_freq-FC_OFFSET)); // Always set frequency
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if (hmi_update) // Others only when indicated
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{
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// Frequency might have been changed in hmi_handler, so set anyway
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si_setfreq(0, HMI_MULFREQ*(hmi_freq-FC_OFFSET));
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// Check bandfilter setting (thanks Alex)
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if (hmi_freq < 2500000UL) band = REL_LPF2;
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else if (hmi_freq < 6000000UL) band = REL_BPF6;
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else if (hmi_freq < 12000000UL) band = REL_BPF12;
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else if (hmi_freq < 24000000UL) band = REL_BPF24;
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else band = REL_BPF40;
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if (band != hmi_bpf[hmi_sub[HMI_S_BPF]]) // Force update when changed
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{
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hmi_bpf[hmi_sub[HMI_S_BPF]] = band;
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hmi_update = true;
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}
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// Update peripherals according to menu setting
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// For frequency si5351 is set directly, HMI top line follows
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if (hmi_update)
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{
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dsp_setmode(hmi_sub[HMI_S_MODE]);
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dsp_setvox(hmi_sub[HMI_S_VOX]);
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dsp_setagc(hmi_sub[HMI_S_AGC]);
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19
relay.c
19
relay.c
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@ -6,15 +6,18 @@
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*
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* Two PCF8574 expanders are on the I2C bus, one on the RX and one on the BPF board.
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* The RX (0x42) bit assignments:
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* 0: Enable -20dB attenuator
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* 1: Enable -10dB attenuator
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* 2: Enable +10dB pre-amplifier
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* 0x03: Enable -20dB and -10dB attenuators
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* 0x01: Enable -20dB attenuator
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* 0x02: Enable -10dB attenuator
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* 0x04: Enable +10dB pre-amplifier
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* 0x00: No attenuator or pre-amp
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*
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* The BPF (0x40) bit assignments:
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* 0: Enable LPF 2.5 MHz
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* 1: Enable BPF 2.0 - 6.0 MHz
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* 2: Enable BPF 5.0 -12.0 MHz
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* 3: Enable BPF 10.0 -24.0 MHz
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* 4: Enable BPF 20.0 -40.0 MHz
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* 0x01: Enable LPF 2.5 MHz
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* 0x02: Enable BPF 2.0 - 6.0 MHz
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* 0x04: Enable BPF 5.0 -12.0 MHz
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* 0x08: Enable BPF 10.0 -24.0 MHz
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* 0x10: Enable BPF 20.0 -40.0 MHz
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*
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*/
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#include <stdio.h>
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160
si5351.c
160
si5351.c
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@ -9,13 +9,13 @@
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Si5351 principle of operation:
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==============================
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Crystal frequency Fxtal (usually 25MHz) is multiplied in a PLL by MSN to obtain Fvco.
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PLL A and B have independent MSN values, the Fout channel i can be derived from either.
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Fvco is between 600MHz and 900MHz, but the spec in reality is more relaxed.
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Fvco is divided by MSi and Ri to obtain the output frequency Fout.
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MSi and Ri are selected to be in the ballpark of desired frequency range.
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MSN is then used for tuning.
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Only certain values of MSi and Ri are allowed when quadrature output is needed.
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Crystal frequency <Fxtal> (usually 25MHz) is multiplied in a PLL by <MSN> to obtain <Fvco>.
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PLL A and B have independent MSN values, the <Fout> on channel <i> can be derived from either.
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<Fvco> must be between 600MHz and 900MHz, but the spec is more relaxed in reality.
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<Fvco> is divided by <MSi> and <Ri> to obtain the output frequency <Fout>.
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<MSi> and <Ri> are selected to be in the ballpark of desired frequency range.
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<MSN> is then used for tuning <Fout>.
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Only certain values of <MSi> and <Ri> are allowed when quadrature output is required.
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+-------+ +-------+ +------+
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- Fxtal --> | * MSN | -- Fvco --> | / MSi | --> | / Ri | -- Fout -->
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@ -27,28 +27,24 @@ Details:
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MSN determines: Fvco = Fxtal * (MSN) , where MSN = a + b/c
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MSi and Ri determine: Fout = Fvco / (Ri*MSi) , where MSi = a + b/c (different a, b and c)
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---Derivation of register values, for MSN and MSi---
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---Derivation of the register values, that determine MSN and MSi---
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P1 = 128*a + Floor(128*b/c) - 512
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P2 = 128*b - c*Floor(128*b/c) (P2 = 0 for MSi integer mode, or calculated for MSN tuning)
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P3 = c (P3 = 1 for MSi integer mode, or P3 = 1000000 for MSN tuning)
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This VFO implementation assumes PLLA is used for clk0 and clk1, PLLB is used for clk2
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This VFO implementation assumes PLLA is used for VFO0 (clk0 and clk1), and PLLB is used for VFO1 (clk2)
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Algorithm to get from frequency to synthesizer settings:
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(this assumes that the current settings are consistent, i.e. must be initialized at startup)
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| calculate new MSN from the desired Fout, based on current Ri and MSi
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The algorithm to get from required Fout to synthesizer settings:
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| calculate new <MSN> from the desired <Fout>, based on the current <Ri> and <MSi>
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| if MSN is still inside [600/Fxtal, 900/Fxtal]
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| then
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| just write the MSN parameter registers
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| just update the MSN related registers
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| else
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| re-calculate MSi, Ri and MSN from desired Fout
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| write the MSi and Ri parameter registers, including phase offset (MSi equals phase offset for 90 deg, use INV to shift 180deg more)
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| write the MSN parameter registers
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| re-calculate <MSi>, <Ri> and <MSN> from desired <Fout>
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| write the <MSi> and <Ri> parameter registers, including phase offset (MSi equals phase offset for 90 deg, use INV to shift 180deg more)
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| write the <MSN> parameter registers
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| reset PLL
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Ri=128 for Fout <1 MHz
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Ri= 32 for Fout 1-6 MHz
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Ri= 1 for Fout >6 MHz
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(this all assumes that the current settings are consistent, i.e. must be initialized at startup)
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Some boundary values:
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Ri MSi Lo MHz Hi MHz
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@ -70,7 +66,10 @@ Quadrature Phase offsets (i.e. delay):
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- Offset for MS0 (reg 165) must be 0 (cosine),
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- Offset for MS1 (reg 166) must be equal to divider MS1 for 90 deg (sine),
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- Set INV bit (reg 17) to add 180 deg.
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NOTE: Phase offsets only work when Ri = 1, this means minimum Fout is 4.762MHz at Fvco = 600MHz. Additional flip/flop dividers are needed to get 80m band frequencies, or Fvco must be tuned below spec.
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NOTE: Phase offsets only work when Ri = 1,
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This implies that minimum Fout is 4.762MHz at Fvco = 600MHz.
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Additional flip/flop dividers are needed to get down to 80m band frequencies, or Fvco must be tuned below spec.
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Control Si5351 (see AN619):
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@ -159,10 +158,12 @@ Control Si5351 (see AN619):
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#define SI_PLL_RESET 177
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#define SI_XTAL_LOAD 183
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// CLK_OE register 3 values
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// CLK_OE register 3 masks
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#define SI_CLK0_ENABLE 0b00000001 // Enable clock 0 output
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#define SI_CLK1_ENABLE 0b00000010 // Enable clock 1 output
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#define SI_CLK2_ENABLE 0b00000100 // Enable clock 2 output
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#define SI_VFO0_DISABLE 0b00000011 // Set bits to disable
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#define SI_VFO1_DISABLE 0b00000100 // Set bits to disable
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// CLKi_CTL register 16, 17, 18 values
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// Normally 0x4f for clk 0 and 1, 0x6f for clk 2
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@ -184,8 +185,59 @@ Control Si5351 (see AN619):
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#define SI_PLL_C 1000000UL // Parameter c for PLL-A and -B setting
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typedef struct
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{
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uint32_t freq; // type can hold up to 4GHz
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uint8_t flag; // flag != 0 when update needed
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uint8_t phase; // in quarter waves (0, 1, 2, 3)
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uint8_t ri; // Ri (1 .. 128)
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uint8_t msi; // MSi parameter a (4, 6, 8 .. 126)
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double msn; // MSN (24.0 .. 35.9999)
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} vfo_t;
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vfo_t vfo[2]; // 0: clk0 / clk1 1: clk2
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vfo_t vfo[2]; // 0: clk0 & clk1 1: clk2
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void si_setfreq(int i, uint32_t f)
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{
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if ((i<0)||(i>1)) return; // Check VFO range
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if (f>150000000) return; // Check frequency range
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if (vfo[i].freq == f) return; // Anything to set at all?
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vfo[i].freq = f; // Entry checks pass, so do the actual setting
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vfo[i].flag = 1;
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}
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void si_setphase(int i, uint8_t p)
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{
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if (i!=0) return; // Check VFO range
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if (p>3) return; // Check phase range
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if (vfo[i].phase == p) return; // Anything to set at all?
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vfo[i].phase = p; // Entry checks pass, so do the actual setting
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vfo[i].flag = 1;
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}
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void si_enable(int i, bool en)
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{
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uint8_t data[2];
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if ((i<0)||(i>1)) return; // Check VFO range
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data[0] = SI_CLK_OE; // Read OE register
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i2c_write_blocking(i2c0, I2C_VFO, &data[0], 1, true);
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i2c_read_blocking(i2c0, I2C_VFO, &data[1], 1, false);
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data[0] = SI_CLK_OE;
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if (i==0)
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{
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data[1] = en ? data[1]&~SI_VFO0_DISABLE : data[1]|SI_VFO0_DISABLE;
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}
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else
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{
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data[1] = en ? data[1]&~SI_VFO1_DISABLE : data[1]|SI_VFO1_DISABLE;
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}
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i2c_write_blocking(i2c0, I2C_VFO, &data[0], 2, false);
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}
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/*
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* read contents of SI5351 registers, from reg to reg+len-1, output in data array
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@ -207,23 +259,26 @@ int si_getreg(uint8_t *data, uint8_t reg, uint8_t len)
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* Optimize for speed, this may be called with short intervals
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* See also SiLabs AN619 section 3.2
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*/
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void si_setmsn(uint8_t i)
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void si_setmsn(int i)
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{
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uint8_t data[16]; // I2C trx buffer
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uint32_t P1, P2; // MSN parameters
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uint32_t A;
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uint32_t B;
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i=(i>0?1:0);
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if ((i<0)||(i>1)) return; // Check VFO range
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A = (uint32_t)(floor(vfo[i].msn)); // A is integer part of MSN
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B = (uint32_t)((vfo[i].msn - (float)A) * SI_PLL_C); // B is C * fraction part of MSN (C is a constant)
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P2 = (uint32_t)(floor((float)(128 * B) / (float)SI_PLL_C));
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B = (uint32_t)((vfo[i].msn - (double)A) * SI_PLL_C); // B is C * fraction part of MSN (C is a constant)
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P2 = (uint32_t)(floor((double)(128 * B) / (double)SI_PLL_C));
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P1 = (uint32_t)(128 * A + P2 - 512);
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P2 = (uint32_t)(128 * B - SI_PLL_C * P2);
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// transfer registers
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data[0] = (i==0?SI_SYNTH_PLLA:SI_SYNTH_PLLB);
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// transfer PLL A or PLL B registers
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if (i==0)
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data[0] = SI_SYNTH_PLLA;
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else
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data[0] = SI_SYNTH_PLLB;
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data[1] = (SI_PLL_C & 0x0000FF00) >> 8;
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data[2] = (SI_PLL_C & 0x000000FF);
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data[3] = (P1 & 0x00030000) >> 16;
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@ -252,7 +307,10 @@ void si_setmsi(uint8_t i)
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R = vfo[i].ri;
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R = (R&0xf0) ? ((R&0xc0)?((R&0x80)?7:6):(R&0x20)?5:4) : ((R&0x0c)?((R&0x08)?3:2):(R&0x02)?1:0); // quick log2(r)
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data[0] = (i==0?SI_SYNTH_MS0:SI_SYNTH_MS2);
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if (i==0)
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data[0] = SI_SYNTH_MS0;
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else
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data[0] = SI_SYNTH_MS2;
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data[1] = 0x00;
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data[2] = 0x01;
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data[3] = ((P1 & 0x00030000) >> 16) | (R << 4 );
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@ -272,18 +330,18 @@ void si_setmsi(uint8_t i)
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if (vfo[0].phase&1) // Phase is either 90 or 270 deg?
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{
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data[0] = SI_CLK1_PHOFF;
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data[1] = vfo[0].msi;
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data[1] = vfo[0].msi; // offset == MSi for 90deg
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i2c_write_blocking(i2c0, I2C_VFO, data, 2, false);
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}
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else // Phase is 0 or 180 deg
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{
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data[0] = SI_CLK1_PHOFF;
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data[1] = 0;
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data[1] = 0; // offset == 0 for 0deg
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i2c_write_blocking(i2c0, I2C_VFO, data, 2, false);
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}
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if (vfo[0].phase&2) // Phase is 180 or 270 deg?
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{
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data[0] = SI_CLK1_CTL;
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data[0] = SI_CLK1_CTL; // Then set the invert flag
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data[1] = 0x5d; // CLK1: INT, PLLA, INV, MS, 8mA
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i2c_write_blocking(i2c0, I2C_VFO, data, 2, false);
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}
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@ -304,13 +362,13 @@ void si_setmsi(uint8_t i)
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*/
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void si_evaluate(void)
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{
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float msn;
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double msn;
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if (vfo[0].flag)
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{
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msn = (float)(vfo[0].msi); // Re-calculate MSN
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msn = msn * (float)(vfo[0].ri);
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msn = msn * (float)(vfo[0].freq) / SI_XTAL_FREQ;
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msn = (double)(vfo[0].msi); // Re-calculate MSN
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msn = msn * (double)(vfo[0].ri);
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msn = msn * (double)(vfo[0].freq) / SI_XTAL_FREQ;
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if ((msn>=SI_MSN_LO)&&(msn<SI_MSN_HI))
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{
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vfo[0].msn = msn;
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@ -318,15 +376,25 @@ void si_evaluate(void)
|
|||
}
|
||||
else
|
||||
{
|
||||
vfo[0].ri = (vfo[0].freq<1000000)?128:((vfo[0].freq<3000000)?32:1); // Pre-scale Ri, stretch down Ri=1 range
|
||||
if ((vfo[0].freq >= 3000000)&&(vfo[0].freq < 6000000)) // Low end of Ri=1 range
|
||||
vfo[0].msi = (uint8_t)126; // Maximum MSi on Fvco=(4x126)MHz
|
||||
// Pre-scale Ri, stretch down Ri=1 range
|
||||
if (vfo[0].freq<1000000)
|
||||
vfo[0].ri = 128;
|
||||
else if (vfo[0].freq<3000000)
|
||||
vfo[0].ri = 32;
|
||||
else
|
||||
vfo[0].msi = (uint8_t)(750000000UL / (vfo[0].freq * vfo[0].ri)) & 0xfe; // Calculate MSi on Fvco=750MHz
|
||||
msn = (float)(vfo[0].msi); // Re-calculate MSN
|
||||
msn = msn * (float)(vfo[0].ri);
|
||||
msn = msn * (float)(vfo[0].freq) / SI_XTAL_FREQ;
|
||||
vfo[0].ri = 1;
|
||||
|
||||
// Set MSi
|
||||
if ((vfo[0].freq >= 3000000)&&(vfo[0].freq < 6000000)) // Handle Low end of Ri=1 range
|
||||
vfo[0].msi = (uint8_t)126; // Maximum MSi on Fvco=(4x126)MHz
|
||||
else // Or calculate MSi on Fvco=750MHz
|
||||
vfo[0].msi = (uint8_t)(750000000UL / (vfo[0].freq * vfo[0].ri)) & 0x000000fe;
|
||||
|
||||
msn = (double)(vfo[0].msi); // Re-calculate MSN
|
||||
msn = msn * (double)(vfo[0].ri);
|
||||
msn = msn * (double)(vfo[0].freq) / SI_XTAL_FREQ;
|
||||
vfo[0].msn = msn;
|
||||
|
||||
si_setmsn(0);
|
||||
si_setmsi(0);
|
||||
}
|
||||
|
|
@ -424,9 +492,9 @@ void si_init(void)
|
|||
data[1] = 0xa0;
|
||||
i2c_write_blocking(i2c0, I2C_VFO, data, 2, false);
|
||||
|
||||
// Enable all outputs
|
||||
// Enable only VFO0 outputs
|
||||
data[0] = SI_CLK_OE;
|
||||
data[1] = 0x00;
|
||||
data[1] = ~SI_VFO0_DISABLE;
|
||||
i2c_write_blocking(i2c0, I2C_VFO, data, 2, false);
|
||||
}
|
||||
|
||||
|
|
|
|||
31
si5351.h
31
si5351.h
|
|
@ -6,31 +6,28 @@
|
|||
* Created: March 2021
|
||||
* Author: Arjan
|
||||
*
|
||||
* Driver for Si5351A chip.
|
||||
* VFO 0 is a quadrature clock on outputs 0 and 1,
|
||||
* VFO 1 is a regular clock on output 2.
|
||||
*
|
||||
* The quadrature clock allows to set shared frequency and phase offsets of 0, 90, 180 and 270 deg
|
||||
* The regular clock just allows to set frequency, phase is ignored
|
||||
*
|
||||
* See si5351.c for more information
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t freq; // type can hold up to 4GHz
|
||||
uint8_t flag; // flag != 0 when update needed
|
||||
uint8_t phase; // in quarter waves (0, 1, 2, 3)
|
||||
uint8_t ri; // Ri (1 .. 128)
|
||||
uint8_t msi; // MSi parameter a (4, 6, 8 .. 126)
|
||||
float msn; // MSN (24.0 .. 35.9999)
|
||||
} vfo_t;
|
||||
extern vfo_t vfo[2]; // Table contains all control data for three clk outputs, but 0 and 1 are coupled in vfo[0]
|
||||
#define PH000 0
|
||||
#define PH090 1
|
||||
#define PH180 2
|
||||
#define PH270 3
|
||||
|
||||
int si_getreg(uint8_t *data, uint8_t reg, uint8_t len);
|
||||
void si_init(void);
|
||||
void si_evaluate(void);
|
||||
void si_setfreq(int i, uint32_t f);
|
||||
void si_setphase(int i, uint8_t p);
|
||||
void si_enable(int i, bool en);
|
||||
|
||||
#define SI_GETFREQ(i) ((((i)>=0)&&((i)<2))?vfo[(i)].freq:0)
|
||||
#define SI_INCFREQ(i, d) if ((((i)>=0)&&((i)<2))&&((vfo[(i)].freq)<(150000000-(d)))) { vfo[(i)].freq += (d); vfo[(i)].flag = 1;}
|
||||
#define SI_DECFREQ(i, d) if ((((i)>=0)&&((i)<2))&&((vfo[(i)].freq)>(d))) { (vfo[(i)].freq) -= (d); vfo[(i)].flag = 1;}
|
||||
#define SI_SETFREQ(i, f) if ((((i)>=0)&&((i)<2))&&((f)<150000000)) { vfo[(i)].freq = (f); vfo[(i)].flag = 1;}
|
||||
#define SI_SETPHASE(i, p) if (((i)>=0)&&((i)<2)) {vfo[(i)].phase = ((uint8_t)p)&3; vfo[(i)].flag = 1;}
|
||||
|
||||
#endif /* _SI5351_H */
|
||||
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Reference in New Issue