Xael South
|
ae5d8f818f
|
simultaneously rx T1, C1 ans S1, but the latter is untested
|
2021-02-05 12:56:22 +00:00 |
Xael South
|
8ac790dc16
|
C1 receiver with better filtering
|
2021-02-04 14:20:04 +00:00 |
Xael South
|
8bec4a2b08
|
C1 mode improvements; S1 mode implemented
|
2021-02-02 17:29:08 +00:00 |
Xael South
|
cec199312e
|
clock recovering for time2 method only if latter selected
|
2021-02-02 08:28:24 +00:00 |
Xael South
|
6d92d1b3f1
|
rx_sdr
|
2021-01-28 14:26:50 +00:00 |
Xael South
|
4098aa84bb
|
configurable decimation rate
|
2021-01-28 13:32:59 +00:00 |
Xael South
|
0dc6a61c92
|
Get rid of some compiler warnings.
|
2021-01-26 12:44:57 +01:00 |
Xael South
|
355ba64a57
|
- run length algorithm for picking datagrams out of the bit stream implemented.
- L(ength) field fixed for C1 Mode B datagrams.
- Allow to redefine CFLAGS and OUTPUT directory.
|
2021-01-26 11:50:05 +01:00 |
Xael South
|
2453cd8c0f
|
#define SSE4.2
|
2018-02-05 19:30:44 +01:00 |
xaelsouth
|
ebe0a8bef6
|
initial commit
|
2017-04-04 20:29:40 +00:00 |