two variants; debugger now runs on Core1

DAP_config.h

@@ -225,7 +225,7 @@ __STATIC_INLINE void PORT_SWD_SETUP (void) {
 
   /* enable the peripheral and enable local control of core1's SWD interface */
   resets_hw->reset &= ~RESETS_RESET_SYSCFG_BITS;
-  syscfg_hw->dbgforce = SYSCFG_DBGFORCE_PROC1_ATTACH_BITS;
+  syscfg_hw->dbgforce = SYSCFG_DBGFORCE_PROC0_ATTACH_BITS;
 
 #if 1
   /* this #if block is a temporary measure to perform target selection even if the host IDE doesn't know how */
@@ -238,12 +238,12 @@ __STATIC_INLINE void PORT_SWD_SETUP (void) {
   SWJ_Sequence(8*sizeof(sequence_alert), sequence_alert);
 
   /* it is possible to do this with SWJ_Sequence on the rp2040 since data input and output are distinct */
-  static const uint8_t write_targetsel[] = { 0x99, 0xff, 0x24, 0x05, 0x20, 0x22, 0x00, };
+  static const uint8_t write_targetsel[] = { 0x99, 0xff, 0x24, 0x05, 0x20, 0x00, 0x00, };
   SWJ_Sequence(8*sizeof(write_targetsel), write_targetsel);
 #endif
 
   /* set to default high level */
-  syscfg_hw->dbgforce |= SYSCFG_DBGFORCE_PROC1_SWCLK_BITS | SYSCFG_DBGFORCE_PROC1_SWDI_BITS;
+  syscfg_hw->dbgforce |= SYSCFG_DBGFORCE_PROC0_SWCLK_BITS | SYSCFG_DBGFORCE_PROC0_SWDI_BITS;
 }
 
 /** Disable JTAG/SWD I/O Pins.
@@ -268,14 +268,14 @@ __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN  (void) {
 Set the SWCLK/TCK DAP hardware I/O pin to high level.
 */
 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_SET (void) {
-  syscfg_hw->dbgforce |= SYSCFG_DBGFORCE_PROC1_SWCLK_BITS;
+  syscfg_hw->dbgforce |= SYSCFG_DBGFORCE_PROC0_SWCLK_BITS;
 }
 
 /** SWCLK/TCK I/O pin: Set Output to Low.
 Set the SWCLK/TCK DAP hardware I/O pin to low level.
 */
 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_CLR (void) {
-  syscfg_hw->dbgforce &= ~SYSCFG_DBGFORCE_PROC1_SWCLK_BITS;
+  syscfg_hw->dbgforce &= ~SYSCFG_DBGFORCE_PROC0_SWCLK_BITS;
 }
 
 
@@ -294,21 +294,21 @@ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN  (void) {
 Set the SWDIO/TMS DAP hardware I/O pin to high level.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_SET (void) {
-  syscfg_hw->dbgforce |= SYSCFG_DBGFORCE_PROC1_SWDI_BITS;
+  syscfg_hw->dbgforce |= SYSCFG_DBGFORCE_PROC0_SWDI_BITS;
 }
 
 /** SWDIO/TMS I/O pin: Set Output to Low.
 Set the SWDIO/TMS DAP hardware I/O pin to low level.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_CLR (void) {
-  syscfg_hw->dbgforce &= ~SYSCFG_DBGFORCE_PROC1_SWDI_BITS;
+  syscfg_hw->dbgforce &= ~SYSCFG_DBGFORCE_PROC0_SWDI_BITS;
 }
 
 /** SWDIO I/O pin: Get Input (used in SWD mode only).
 \return Current status of the SWDIO DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN      (void) {
-  return (syscfg_hw->dbgforce & SYSCFG_DBGFORCE_PROC1_SWDO_BITS) ? 1U : 0U;
+  return (syscfg_hw->dbgforce & SYSCFG_DBGFORCE_PROC0_SWDO_BITS) ? 1U : 0U;
 }
 
 /** SWDIO I/O pin: Set Output (used in SWD mode only).
@@ -316,9 +316,9 @@ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN      (void) {
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT     (uint32_t bit) {
   if (bit & 1)
-    syscfg_hw->dbgforce |= SYSCFG_DBGFORCE_PROC1_SWDI_BITS;
+    syscfg_hw->dbgforce |= SYSCFG_DBGFORCE_PROC0_SWDI_BITS;
   else
-    syscfg_hw->dbgforce &= ~SYSCFG_DBGFORCE_PROC1_SWDI_BITS;
+    syscfg_hw->dbgforce &= ~SYSCFG_DBGFORCE_PROC0_SWDI_BITS;
 }
 
 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
@@ -334,7 +334,7 @@ Configure the SWDIO DAP hardware I/O pin to input mode. This function is
 called prior \ref PIN_SWDIO_IN function calls.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_DISABLE (void) {
-  syscfg_hw->dbgforce |= SYSCFG_DBGFORCE_PROC1_SWDI_BITS;
+  syscfg_hw->dbgforce |= SYSCFG_DBGFORCE_PROC0_SWDI_BITS;
 }
 
 

README.md

@@ -6,13 +6,18 @@ pico-debug runs on one core in a RP2040 and provides a USB CMSIS-DAP interface t
 
 Boot the RP2040 with the BOOTSEL button pressed, copy over pico-debug.uf2, and it immediately reboots as a CMSIS-DAP adapter.  pico-debug loads as a RAM only .uf2 image, meaning that it is never written to flash and doesn't replace existing user code.
 
-*All* 264kBytes of SRAM on the RP2040 is available for running user code; pico-debug shoehorns itself entirely into the 16kBytes of XIP_SRAM (aka flash cache).
+To cater to different user situations, there are two versions of pico-debug: **MAXRAM** and **GIMMECACHE**
 
-If viewing this on github, a pre-built binary is available for download on the right under "Releases".
+With **pico-debug-maxram**, *all* 264kBytes of SRAM on the RP2040 is available for running user code; pico-debug shoehorns itself entirely into the 16kBytes of XIP_SRAM (aka flash cache).
+
+With **pico-debug-gimmecache**, 248kBytes (94% of total) of SRAM is available for running user code; pico-debug gives plenty of elbow room by occupying only 6% near the very top of SRAM, and unlike MAXRAM, leaves the flash cache operational.
+
+If viewing this on github, pre-built binaries are available for download on the right under "Releases".
 
 ## Caveats whilst using pico-debug
 
-- the flash cache cannot be used by the user code, as pico-debug is using this memory
+- MAXRAM only: the flash cache cannot be used by the user code, as pico-debug is using this memory
+- GIMMECACHE only: SRAM 0x2003C000 to 0x2003FFFF must not be used by user code
 - user code cannot reconfigure the PLL and clocks, as the USB peripheral needs this
 - the USB peripheral is used to provide the debugger, so the user code cannot use it as well
 

pico-debug.hzp

@@ -3,18 +3,20 @@
   <project Name="pico-debug">
     <configuration
       Name="Common"
+      batch_build_configurations="THUMB Release - SRAM;THUMB Release - XIP"
       build_intermediate_directory="./_build/$(ProjectName) $(Configuration)"
       build_output_directory="./_build/$(ProjectName) $(Configuration)"
       c_preprocessor_definitions=""
-      package_dependencies="CMSIS;Cortex_M_Generic"
       c_user_include_directories=".;./rp2040/;$(PackagesDir)/CMSIS_5/CMSIS/Core/Include;./CMSIS_5/CMSIS/DAP/Firmware/Include"
-      gcc_entry_point="boot_entry" />
+      gcc_entry_point="boot_entry"
+      package_dependencies="CMSIS;Cortex_M_Generic" />
     <folder Name="Source Files">
       <configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc" />
       <file file_name="./main.c" />
       <file file_name="./usb_descriptors.c" />
       <file file_name="myboard.c" />
       <file file_name="clock_setup.c" />
+      <file file_name="spawn.c" />
     </folder>
     <folder Name="hal">
       <file file_name="$(TOP)/hw/bsp/board.c" />
@@ -44,9 +46,7 @@
     </folder>
     <folder Name="System Files">
       <file file_name="picodebug_Startup.s" />
-      <file file_name="picodebug_placement.xml" />
     </folder>
-    <configuration Name="Release" link_time_optimization="Yes" />
   </project>
   <configuration
     Name="Common"
@@ -72,7 +72,6 @@
     property_groups_file_path="$(TargetsDir)/Cortex_M/propertyGroups.xml"
     target_reset_script="Reset()"
     target_script_file="$(TargetsDir)/Cortex_M/Cortex_M_Target.js" />
-  <configuration Name="THUMB Debug" inherited_configurations="THUMB;Debug" />
   <configuration
     Name="THUMB"
     Platform="ARM"
@@ -81,20 +80,26 @@
     c_preprocessor_definitions="__THUMB"
     hidden="Yes" />
   <configuration
-    Name="Debug"
+    Name="THUMB Release - XIP"
-    c_preprocessor_definitions="DEBUG"
+    inherited_configurations="THUMB;Release;XIP" />
-    gcc_debugging_level="Level 3"
-    gcc_omit_frame_pointer="Yes"
-    gcc_optimization_level="None"
-    hidden="Yes" />
   <configuration
-    Name="THUMB Release"
+    Name="THUMB Release - SRAM"
-    inherited_configurations="THUMB;Release" />
+    inherited_configurations="THUMB;Release;SRAM" />
   <configuration
     Name="Release"
     c_preprocessor_definitions="NDEBUG"
     gcc_debugging_level="Level 3"
     gcc_omit_frame_pointer="Yes"
     gcc_optimization_level="Level 1"
-    hidden="Yes" />
+    hidden="Yes"
+    link_time_optimization="Yes" />
+  <configuration
+    Name="XIP"
+    hidden="Yes"
+    linker_section_placement_file="picodebug_xip_placement.xml" />
+  <configuration
+    Name="SRAM"
+    c_preprocessor_definitions="STAY_IN_SRAM"
+    hidden="Yes"
+    linker_section_placement_file="picodebug_sram_placement.xml" />
 </solution>

picodebug_MemoryMap.xml

@@ -1,5 +1,5 @@
 <!DOCTYPE Board_Memory_Definition_File>
 <Root name="Cortex-M0">
-  <MemorySegment start="0x20030000" size="0x4100" access="Read/Write" name="SRAM" />
+  <MemorySegment start="0x2003BF00" size="0x4100" access="Read/Write" name="SRAM" />
   <MemorySegment start="0x15000000" size="0x4000" access="Read/Write" name="XIP_SRAM" />
 </Root>

picodebug_Startup.s

@@ -42,6 +42,7 @@
   .syntax unified
   .global boot_entry
   .extern main
+  .extern multicore_launch_core1_raw
   .global exit
   .weak exit
 
@@ -49,6 +50,7 @@
   .thumb_func
 
 boot_entry:
+#ifndef STAY_IN_SRAM
   /* disable flash cache (allowing XIP_SRAM access) */
   ldr r0, =0x14000000
   ldr r1, =0
@@ -70,15 +72,17 @@ copy_loop:
   subs r2, r2, #1
   bne copy_loop
 copy_finished:
+#endif
 
-  ldr r1, =__vectors_start__ /* origin of where vector table now resides */
+  ldr r2, =__vectors_start__ /* origin of where vector table now resides */
-  ldr r0, =0xE000ED08 /* VTOR register */
+  ldr r1, [r2] /* load stack pointer from user app */
-  str r1, [r0] /* point VTOR to user app */
+  ldr r0, [r2, #4] /* load reset address from user app */
-  ldr r0, [r1] /* load stack pointer from user app */
+  ldr r3, =multicore_launch_core1_raw
-  msr msp, r0
+  blx r3
-  msr psp, r0
+
-  ldr r0, [r1, #4] /* load reset address from user app */
+sleep:
-  mov pc, r0
+  wfi
+  b sleep
 
   .section .vectors, "ax"
   .code 16  

picodebug_sram_placement.xml

@@ -0,0 +1,15 @@
+<!DOCTYPE Linker_Placement_File>
+<Root name="picodebug Section Placement">
+  <MemorySegment name="SRAM">
+    <ProgramSection alignment="4" load="Yes" name=".boot" />
+    <ProgramSection alignment="4" load="Yes" name=".bootc" />
+    <ProgramSection alignment="0x100" load="Yes" name=".vectors" />
+    <ProgramSection alignment="4" load="Yes" name=".text" />
+    <ProgramSection alignment="4" load="Yes" name=".data" />
+    <ProgramSection alignment="4" load="Yes" name=".rodata" />
+    <ProgramSection alignment="4" load="No" name=".bss" />
+    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" name=".stack" />
+  </MemorySegment>
+  <MemorySegment name="XIP_SRAM">
+  </MemorySegment>
+</Root>

picodebug_xip_placement.xml

@@ -2,12 +2,13 @@
 <Root name="picodebug Section Placement">
   <MemorySegment name="SRAM">
     <ProgramSection alignment="4" load="Yes" name=".boot" />
-    <ProgramSection alignment="0x100" load="Yes" runoffset="0x15000000-0x20030100" name=".vectors" />
+    <ProgramSection alignment="4" load="Yes" name=".bootc" />
-    <ProgramSection alignment="4" load="Yes" runoffset="0x15000000-0x20030100" name=".text" />
+    <ProgramSection alignment="0x100" load="Yes" runoffset="0x15000000-0x2003C000" name=".vectors" />
-    <ProgramSection alignment="4" load="Yes" runoffset="0x15000000-0x20030100" name=".data" />
+    <ProgramSection alignment="4" load="Yes" runoffset="0x15000000-0x2003C000" name=".text" />
-    <ProgramSection alignment="4" load="Yes" runoffset="0x15000000-0x20030100" name=".rodata" />
+    <ProgramSection alignment="4" load="Yes" runoffset="0x15000000-0x2003C000" name=".data" />
-    <ProgramSection alignment="4" load="No" runoffset="0x15000000-0x20030100" name=".bss" />
+    <ProgramSection alignment="4" load="Yes" runoffset="0x15000000-0x2003C000" name=".rodata" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" runoffset="0x15000000-0x20030100" name=".stack" />
+    <ProgramSection alignment="4" load="No" runoffset="0x15000000-0x2003C000" name=".bss" />
+    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" runoffset="0x15000000-0x2003C000" name=".stack" />
   </MemorySegment>
   <MemorySegment name="XIP_SRAM">
   </MemorySegment>

spawn.c

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <rp2040.h>
+
+static inline bool multicore_fifo_rvalid() {
+    return !!(sio_hw->fifo_st & SIO_FIFO_ST_VLD_BITS);
+}
+
+static inline void multicore_fifo_drain() {
+    while (multicore_fifo_rvalid())
+        (void) sio_hw->fifo_rd;
+}
+
+static inline bool multicore_fifo_wready() {
+    return !!(sio_hw->fifo_st & SIO_FIFO_ST_RDY_BITS);
+}
+
+static inline void multicore_fifo_push_blocking(uint32_t data) {
+    // We wait for the fifo to have some space
+    while (!multicore_fifo_wready())
+        tight_loop_contents();
+
+    sio_hw->fifo_wr = data;
+
+    // Fire off an event to the other core
+    __SEV();
+}
+
+static inline uint32_t multicore_fifo_pop_blocking(void) {
+    // If nothing there yet, we wait for an event first,
+    // to try and avoid too much busy waiting
+    while (!multicore_fifo_rvalid())
+        __WFE();
+
+    return sio_hw->fifo_rd;
+}
+
+__attribute__ (( section(".bootc") )) void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table) {
+    uint32_t cmd_sequence[] = {0, 0, 1, (uintptr_t) vector_table, (uintptr_t) sp, (uintptr_t) entry};
+
+    uint seq = 0;
+    do {
+        uint cmd = cmd_sequence[seq];
+        // we drain before sending a 0
+        if (!cmd) {
+            multicore_fifo_drain();
+            __SEV(); // core 1 may be waiting for fifo space
+        }
+        multicore_fifo_push_blocking(cmd);
+        uint32_t response = multicore_fifo_pop_blocking();
+        // move to next state on correct response otherwise start over
+        seq = cmd == response ? seq + 1 : 0;
+    } while (seq < (sizeof(cmd_sequence) / sizeof(*cmd_sequence)));
+}

usb_descriptors.c

@@ -23,7 +23,7 @@ tusb_desc_device_t const desc_device =
     /* using Dapper Miser CMSIS-DAP VID:PID */
     .idVendor           = 0x1209,
     .idProduct          = 0x2488,
-    .bcdDevice          = 0x1000,
+    .bcdDevice          = 0x1001,
 
     .iManufacturer      = 0,
     .iProduct           = STRID_PRODUCT,