kopia lustrzana https://github.com/micropython/micropython
245 wiersze
7.4 KiB
C
245 wiersze
7.4 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2013, 2014 Damien P. George
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* Copyright (c) 2021, 2022 Renesas Electronics Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h>
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#include "py/obj.h"
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#include "py/mphal.h"
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#include "ra_it.h"
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#include "pendsv.h"
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#include "irq.h"
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#include "powerctrl.h"
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#include "pybthread.h"
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#include "gccollect.h"
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#include "extint.h"
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#include "timer.h"
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#include "uart.h"
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#include "storage.h"
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extern void __fatal_error(const char *);
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/******************************************************************************/
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/* Cortex-M4 Processor Exceptions Handlers */
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/******************************************************************************/
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// Set the following to 1 to get some more information on the Hard Fault
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// More information about decoding the fault registers can be found here:
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// http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0646a/Cihdjcfc.html
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static char *fmt_hex(uint32_t val, char *buf) {
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const char *hexDig = "0123456789abcdef";
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buf[0] = hexDig[(val >> 28) & 0x0f];
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buf[1] = hexDig[(val >> 24) & 0x0f];
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buf[2] = hexDig[(val >> 20) & 0x0f];
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buf[3] = hexDig[(val >> 16) & 0x0f];
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buf[4] = hexDig[(val >> 12) & 0x0f];
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buf[5] = hexDig[(val >> 8) & 0x0f];
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buf[6] = hexDig[(val >> 4) & 0x0f];
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buf[7] = hexDig[(val >> 0) & 0x0f];
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buf[8] = '\0';
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return buf;
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}
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static void print_reg(const char *label, uint32_t val) {
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char hexStr[9];
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mp_hal_stdout_tx_str(label);
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mp_hal_stdout_tx_str(fmt_hex(val, hexStr));
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mp_hal_stdout_tx_str("\r\n");
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}
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static void print_hex_hex(const char *label, uint32_t val1, uint32_t val2) {
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char hex_str[9];
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mp_hal_stdout_tx_str(label);
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mp_hal_stdout_tx_str(fmt_hex(val1, hex_str));
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mp_hal_stdout_tx_str(" ");
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mp_hal_stdout_tx_str(fmt_hex(val2, hex_str));
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mp_hal_stdout_tx_str("\r\n");
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}
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// The ARMv7M Architecture manual (section B.1.5.6) says that upon entry
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// to an exception, that the registers will be in the following order on the
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// // stack: R0, R1, R2, R3, R12, LR, PC, XPSR
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typedef struct {
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uint32_t r0, r1, r2, r3, r12, lr, pc, xpsr;
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} ExceptionRegisters_t;
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int pyb_hard_fault_debug = 0;
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void HardFault_C_Handler(ExceptionRegisters_t *regs) {
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if (!pyb_hard_fault_debug) {
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powerctrl_mcu_reset();
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}
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#if MICROPY_HW_ENABLE_USB
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// We need to disable the USB so it doesn't try to write data out on
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// the VCP and then block indefinitely waiting for the buffer to drain.
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pyb_usb_flags = 0;
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#endif
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mp_hal_stdout_tx_str("HardFault\r\n");
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print_reg("R0 ", regs->r0);
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print_reg("R1 ", regs->r1);
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print_reg("R2 ", regs->r2);
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print_reg("R3 ", regs->r3);
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print_reg("R12 ", regs->r12);
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print_reg("SP ", (uint32_t)regs);
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print_reg("LR ", regs->lr);
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print_reg("PC ", regs->pc);
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print_reg("XPSR ", regs->xpsr);
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#if __CORTEX_M >= 3
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uint32_t cfsr = SCB->CFSR;
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print_reg("HFSR ", SCB->HFSR);
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print_reg("CFSR ", cfsr);
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if (cfsr & 0x80) {
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print_reg("MMFAR ", SCB->MMFAR);
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}
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if (cfsr & 0x8000) {
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print_reg("BFAR ", SCB->BFAR);
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}
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#endif
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if ((void *)&_ram_start <= (void *)regs && (void *)regs < (void *)&_ram_end) {
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mp_hal_stdout_tx_str("Stack:\r\n");
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uint32_t *stack_top = &_estack;
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if ((void *)regs < (void *)&_sstack) {
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// stack not in static stack area so limit the amount we print
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stack_top = (uint32_t *)regs + 32;
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}
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for (uint32_t *sp = (uint32_t *)regs; sp < stack_top; ++sp) {
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print_hex_hex(" ", (uint32_t)sp, *sp);
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}
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}
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/* Go to infinite loop when Hard Fault exception occurs */
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while (1) {
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__fatal_error("HardFault");
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}
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}
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// Naked functions have no compiler generated gunk, so are the best thing to
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// use for asm functions.
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__attribute__((naked))
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void HardFault_Handler(void) {
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// From the ARMv7M Architecture Reference Manual, section B.1.5.6
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// on entry to the Exception, the LR register contains, amongst other
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// things, the value of CONTROL.SPSEL. This can be found in bit 3.
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//
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// If CONTROL.SPSEL is 0, then the exception was stacked up using the
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// main stack pointer (aka MSP). If CONTROL.SPSEL is 1, then the exception
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// was stacked up using the process stack pointer (aka PSP).
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#if __CORTEX_M == 0
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__asm volatile (
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" mov r0, lr \n"
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" lsr r0, r0, #3 \n" // Shift Bit 3 into carry to see which stack pointer we should use.
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" mrs r0, msp \n" // Make R0 point to main stack pointer
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" bcc .use_msp \n" // Keep MSP in R0 if SPSEL (carry) is 0
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" mrs r0, psp \n" // Make R0 point to process stack pointer
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" .use_msp: \n"
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" b HardFault_C_Handler \n" // Off to C land
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);
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#else
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__asm volatile (
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" tst lr, #4 \n" // Test Bit 3 to see which stack pointer we should use.
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" ite eq \n" // Tell the assembler that the nest 2 instructions are if-then-else
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" mrseq r0, msp \n" // Make R0 point to main stack pointer
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" mrsne r0, psp \n" // Make R0 point to process stack pointer
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" b HardFault_C_Handler \n" // Off to C land
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);
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#endif
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}
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#if 0
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/**
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* @brief This function handles NMI exception.
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* @param None
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* @retval None
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*/
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void NMI_Handler(void) {
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}
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#endif
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/**
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* @brief This function handles Memory Manage exception.
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* @param None
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* @retval None
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*/
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void MemManage_Handler(void) {
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/* Go to infinite loop when Memory Manage exception occurs */
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while (1) {
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__fatal_error("MemManage");
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}
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}
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/**
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* @brief This function handles Bus Fault exception.
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* @param None
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* @retval None
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*/
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void BusFault_Handler(void) {
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/* Go to infinite loop when Bus Fault exception occurs */
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while (1) {
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__fatal_error("BusFault");
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}
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}
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/**
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* @brief This function handles Usage Fault exception.
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* @param None
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* @retval None
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*/
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void UsageFault_Handler(void) {
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/* Go to infinite loop when Usage Fault exception occurs */
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while (1) {
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__fatal_error("UsageFault");
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}
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}
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/**
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* @brief This function handles SVCall exception.
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* @param None
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* @retval None
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*/
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void SVC_Handler(void) {
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}
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/**
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* @brief This function handles Debug Monitor exception.
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* @param None
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* @retval None
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*/
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void DebugMon_Handler(void) {
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}
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