Wykres commitów

4 Commity (master)

Autor SHA1 Wiadomość Data
iabdalkader a00e1e5735 stm32/dac: Deinit all DACs on soft reset.
DAC timed functions continue to run after a soft reset cycle, using
collected memory in the case of write_timed.
2022-01-27 17:10:39 +11:00
Damien George aa7b32c811 stm32/dac: Rework DAC driver to use direct register access.
This patch makes the DAC driver simpler and removes the need for the ST
HAL.  As part of it, new helper functions are added to the DMA driver,
which also use direct register access instead of the ST HAL.

Main changes to the DAC interface are:

- The DAC uPy object is no longer allocated dynamically on the heap,
  rather it's statically allocated and the same object is retrieved for
  subsequent uses of pyb.DAC(<id>).  This allows to access the DAC objects
  without resetting the DAC peripheral.  It also means that the DAC is only
  reset if explicitly passed initialisation parameters, like "bits" or
  "buffering".

- The DAC.noise() and DAC.triangle() methods now output a signal which is
  full scale (previously it was a fraction of the full output voltage).

- The DAC.write_timed() method is fixed so that it continues in the
  background when another peripheral (eg SPI) uses the DMA (previously the
  DAC would stop if another peripheral finished with the DMA and shut the
  DMA peripheral off completely).

Based on the above, the following backwards incompatibilities are
introduced:

- pyb.DAC(id) will now only reset the DAC the first time it is called,
  whereas previously each call to create a DAC object would reset the DAC.
  To get the old behaviour pass the bits parameter like: pyb.DAC(id, bits).

- DAC.noise() and DAC.triangle() are now full scale.  To get previous
  behaviour (to change the amplitude and offset) write to the DAC_CR (MAMP
  bits) and DAC_DHR12Rx registers manually.
2019-04-24 15:51:19 +10:00
Damien George d966a33486 stm32: Change header include guards from STMHAL to STM32 to match dir. 2018-02-15 15:47:04 +11:00
Damien George 01dd7804b8 ports: Make new ports/ sub-directory and move all ports there.
This is to keep the top-level directory clean, to make it clear what is
core and what is a port, and to allow the repository to grow with new ports
in a sustainable way.
2017-09-06 13:40:51 +10:00