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samd/DAC: Add a callback keyword option to machine.DAC(). 

The callback is called when a dac_timed() sequence finishes. It will be
reset with callback=None or omitting the callback option in the
constructor.

Side change: Set the clock freq. to 48Mhz.

Signed-off-by: robert-hh <robert@hammelrath.com>
pull/9624/head
robert-hh 2022-09-13 18:50:42 +02:00
rodzic 94a1988698
commit f6c41257e9
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ID klucza GPG: 32EC5F755D5A3A93
2 zmienionych plików z 41 dodań i 9 usunięć
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46
ports/samd/machine_dac.c
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@ -49,14 +49,16 @@ typedef struct _dac_obj_t {
int8_t dma_channel;
int8_t tc_index;
uint32_t count;
mp_obj_t callback;
} dac_obj_t;
Dac *const dac_bases[] = DAC_INSTS;
static void dac_init(dac_obj_t *self, Dac *dac);
static mp_obj_t dac_deinit(mp_obj_t self_in);
#if defined(MCU_SAMD21)
static dac_obj_t dac_obj[] = {
{{&machine_dac_type}, 0, PIN_PA02},
{{&machine_dac_type}, 0, 0, PIN_PA02},
};
#define MAX_DAC_VALUE (1023)
@ -66,8 +68,8 @@ static dac_obj_t dac_obj[] = {
#elif defined(MCU_SAMD51)
static dac_obj_t dac_obj[] = {
{{&machine_dac_type}, 0, PIN_PA02},
{{&machine_dac_type}, 1, PIN_PA05},
{{&machine_dac_type}, 0, 0, PIN_PA02, 2, -1, -1, 1, NULL},
{{&machine_dac_type}, 1, 0, PIN_PA05, 2, -1, -1, 1, NULL},
};
// According to Errata 2.9.2, VDDANA as ref value is not available. However it worked
// in tests. So I keep the selection here but set the default to Aref, which is usually
@ -82,7 +84,6 @@ static uint8_t dac_vref_table[] = {
#endif // defined SAMD21 or SAMD51
void dac_irq_handler(int dma_channel) {
dac_obj_t *self;
@ -94,6 +95,10 @@ void dac_irq_handler(int dma_channel) {
self->count -= 1;
dma_desc[self->dma_channel].BTCTRL.reg |= DMAC_BTCTRL_VALID;
DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
} else {
if (self->callback != MP_OBJ_NULL) {
mp_sched_schedule(self->callback, self);
}
}
#elif defined(MCU_SAMD51)
@ -107,6 +112,10 @@ void dac_irq_handler(int dma_channel) {
self->count -= 1;
dma_desc[self->dma_channel].BTCTRL.reg |= DMAC_BTCTRL_VALID;
DMAC->Channel[self->dma_channel].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
} else {
if (self->callback != MP_OBJ_NULL) {
mp_sched_schedule(self->callback, self);
}
}
#endif
}
@ -114,10 +123,11 @@ void dac_irq_handler(int dma_channel) {
static mp_obj_t dac_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw,
const mp_obj_t *all_args) {
enum { ARG_id, ARG_vref };
enum { ARG_id, ARG_vref, ARG_callback };
static const mp_arg_t allowed_args[] = {
{ MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} },
{ MP_QSTR_vref, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_DAC_VREF} },
{ MP_QSTR_callback, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
};
// Parse the arguments.
@ -137,6 +147,15 @@ static mp_obj_t dac_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_
self->vref = vref;
}
self->callback = args[ARG_callback].u_obj;
if (self->callback == mp_const_none) {
self->callback = MP_OBJ_NULL;
}
self->dma_channel = -1;
self->tc_index = -1;
self->initialized = false;
Dac *dac = dac_bases[0]; // Just one DAC
dac_init(self, dac);
// Set the port as given in self->gpio_id as DAC
@ -151,9 +170,9 @@ static void dac_init(dac_obj_t *self, Dac *dac) {
#if defined(MCU_SAMD21)
// Configuration SAMD21
// Enable APBC clocks and PCHCTRL clocks; GCLK3 at 1 MHz
// Enable APBC clocks and PCHCTRL clocks; GCLK5 at 48 MHz
PM->APBCMASK.reg |= PM_APBCMASK_DAC;
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK3 | GCLK_CLKCTRL_ID_DAC;
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK5 | GCLK_CLKCTRL_ID_DAC;
while (GCLK->STATUS.bit.SYNCBUSY) {
}
// Reset DAC registers
@ -169,9 +188,9 @@ static void dac_init(dac_obj_t *self, Dac *dac) {
#elif defined(MCU_SAMD51)
// Configuration SAMD51
// Enable APBD clocks and PCHCTRL clocks; GCLK3 at 8 MHz
// Enable APBD clocks and PCHCTRL clocks; GCLK5 at 48 MHz
MCLK->APBDMASK.reg |= MCLK_APBDMASK_DAC;
GCLK->PCHCTRL[DAC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK3 | GCLK_PCHCTRL_CHEN;
GCLK->PCHCTRL[DAC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK5 | GCLK_PCHCTRL_CHEN;
// Reset DAC registers
dac->CTRLA.bit.SWRST = 1;
@ -317,10 +336,19 @@ static mp_obj_t dac_deinit(mp_obj_t self_in) {
free_tc_instance(self->tc_index);
self->tc_index = -1;
}
self->callback = MP_OBJ_NULL;
return mp_const_none;
}
MP_DEFINE_CONST_FUN_OBJ_1(dac_deinit_obj, dac_deinit);
// Clear the DMA channel entry in the DAC object.
void dac_deinit_channel(void) {
dac_obj[0].dma_channel = -1;
#if defined(MCU_SAMD51)
dac_obj[1].dma_channel = -1;
#endif
}
static const mp_rom_map_elem_t dac_locals_dict_table[] = {
{ MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&dac_deinit_obj) },
{ MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&dac_write_obj) },

4
ports/samd/main.c
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@ -40,6 +40,7 @@
extern uint8_t _sstack, _estack, _sheap, _eheap;
extern void adc_deinit_all(void);
extern void dac_deinit_channel(void);
extern void pin_irq_deinit_all(void);
extern void pwm_deinit_all(void);
extern void sercom_deinit_all(void);
@ -94,6 +95,9 @@ void samd_main(void) {
#if MICROPY_PY_MACHINE_ADC
adc_deinit_all();
#endif
#if MICROPY_PY_MACHINE_DAC
dac_deinit_channel();
#endif
pin_irq_deinit_all();
#if MICROPY_PY_MACHINE_PWM
pwm_deinit_all();