kopia lustrzana https://github.com/micropython/micropython
samd/ADC: Add a adc.read_timed() method.
Call: adc.read_timed(buffer, freq) buffer must be preallocated. The size determines the number of 16 bit words to be read. The numeric range of the results is that of the raw ADC. The call returns immediately, and the data transfer is done by DMA. The caller must wait sufficiently long until the data is sampled and can be noticed by a callback. No internal checks are made for a too-high freq value. Read speeds depends on Average and bit length setting: SAMD21: Max. 350kS/s (8 bit, Average 1) SAMD51: Max. 1 MS/s (8 bit, Average 1) Signed-off-by: robert-hh <robert@hammelrath.com>pull/9624/head
robert-hh
rodzic
3b08312c16
commit
94a1988698
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@ -52,7 +52,7 @@ static volatile DmacDescriptor dma_write_back[MICROPY_HW_DMA_CHANNELS] __attribu
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// List of channel flags: true: channel used, false: channel available
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static bool channel_list[MICROPY_HW_DMA_CHANNELS];
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STATIC bool dma_initialized = false;
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static bool dma_initialized = false;
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// allocate_channel(): retrieve an available channel. Return the number or -1
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int allocate_dma_channel(void) {
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@ -31,6 +31,10 @@
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#include "py/mphal.h"
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#include "sam.h"
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#include "pin_af.h"
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#include "modmachine.h"
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#include "samd_soc.h"
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#include "dma_manager.h"
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#include "tc_manager.h"
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typedef struct _machine_adc_obj_t {
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mp_obj_base_t base;
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@ -39,6 +43,8 @@ typedef struct _machine_adc_obj_t {
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uint8_t avg;
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uint8_t bits;
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uint8_t vref;
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int8_t dma_channel;
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int8_t tc_index;
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} machine_adc_obj_t;
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#define DEFAULT_ADC_BITS 12
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@ -85,6 +91,20 @@ static uint8_t resolution[] = {
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extern mp_int_t log2i(mp_int_t num);
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// Active just for SAMD21, stops the freerun mode
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// For SAMD51, just the INT flag is reset.
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void adc_irq_handler(int dma_channel) {
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#if defined(MCU_SAMD21)
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DMAC->CHID.reg = dma_channel;
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DMAC->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
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ADC->EVCTRL.bit.STARTEI = 0;
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#elif defined(MCU_SAMD51)
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DMAC->Channel[dma_channel].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
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#endif
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}
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static void mp_machine_adc_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
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(void)kind;
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machine_adc_obj_t *self = MP_OBJ_TO_PTR(self_in);
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@ -116,8 +136,9 @@ static mp_obj_t mp_machine_adc_make_new(const mp_obj_type_t *type, size_t n_args
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self->id = id;
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self->adc_config = adc_config;
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self->bits = DEFAULT_ADC_BITS;
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uint16_t bits = args[ARG_bits].u_int;
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if (bits >= 8 && bits <= 12) {
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if (8 <= bits && bits <= 12) {
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self->bits = bits;
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}
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uint32_t avg = log2i(args[ARG_average].u_int);
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@ -147,6 +168,14 @@ static mp_int_t mp_machine_adc_read_u16(machine_adc_obj_t *self) {
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adc->INPUTCTRL.reg = ADC_INPUTCTRL_MUXNEG_GND | self->adc_config.channel;
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// set resolution. Scale 8-16 to 0 - 4 for table access.
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adc->CTRLB.bit.RESSEL = resolution[(self->bits - 8) / 2];
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#if defined(MCU_SAMD21)
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// Stop the ADC sampling by timer
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adc->EVCTRL.bit.STARTEI = 0;
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#elif defined(MCU_SAMD51)
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// Do not restart ADC after data has bee read
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adc->DSEQCTRL.reg = 0;
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#endif
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// Measure input voltage
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adc->SWTRIG.bit.START = 1;
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while (adc->INTFLAG.bit.RESRDY == 0) {
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@ -155,9 +184,107 @@ static mp_int_t mp_machine_adc_read_u16(machine_adc_obj_t *self) {
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return adc->RESULT.reg * (65536 / (1 << self->bits));
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}
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static void machine_adc_read_timed(mp_obj_t self_in, mp_obj_t values, mp_obj_t freq_in) {
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machine_adc_obj_t *self = self_in;
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Adc *adc = adc_bases[self->adc_config.device];
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mp_buffer_info_t src;
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mp_get_buffer_raise(values, &src, MP_BUFFER_READ);
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if (src.len >= 2) {
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int freq = mp_obj_get_int(freq_in);
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if (self->dma_channel == -1) {
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self->dma_channel = allocate_dma_channel();
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dma_init();
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}
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if (self->tc_index == -1) {
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self->tc_index = allocate_tc_instance();
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}
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// Set Input channel and resolution
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// Select the pin as positive input and gnd as negative input reference, non-diff mode by default
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adc->INPUTCTRL.reg = ADC_INPUTCTRL_MUXNEG_GND | self->adc_config.channel;
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// set resolution. Scale 8-16 to 0 - 4 for table access.
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adc->CTRLB.bit.RESSEL = resolution[(self->bits - 8) / 2];
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// Configure DMA for halfword output to the DAC
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#if defined(MCU_SAMD21)
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// dma irq just for SAMD21 to stop the timer based acquisition
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dma_register_irq(self->dma_channel, adc_irq_handler);
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configure_tc(self->tc_index, freq, TC_EVCTRL_OVFEO);
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// Enable APBC clock
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PM->APBCMASK.reg |= PM_APBCMASK_EVSYS;
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// Set up the EVSYS channel
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EVSYS->CTRL.bit.SWRST = 1;
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EVSYS->USER.reg = EVSYS_USER_CHANNEL(ADC_EVSYS_CHANNEL + 1) |
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EVSYS_USER_USER(EVSYS_ID_USER_ADC_START);
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EVSYS->CHANNEL.reg = EVSYS_CHANNEL_CHANNEL(ADC_EVSYS_CHANNEL) |
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EVSYS_CHANNEL_EVGEN(EVSYS_ID_GEN_TC3_OVF + 3 * self->tc_index) |
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EVSYS_CHANNEL_PATH_ASYNCHRONOUS;
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dma_desc[self->dma_channel].BTCTRL.reg =
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DMAC_BTCTRL_VALID | DMAC_BTCTRL_BLOCKACT_NOACT |
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DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_DSTINC | DMAC_BTCTRL_STEPSEL |
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DMAC_BTCTRL_STEPSIZE(DMAC_BTCTRL_STEPSIZE_X1_Val);
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dma_desc[self->dma_channel].BTCNT.reg = src.len / 2;
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dma_desc[self->dma_channel].SRCADDR.reg = (uint32_t)(&adc->RESULT.reg);
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dma_desc[self->dma_channel].DSTADDR.reg = (uint32_t)(src.buf) + src.len;
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dma_desc[self->dma_channel].DESCADDR.reg = 0; // ONE_SHOT
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DMAC->CHID.reg = self->dma_channel;
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DMAC->CHCTRLA.reg = 0;
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while (DMAC->CHCTRLA.bit.ENABLE) {
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}
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DMAC->CHCTRLB.reg =
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DMAC_CHCTRLB_LVL(0) |
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DMAC_CHCTRLB_TRIGACT_BEAT |
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DMAC_CHCTRLB_TRIGSRC(ADC_DMAC_ID_RESRDY);
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DMAC->CHINTENSET.reg = DMAC_CHINTFLAG_TCMPL;
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DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
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NVIC_EnableIRQ(DMAC_IRQn);
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adc->EVCTRL.bit.STARTEI = 1;
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#elif defined(MCU_SAMD51)
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configure_tc(self->tc_index, freq, 0);
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// Restart ADC after data has bee read
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adc->DSEQCTRL.reg = ADC_DSEQCTRL_AUTOSTART;
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// Start the first sampling to ensure we get a proper first value.
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adc->SWTRIG.bit.START = 1;
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while (adc->INTFLAG.bit.RESRDY == 0) {
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}
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dma_desc[self->dma_channel].BTCTRL.reg =
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DMAC_BTCTRL_VALID | DMAC_BTCTRL_BLOCKACT_NOACT |
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DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_DSTINC | DMAC_BTCTRL_STEPSEL |
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DMAC_BTCTRL_STEPSIZE(DMAC_BTCTRL_STEPSIZE_X1_Val);
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dma_desc[self->dma_channel].BTCNT.reg = src.len / 2;
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dma_desc[self->dma_channel].SRCADDR.reg = (uint32_t)(&adc->RESULT.reg);
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dma_desc[self->dma_channel].DSTADDR.reg = (uint32_t)(src.buf) + src.len;
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dma_desc[self->dma_channel].DESCADDR.reg = 0; // ONE_SHOT
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DMAC->Channel[self->dma_channel].CHCTRLA.reg =
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DMAC_CHCTRLA_BURSTLEN(DMAC_CHCTRLA_BURSTLEN_SINGLE_Val) |
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DMAC_CHCTRLA_TRIGACT(DMAC_CHCTRLA_TRIGACT_BURST_Val) |
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DMAC_CHCTRLA_TRIGSRC(TC0_DMAC_ID_OVF + 3 * self->tc_index);
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DMAC->Channel[self->dma_channel].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
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#endif // defined SAMD21 or SAMD51
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}
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return mp_const_none;
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}
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// deinit() : release the ADC channel
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static void mp_machine_adc_deinit(machine_adc_obj_t *self) {
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busy_flags &= ~((1 << (self->adc_config.device * 16 + self->adc_config.channel)));
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if (self->dma_channel >= 0) {
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dac_stop_dma(self->dma_channel, true);
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free_dma_channel(self->dma_channel);
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self->dma_channel = -1;
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}
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if (self->tc_index >= 0) {
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free_tc_instance(self->tc_index);
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self->tc_index = -1;
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}
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}
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void adc_deinit_all(void) {
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@ -175,9 +302,9 @@ static void adc_init(machine_adc_obj_t *self) {
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#if defined(MCU_SAMD21)
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// Configuration SAMD21
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// Enable APBD clocks and PCHCTRL clocks; GCLK2 at 48 MHz
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// Enable APBD clocks and PCHCTRL clocks; GCLK5 at 48 MHz
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PM->APBCMASK.reg |= PM_APBCMASK_ADC;
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK2 | GCLK_CLKCTRL_ID_ADC;
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK5 | GCLK_CLKCTRL_ID_ADC;
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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// Reset ADC registers
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@ -190,7 +317,7 @@ static void adc_init(machine_adc_obj_t *self) {
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linearity |= ((*((uint32_t *)ADC_FUSES_LINEARITY_1_ADDR) & ADC_FUSES_LINEARITY_1_Msk) >> ADC_FUSES_LINEARITY_1_Pos) << 5;
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/* Write the calibration data. */
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ADC->CALIB.reg = ADC_CALIB_BIAS_CAL(bias) | ADC_CALIB_LINEARITY_CAL(linearity);
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// Divide 48MHz clock by 32 to obtain 1.5 MHz clock to adc
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// Divide a 48MHz clock by 32 to obtain 1.5 MHz clock to adc
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adc->CTRLB.reg = ADC_CTRLB_PRESCALER_DIV32;
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// Select external AREFA as reference voltage.
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adc->REFCTRL.reg = adc_vref_table[self->vref];
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@ -203,12 +330,12 @@ static void adc_init(machine_adc_obj_t *self) {
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#elif defined(MCU_SAMD51)
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// Configuration SAMD51
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// Enable APBD clocks and PCHCTRL clocks; GCLK2 at 48 MHz
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// Enable APBD clocks and PCHCTRL clocks; GCLK5 at 48 MHz
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if (self->adc_config.device == 0) {
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GCLK->PCHCTRL[ADC0_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN;
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GCLK->PCHCTRL[ADC0_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK5 | GCLK_PCHCTRL_CHEN;
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MCLK->APBDMASK.bit.ADC0_ = 1;
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} else {
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GCLK->PCHCTRL[ADC1_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN;
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GCLK->PCHCTRL[ADC1_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK5 | GCLK_PCHCTRL_CHEN;
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MCLK->APBDMASK.bit.ADC1_ = 1;
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}
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// Reset ADC registers
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@ -230,8 +357,10 @@ static void adc_init(machine_adc_obj_t *self) {
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}
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/* Write the calibration data. */
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adc->CALIB.reg = ADC_CALIB_BIASCOMP(biascomp) | ADC_CALIB_BIASR2R(biasr2r) | ADC_CALIB_BIASREFBUF(biasrefbuf);
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// Divide 48MHz clock by 32 to obtain 1.5 MHz clock to adc
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adc->CTRLA.reg = ADC_CTRLA_PRESCALER_DIV32;
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// Divide 48MHz clock by 4 to obtain 12 MHz clock to adc
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adc->CTRLA.reg = ADC_CTRLA_PRESCALER_DIV4;
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// Enable the offset compensation
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adc->SAMPCTRL.reg = ADC_SAMPCTRL_OFFCOMP;
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// Set the reference voltage. Default: external AREFA.
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adc->REFCTRL.reg = adc_vref_table[self->vref];
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// Average: Accumulate samples and scale them down accordingly
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@ -51,11 +51,11 @@ typedef struct _dac_obj_t {
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uint32_t count;
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} dac_obj_t;
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Dac *const dac_bases[] = DAC_INSTS;
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STATIC void dac_init(dac_obj_t *self, Dac *dac);
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static void dac_init(dac_obj_t *self, Dac *dac);
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#if defined(MCU_SAMD21)
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STATIC dac_obj_t dac_obj[] = {
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static dac_obj_t dac_obj[] = {
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{{&machine_dac_type}, 0, PIN_PA02},
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};
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@ -65,7 +65,7 @@ STATIC dac_obj_t dac_obj[] = {
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#elif defined(MCU_SAMD51)
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STATIC dac_obj_t dac_obj[] = {
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static dac_obj_t dac_obj[] = {
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{{&machine_dac_type}, 0, PIN_PA02},
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{{&machine_dac_type}, 1, PIN_PA05},
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};
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@ -145,7 +145,7 @@ static mp_obj_t dac_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_
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return MP_OBJ_FROM_PTR(self);
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}
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STATIC void dac_init(dac_obj_t *self, Dac *dac) {
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static void dac_init(dac_obj_t *self, Dac *dac) {
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// Init DAC
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if (self->initialized == false) {
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#if defined(MCU_SAMD21)
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@ -190,7 +190,7 @@ STATIC void dac_init(dac_obj_t *self, Dac *dac) {
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self->initialized = true;
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}
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STATIC void dac_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
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static void dac_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
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dac_obj_t *self = self_in;
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mp_printf(print, "DAC(%u, Pin=%q, vref=%d)", self->id, pin_find_by_id(self->gpio_id)->name, self->vref);
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}
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@ -215,7 +215,7 @@ static mp_obj_t dac_write(mp_obj_t self_in, mp_obj_t value_in) {
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}
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MP_DEFINE_CONST_FUN_OBJ_2(dac_write_obj, dac_write);
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STATIC mp_obj_t dac_write_timed(size_t n_args, const mp_obj_t *args) {
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static mp_obj_t dac_write_timed(size_t n_args, const mp_obj_t *args) {
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Dac *dac = dac_bases[0]; // Just one DAC used
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dac_obj_t *self = args[0];
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mp_buffer_info_t src;
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@ -239,7 +239,7 @@ STATIC mp_obj_t dac_write_timed(size_t n_args, const mp_obj_t *args) {
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self->tc_index = allocate_tc_instance();
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}
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// Configure TC; no need to check the return value
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configure_tc(self->tc_index, freq);
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configure_tc(self->tc_index, freq, 0);
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// Configure DMA for halfword output to the DAC
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#if defined(MCU_SAMD21)
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@ -301,9 +301,9 @@ STATIC mp_obj_t dac_write_timed(size_t n_args, const mp_obj_t *args) {
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}
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return mp_const_none;
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}
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STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(dac_write_timed_obj, 3, 4, dac_write_timed);
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static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(dac_write_timed_obj, 3, 4, dac_write_timed);
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STATIC mp_obj_t dac_deinit(mp_obj_t self_in) {
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static mp_obj_t dac_deinit(mp_obj_t self_in) {
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dac_obj_t *self = self_in;
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self->initialized = false;
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// Reset the DAC to lower the current consumption as SAMD21
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@ -321,7 +321,7 @@ STATIC mp_obj_t dac_deinit(mp_obj_t self_in) {
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}
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MP_DEFINE_CONST_FUN_OBJ_1(dac_deinit_obj, dac_deinit);
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STATIC const mp_rom_map_elem_t dac_locals_dict_table[] = {
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static const mp_rom_map_elem_t dac_locals_dict_table[] = {
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{ MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&dac_deinit_obj) },
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{ MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&dac_write_obj) },
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{ MP_ROM_QSTR(MP_QSTR_write_timed), MP_ROM_PTR(&dac_write_timed_obj) },
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@ -57,7 +57,7 @@ void free_tc_instance(int tc_index) {
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}
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}
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int configure_tc(int tc_index, int freq) {
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int configure_tc(int tc_index, int freq, int event) {
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uint32_t clock = DFLL48M_FREQ; // Use the fixed 48M clock
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Tc *tc;
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@ -105,6 +105,9 @@ int configure_tc(int tc_index, int freq) {
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TC_CTRLA_MODE_COUNT16 | TC_CTRLA_RUNSTDBY |
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TC_CTRLA_WAVEGEN_MFRQ;
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tc->COUNT16.CC[0].reg = period;
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if (event) {
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tc->COUNT16.EVCTRL.reg = event;
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}
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tc->COUNT16.CTRLA.bit.ENABLE = 1;
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while (tc->COUNT16.STATUS.bit.SYNCBUSY) {
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@ -31,7 +31,7 @@
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int allocate_tc_instance(void);
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void free_tc_instance(int tc_index);
|
||||
int configure_tc(int tc_index, int freq);
|
||||
int configure_tc(int tc_index, int freq, int event);
|
||||
void tc_deinit(void);
|
||||
|
||||
extern Tc *tc_instance_list[];
|
||||
|
|
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Ładowanie…
Reference in New Issue