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samd/DAC: Add the dac.write_timed(). 

Call:
dac.write_timed(data, freq [, count])
dac.deinit()

Working range for dac_timed():

SAMD21: 1 Hz - 100 kHz (1 MHz clock, 10 bit)
SAMD51: 1 Hz - ~500 kHz (8 MHz clock, 12 bit)

The buffer has to be a byte array or a halfword array,
and the data is sent once.

The default for count is 1. If set to a value > 0, the data will be
transmitted count times. If set to 0 or  < 0, the date will be
transmitted until deliberately stopped. The playback
can be stopped with dac.deinit().

dac.deinit() just releases the timer and DMA channel needed by
dac_timed(). The DAC object itself does not have to be released.

Signed-off-by: robert-hh <robert@hammelrath.com>
pull/9624/head
robert-hh 2022-09-05 11:29:08 +02:00
rodzic 9226188a46
commit 3b08312c16
Nie znaleziono w bazie danych klucza dla tego podpisu
ID klucza GPG: 32EC5F755D5A3A93
5 zmienionych plików z 213 dodań i 56 usunięć
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2
ports/samd/Makefile
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@ -101,6 +101,7 @@ MPY_CROSS_FLAGS += -march=$(MPY_CROSS_MCU_ARCH)
SRC_C += \
mcu/$(MCU_SERIES_LOWER)/clock_config.c \
dma_manager.c \
help.c \
machine_bitstream.c \
machine_dac.c \
@ -119,6 +120,7 @@ SRC_C += \
samd_soc.c \
samd_spiflash.c \
usbd.c \
tc_manager.c \
SHARED_SRC_C += \
drivers/dht/dht.c \

1
ports/samd/dma_manager.h
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@ -32,6 +32,7 @@ int allocate_dma_channel(void);
void free_dma_channel(int n);
void dma_init(void);
void dma_deinit(void);
void dac_stop_dma(int dma_channel, bool wait);
extern volatile DmacDescriptor dma_desc[];

261
ports/samd/machine_dac.c
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@ -36,32 +36,39 @@
#include "sam.h"
#include "pin_af.h"
#include "modmachine.h"
#include "samd_soc.h"
#include "dma_manager.h"
#include "tc_manager.h"
typedef struct _dac_obj_t {
mp_obj_base_t base;
uint8_t id;
bool initialized;
mp_hal_pin_obj_t gpio_id;
uint8_t vref;
int8_t dma_channel;
int8_t tc_index;
uint32_t count;
} dac_obj_t;
static dac_obj_t dac_obj[] = {
#if defined(MCU_SAMD21)
{{&machine_dac_type}, 0, PIN_PA02},
#elif defined(MCU_SAMD51)
{{&machine_dac_type}, 0, PIN_PA02},
{{&machine_dac_type}, 1, PIN_PA05},
#endif
};
Dac *const dac_bases[] = DAC_INSTS;
STATIC void dac_init(dac_obj_t *self, Dac *dac);
#if defined(MCU_SAMD21)
STATIC dac_obj_t dac_obj[] = {
{{&machine_dac_type}, 0, PIN_PA02},
};
#define MAX_DAC_VALUE (1023)
#define DEFAULT_DAC_VREF (1)
#define MAX_DAC_VREF (2)
#elif defined(MCU_SAMD51)
STATIC dac_obj_t dac_obj[] = {
{{&machine_dac_type}, 0, PIN_PA02},
{{&machine_dac_type}, 1, PIN_PA05},
};
// According to Errata 2.9.2, VDDANA as ref value is not available. However it worked
// in tests. So I keep the selection here but set the default to Aref, which is usually
// connected at the Board to VDDANA
@ -72,9 +79,37 @@ static uint8_t dac_vref_table[] = {
#define MAX_DAC_VALUE (4095)
#define DEFAULT_DAC_VREF (2)
#define MAX_DAC_VREF (3)
static bool dac_init = false;
#endif
#endif // defined SAMD21 or SAMD51
void dac_irq_handler(int dma_channel) {
dac_obj_t *self;
#if defined(MCU_SAMD21)
DMAC->CHID.reg = dma_channel;
DMAC->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
self = &dac_obj[0];
if (self->count > 1) {
self->count -= 1;
dma_desc[self->dma_channel].BTCTRL.reg |= DMAC_BTCTRL_VALID;
DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
}
#elif defined(MCU_SAMD51)
DMAC->Channel[dma_channel].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
if (dac_obj[0].dma_channel == dma_channel) {
self = &dac_obj[0];
} else {
self = &dac_obj[1];
}
if (self->count > 1) {
self->count -= 1;
dma_desc[self->dma_channel].BTCTRL.reg |= DMAC_BTCTRL_VALID;
DMAC->Channel[self->dma_channel].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
}
#endif
}
static mp_obj_t dac_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw,
const mp_obj_t *all_args) {
@ -103,68 +138,76 @@ static mp_obj_t dac_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_
}
Dac *dac = dac_bases[0]; // Just one DAC
// Init DAC
#if defined(MCU_SAMD21)
// Configuration SAMD21
// Enable APBC clocks and PCHCTRL clocks; GCLK3 at 1 MHz
PM->APBCMASK.reg |= PM_APBCMASK_DAC;
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK3 | GCLK_CLKCTRL_ID_DAC;
while (GCLK->STATUS.bit.SYNCBUSY) {
}
// Reset DAC registers
dac->CTRLA.bit.SWRST = 1;
while (dac->CTRLA.bit.SWRST) {
}
dac->CTRLB.reg = DAC_CTRLB_EOEN | DAC_CTRLB_REFSEL(self->vref);
// Enable DAC and wait to be ready
dac->CTRLA.bit.ENABLE = 1;
while (dac->STATUS.bit.SYNCBUSY) {
}
#elif defined(MCU_SAMD51)
// Configuration SAMD51
// Enable APBD clocks and PCHCTRL clocks; GCLK3 at 8 MHz
dac_init = true;
MCLK->APBDMASK.reg |= MCLK_APBDMASK_DAC;
GCLK->PCHCTRL[DAC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK3 | GCLK_PCHCTRL_CHEN;
// Reset DAC registers
dac->CTRLA.bit.SWRST = 1;
while (dac->CTRLA.bit.SWRST) {
}
dac->CTRLB.reg = DAC_CTRLB_REFSEL(dac_vref_table[self->vref]);
dac->DACCTRL[self->id].reg = DAC_DACCTRL_ENABLE | DAC_DACCTRL_REFRESH(2) | DAC_DACCTRL_CCTRL_CC12M;
// Enable DAC and wait to be ready
dac->CTRLA.bit.ENABLE = 1;
while (dac->SYNCBUSY.bit.ENABLE) {
}
#endif
dac_init(self, dac);
// Set the port as given in self->gpio_id as DAC
mp_hal_set_pin_mux(self->gpio_id, ALT_FCT_DAC);
return MP_OBJ_FROM_PTR(self);
}
static void dac_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
STATIC void dac_init(dac_obj_t *self, Dac *dac) {
// Init DAC
if (self->initialized == false) {
#if defined(MCU_SAMD21)
// Configuration SAMD21
// Enable APBC clocks and PCHCTRL clocks; GCLK3 at 1 MHz
PM->APBCMASK.reg |= PM_APBCMASK_DAC;
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK3 | GCLK_CLKCTRL_ID_DAC;
while (GCLK->STATUS.bit.SYNCBUSY) {
}
// Reset DAC registers
dac->CTRLA.bit.SWRST = 1;
while (dac->CTRLA.bit.SWRST) {
}
dac->CTRLB.reg = DAC_CTRLB_EOEN | DAC_CTRLB_REFSEL(self->vref);
// Enable DAC and wait to be ready
dac->CTRLA.bit.ENABLE = 1;
while (dac->STATUS.bit.SYNCBUSY) {
}
#elif defined(MCU_SAMD51)
// Configuration SAMD51
// Enable APBD clocks and PCHCTRL clocks; GCLK3 at 8 MHz
MCLK->APBDMASK.reg |= MCLK_APBDMASK_DAC;
GCLK->PCHCTRL[DAC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK3 | GCLK_PCHCTRL_CHEN;
// Reset DAC registers
dac->CTRLA.bit.SWRST = 1;
while (dac->CTRLA.bit.SWRST) {
}
dac->CTRLB.reg = DAC_CTRLB_REFSEL(dac_vref_table[self->vref]);
dac->DACCTRL[self->id].reg = DAC_DACCTRL_ENABLE | DAC_DACCTRL_REFRESH(2) | DAC_DACCTRL_CCTRL_CC12M;
// Enable DAC and wait to be ready
dac->CTRLA.bit.ENABLE = 1;
while (dac->SYNCBUSY.bit.ENABLE) {
}
#endif // defined SAMD21 or SAMD51
}
self->initialized = true;
}
STATIC void dac_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
dac_obj_t *self = self_in;
mp_printf(print, "DAC(%u, Pin=%q, vref=%d)", self->id, pin_find_by_id(self->gpio_id)->name, self->vref);
}
static mp_obj_t dac_write(mp_obj_t self_in, mp_obj_t value_in) {
Dac *dac = dac_bases[0]; // Just one DAC
dac_obj_t *self = self_in;
int value = mp_obj_get_int(value_in);
if (value < 0 || value > MAX_DAC_VALUE) {
mp_raise_ValueError(MP_ERROR_TEXT("value out of range"));
}
// Re-init, if required
dac_init(self, dac);
#if defined(MCU_SAMD21)
dac->DATA.reg = value;
#elif defined(MCU_SAMD51)
dac_obj_t *self = self_in;
dac->DATA[self->id].reg = value;
#endif
@ -172,8 +215,116 @@ static mp_obj_t dac_write(mp_obj_t self_in, mp_obj_t value_in) {
}
MP_DEFINE_CONST_FUN_OBJ_2(dac_write_obj, dac_write);
static const mp_rom_map_elem_t dac_locals_dict_table[] = {
STATIC mp_obj_t dac_write_timed(size_t n_args, const mp_obj_t *args) {
Dac *dac = dac_bases[0]; // Just one DAC used
dac_obj_t *self = args[0];
mp_buffer_info_t src;
// Re-init, if required
dac_init(self, dac);
mp_get_buffer_raise(args[1], &src, MP_BUFFER_READ);
if (n_args > 3) {
self->count = mp_obj_get_int(args[3]);
} else {
self->count = 1;
}
if (src.len >= 2) {
int freq = mp_obj_get_int(args[2]);
if (self->dma_channel == -1) {
self->dma_channel = allocate_dma_channel();
dma_init();
dma_register_irq(self->dma_channel, dac_irq_handler);
}
if (self->tc_index == -1) {
self->tc_index = allocate_tc_instance();
}
// Configure TC; no need to check the return value
configure_tc(self->tc_index, freq);
// Configure DMA for halfword output to the DAC
#if defined(MCU_SAMD21)
dma_desc[self->dma_channel].BTCTRL.reg =
DMAC_BTCTRL_VALID | DMAC_BTCTRL_BLOCKACT_NOACT |
DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_SRCINC | DMAC_BTCTRL_STEPSEL |
DMAC_BTCTRL_STEPSIZE(DMAC_BTCTRL_STEPSIZE_X1_Val);
dma_desc[self->dma_channel].BTCNT.reg = src.len / 2;
dma_desc[self->dma_channel].SRCADDR.reg = (uint32_t)(src.buf) + src.len;
dma_desc[self->dma_channel].DSTADDR.reg = (uint32_t)(&dac->DATA.reg);
if (self->count >= 1) {
dma_desc[self->dma_channel].DESCADDR.reg = 0; // ONE_SHOT
} else {
dma_desc[self->dma_channel].DESCADDR.reg = (uint32_t)(&dma_desc[self->dma_channel].BTCTRL.reg);
}
DMAC->CHID.reg = self->dma_channel;
DMAC->CHCTRLA.reg = 0;
while (DMAC->CHCTRLA.bit.ENABLE) {
}
DMAC->CHCTRLB.reg =
DMAC_CHCTRLB_LVL(0) |
DMAC_CHCTRLB_TRIGACT_BEAT |
DMAC_CHCTRLB_TRIGSRC(TC3_DMAC_ID_OVF + 3 * self->tc_index);
DMAC->CHINTENSET.reg = DMAC_CHINTFLAG_TCMPL;
DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
NVIC_EnableIRQ(DMAC_IRQn);
#elif defined(MCU_SAMD51)
dma_desc[self->dma_channel].BTCTRL.reg =
DMAC_BTCTRL_VALID | DMAC_BTCTRL_BLOCKACT_NOACT |
DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_SRCINC | DMAC_BTCTRL_STEPSEL |
DMAC_BTCTRL_STEPSIZE(DMAC_BTCTRL_STEPSIZE_X1_Val);
dma_desc[self->dma_channel].BTCNT.reg = src.len / 2;
dma_desc[self->dma_channel].SRCADDR.reg = (uint32_t)(src.buf) + src.len;
dma_desc[self->dma_channel].DSTADDR.reg = (uint32_t)(&dac->DATA[self->id].reg);
if (self->count >= 1) {
dma_desc[self->dma_channel].DESCADDR.reg = 0; // ONE_SHOT
} else {
dma_desc[self->dma_channel].DESCADDR.reg = (uint32_t)(&dma_desc[self->dma_channel].BTCTRL.reg);
}
DMAC->Channel[self->dma_channel].CHCTRLA.reg =
DMAC_CHCTRLA_BURSTLEN(DMAC_CHCTRLA_BURSTLEN_SINGLE_Val) |
DMAC_CHCTRLA_TRIGACT(DMAC_CHCTRLA_TRIGACT_BURST_Val) |
DMAC_CHCTRLA_TRIGSRC(TC0_DMAC_ID_OVF + 3 * self->tc_index);
DMAC->Channel[self->dma_channel].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
DMAC->Channel[self->dma_channel].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
if (self->dma_channel < 4) {
NVIC_EnableIRQ(DMAC_0_IRQn + self->dma_channel);
} else {
NVIC_EnableIRQ(DMAC_4_IRQn);
}
#endif // defined SAMD21 or SAMD51
}
return mp_const_none;
}
STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(dac_write_timed_obj, 3, 4, dac_write_timed);
STATIC mp_obj_t dac_deinit(mp_obj_t self_in) {
dac_obj_t *self = self_in;
self->initialized = false;
// Reset the DAC to lower the current consumption as SAMD21
dac_bases[0]->CTRLA.bit.SWRST = 1;
if (self->dma_channel >= 0) {
dac_stop_dma(self->dma_channel, true);
free_dma_channel(self->dma_channel);
self->dma_channel = -1;
}
if (self->tc_index >= 0) {
free_tc_instance(self->tc_index);
self->tc_index = -1;
}
return mp_const_none;
}
MP_DEFINE_CONST_FUN_OBJ_1(dac_deinit_obj, dac_deinit);
STATIC const mp_rom_map_elem_t dac_locals_dict_table[] = {
{ MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&dac_deinit_obj) },
{ MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&dac_write_obj) },
{ MP_ROM_QSTR(MP_QSTR_write_timed), MP_ROM_PTR(&dac_write_timed_obj) },
};
static MP_DEFINE_CONST_DICT(dac_locals_dict, dac_locals_dict_table);

4
ports/samd/main.c
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@ -35,6 +35,8 @@
#include "shared/runtime/softtimer.h"
#include "shared/tinyusb/mp_usbd.h"
#include "clock_config.h"
#include "dma_manager.h"
#include "tc_manager.h"
extern uint8_t _sstack, _estack, _sheap, _eheap;
extern void adc_deinit_all(void);
@ -87,6 +89,8 @@ void samd_main(void) {
soft_reset_exit:
mp_printf(MP_PYTHON_PRINTER, "MPY: soft reboot\n");
dma_deinit();
tc_deinit();
#if MICROPY_PY_MACHINE_ADC
adc_deinit_all();
#endif

1
ports/samd/samd_soc.c
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@ -68,7 +68,6 @@ static void usb_init(void) {
void init_us_counter(void) {
#if defined(MCU_SAMD21)
PM->APBCMASK.bit.TC3_ = 1; // Enable TC3 clock
PM->APBCMASK.bit.TC4_ = 1; // Enable TC4 clock
// Select multiplexer generic clock source and enable.
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK3 | GCLK_CLKCTRL_ID_TC4_TC5;