kopia lustrzana https://github.com/micropython/micropython
stm32: Add support for dual-analog-pad "_C" pins on H7 MCUs.
This commit adds support for the dual-analog-pads on STM32H7 parts. These
pads/pins are called PA0_C/PA1_C/PC2_C/PC3_C in the datasheet. They each
have an analog switch that can optionally connect them to their normal pin
(eg PA0). When the switch is open, the normal and _C pin are independent
pins/pads.
The approach taken in this commit to make these _C pins available to Python
is:
- put them in their own, independent row in the stm32h7_af.csv definition
file, with only the ADC column defined (they are separate machine.Pin
entities, and doing it this way keeps make-pins.py pretty clean)
- allow a board to reference these pins in the board's pins.csv file by the
name PA0_C etc (so a board can alias them, for example)
- these pins (when enabled in pins.csv) now become available like any other
machine.Pin through both machine.Pin.board and machine.Pin.cpu
- BUT these _C pins have a separate pin type which doesn't have any
methods, because they don't have any functionality
- these _C pins can be used with machine.ADC to construct the appropriate
ADC object, either by passing the string as machine.ADC("PA0_C") or by
passing the object as machine.ADC(machine.Pin.cpu.PA0_C)
- if a board defines both the normal and _C pin (eg both PA0 and PA0_C) in
pins.csv then it must not define the analog switch to be closed (this is
a sanity check for the build, because it doesn't make sense to close the
switch and have two separate pins)
Signed-off-by: Damien George <damien@micropython.org>
pull/13764/head
Damien George
rodzic
7fd8a6d4bc
commit
a9efffca96
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@ -59,6 +59,12 @@ class Stm32Pin(boardgen.Pin):
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def __init__(self, cpu_pin_name):
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def __init__(self, cpu_pin_name):
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super().__init__(cpu_pin_name)
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super().__init__(cpu_pin_name)
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# Pins ending in "_C" correspond to the analog-only pad of a pair
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# of dual (analog) pads found on H7 MCUs (eg PA0 and PA0_C pair).
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self._analog_only = cpu_pin_name.endswith("_C")
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if self._analog_only:
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cpu_pin_name = cpu_pin_name[:-2]
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# P<port><num> (already verified by validate_cpu_pin_name).
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# P<port><num> (already verified by validate_cpu_pin_name).
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self._port = cpu_pin_name[1]
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self._port = cpu_pin_name[1]
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self._pin = int(cpu_pin_name[2:])
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self._pin = int(cpu_pin_name[2:])
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@ -129,11 +135,6 @@ class Stm32Pin(boardgen.Pin):
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# be the P for one channel, and the N for a different channel.
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# be the P for one channel, and the N for a different channel.
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# e.g. "ADC123_INP12/ADC123_INN11".
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# e.g. "ADC123_INP12/ADC123_INN11".
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for adc_name in adc.split("/"):
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for adc_name in adc.split("/"):
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if adc_name.startswith("C_"):
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# Currently unsupported, H7 dual-pad. The C_ADC entries should
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# only be available directly from machine.ADC (not via the pin
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# object).
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continue
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m = re.match("ADC([1-5]+)_(IN[NP]?)([0-9]+)$", adc_name)
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m = re.match("ADC([1-5]+)_(IN[NP]?)([0-9]+)$", adc_name)
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if not m:
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if not m:
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raise boardgen.PinGeneratorError(
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raise boardgen.PinGeneratorError(
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@ -167,8 +168,9 @@ class Stm32Pin(boardgen.Pin):
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)
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)
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# PIN(p_port, p_pin, p_af, p_adc_num, p_adc_channel)
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# PIN(p_port, p_pin, p_af, p_adc_num, p_adc_channel)
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return "PIN({:s}, {:d}, pin_{:s}_af, {:s}, {:d})".format(
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pin_macro = "PIN_ANALOG" if self._analog_only else "PIN"
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self._port, self._pin, self.name(), adc_units_bitfield, self._adc_channel
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return "{:s}({:s}, {:d}, pin_{:s}_af, {:s}, {:d})".format(
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pin_macro, self._port, self._pin, self.name(), adc_units_bitfield, self._adc_channel
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)
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)
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# This will be called at the start of the output (after the prefix). Use
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# This will be called at the start of the output (after the prefix). Use
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@ -210,7 +212,7 @@ class Stm32Pin(boardgen.Pin):
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def validate_cpu_pin_name(cpu_pin_name):
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def validate_cpu_pin_name(cpu_pin_name):
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boardgen.Pin.validate_cpu_pin_name(cpu_pin_name)
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boardgen.Pin.validate_cpu_pin_name(cpu_pin_name)
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if not re.match("P[A-K][0-9]+$", cpu_pin_name):
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if not re.match("P[A-K][0-9]+(_C)?$", cpu_pin_name):
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raise boardgen.PinGeneratorError("Invalid cpu pin name '{}'".format(cpu_pin_name))
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raise boardgen.PinGeneratorError("Invalid cpu pin name '{}'".format(cpu_pin_name))
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@ -30,3 +30,21 @@
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.adc_num = p_adc_num, \
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.adc_num = p_adc_num, \
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.adc_channel = p_adc_channel, \
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.adc_channel = p_adc_channel, \
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}
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}
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#if MICROPY_HW_ENABLE_ANALOG_ONLY_PINS
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#define PIN_ANALOG(p_port, p_pin, p_af, p_adc_num, p_adc_channel) \
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{ \
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{ &pin_analog_type }, \
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.name = MP_QSTR_##p_port##p_pin##_C, \
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.port = PORT_##p_port, \
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.pin = (p_pin), \
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.num_af = (sizeof(p_af) / sizeof(pin_af_obj_t)), \
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.pin_mask = (1 << ((p_pin) & 0x0f)), \
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.gpio = GPIO##p_port, \
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.af = p_af, \
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.adc_num = p_adc_num, \
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.adc_channel = p_adc_channel, \
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}
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#else
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#define PIN_ANALOG DUAL_PAD_SUPPORT_NOT_ENABLED__CONFIGURE__MICROPY_HW_ANALOG_SWITCH_Pxy
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#endif
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@ -34,8 +34,10 @@ PortB,PB14, ,TIM1_CH2N ,TIM12_CH1
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PortB,PB15,RTC_REFIN ,TIM1_CH3N ,TIM12_CH2 ,TIM8_CH3N ,USART1_RX ,SPI2_MOSI/I2S2_SDO ,DFSDM1_CKIN2 , ,UART4_CTS ,SDMMC2_D1 , , ,FMC_D11/FMC_AD11 , ,LCD_G7 ,EVENTOUT,
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PortB,PB15,RTC_REFIN ,TIM1_CH3N ,TIM12_CH2 ,TIM8_CH3N ,USART1_RX ,SPI2_MOSI/I2S2_SDO ,DFSDM1_CKIN2 , ,UART4_CTS ,SDMMC2_D1 , , ,FMC_D11/FMC_AD11 , ,LCD_G7 ,EVENTOUT,
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PortC,PC0 , ,FMC_D12/FMC_AD12 , ,DFSDM1_CKIN0 , , ,DFSDM1_DATIN4 , ,SAI4_FS_B ,FMC_A25 ,OTG_HS_ULPI_STP ,LCD_G2 ,FMC_SDNWE , ,LCD_R5 ,EVENTOUT,ADC123_INP10
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PortC,PC0 , ,FMC_D12/FMC_AD12 , ,DFSDM1_CKIN0 , , ,DFSDM1_DATIN4 , ,SAI4_FS_B ,FMC_A25 ,OTG_HS_ULPI_STP ,LCD_G2 ,FMC_SDNWE , ,LCD_R5 ,EVENTOUT,ADC123_INP10
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PortC,PC1 ,TRACED0 ,SAI4_D1 ,SAI1_D1 ,DFSDM1_DATIN0 ,DFSDM1_CKIN4 ,SPI2_MOSI/I2S2_SDO ,SAI1_SD_A , ,SAI4_SD_A ,SDMMC2_CK ,OCTOSPIM_P1_IO4 ,ETH_MDC ,MDIOS_MDC , ,LCD_G5 ,EVENTOUT,ADC123_INP11/ADC123_INN10
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PortC,PC1 ,TRACED0 ,SAI4_D1 ,SAI1_D1 ,DFSDM1_DATIN0 ,DFSDM1_CKIN4 ,SPI2_MOSI/I2S2_SDO ,SAI1_SD_A , ,SAI4_SD_A ,SDMMC2_CK ,OCTOSPIM_P1_IO4 ,ETH_MDC ,MDIOS_MDC , ,LCD_G5 ,EVENTOUT,ADC123_INP11/ADC123_INN10
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PortC,PC2 ,PWR_DEEPSLEEP, , ,DFSDM1_CKIN1 ,OCTOSPIM_P1_IO5 ,SPI2_MISO/I2S2_SDI ,DFSDM1_CKOUT , , ,OCTOSPIM_P1_IO2 ,OTG_HS_ULPI_DIR ,ETH_MII_TXD2 ,FMC_SDNE0 , , ,EVENTOUT,ADC123_INP12/ADC123_INN11/C_ADC3_INN1/C_ADC3_INP0
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PortC,PC2 ,PWR_DEEPSLEEP, , ,DFSDM1_CKIN1 ,OCTOSPIM_P1_IO5 ,SPI2_MISO/I2S2_SDI ,DFSDM1_CKOUT , , ,OCTOSPIM_P1_IO2 ,OTG_HS_ULPI_DIR ,ETH_MII_TXD2 ,FMC_SDNE0 , , ,EVENTOUT,ADC123_INP12/ADC123_INN11
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PortC,PC3 ,PWR_SLEEP , , ,DFSDM1_DATIN1 ,OCTOSPIM_P1_IO6 ,SPI2_MOSI/I2S2_SDO , , , ,OCTOSPIM_P1_IO0 ,OTG_HS_ULPI_NXT ,ETH_MII_TX_CLK ,FMC_SDCKE0 , , ,EVENTOUT,ADC12_INP13/ADC12_INN12/C_ADC3_INP1
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PortC,PC2_C, , , , , , , , , , , , , , , , ,ADC3_INN1/ADC3_INP0
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PortC,PC3 ,PWR_SLEEP , , ,DFSDM1_DATIN1 ,OCTOSPIM_P1_IO6 ,SPI2_MOSI/I2S2_SDO , , , ,OCTOSPIM_P1_IO0 ,OTG_HS_ULPI_NXT ,ETH_MII_TX_CLK ,FMC_SDCKE0 , , ,EVENTOUT,ADC12_INP13/ADC12_INN12
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PortC,PC3_C, , , , , , , , , , , , , , , , ,ADC3_INP1
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PortC,PC4 ,PWR_DEEPSLEEP,FMC_A22 , ,DFSDM1_CKIN2 , ,I2S1_MCK , , , ,SPDIFRX1_IN3 ,SDMMC2_CKIN ,ETH_MII_RXD0/ETH_RMII_RXD0 ,FMC_SDNE0 , ,LCD_R7 ,EVENTOUT,ADC12_INP4
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PortC,PC4 ,PWR_DEEPSLEEP,FMC_A22 , ,DFSDM1_CKIN2 , ,I2S1_MCK , , , ,SPDIFRX1_IN3 ,SDMMC2_CKIN ,ETH_MII_RXD0/ETH_RMII_RXD0 ,FMC_SDNE0 , ,LCD_R7 ,EVENTOUT,ADC12_INP4
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PortC,PC5 ,PWR_SLEEP ,SAI4_D3 ,SAI1_D3 ,DFSDM1_DATIN2 ,PSSI_D15 , , , , ,SPDIFRX1_IN4 ,OCTOSPIM_P1_DQS ,ETH_MII_RXD1/ETH_RMII_RXD1 ,FMC_SDCKE0 ,COMP1_OUT ,LCD_DE ,EVENTOUT,ADC12_INP8/ADC12_INN4
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PortC,PC5 ,PWR_SLEEP ,SAI4_D3 ,SAI1_D3 ,DFSDM1_DATIN2 ,PSSI_D15 , , , , ,SPDIFRX1_IN4 ,OCTOSPIM_P1_DQS ,ETH_MII_RXD1/ETH_RMII_RXD1 ,FMC_SDCKE0 ,COMP1_OUT ,LCD_DE ,EVENTOUT,ADC12_INP8/ADC12_INN4
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PortC,PC6 , , ,TIM3_CH1 ,TIM8_CH1 ,DFSDM1_CKIN3 ,I2S2_MCK , ,USART6_TX ,SDMMC1_D0DIR ,FMC_NWAIT ,SDMMC2_D6 , ,SDMMC1_D6 ,DCMI_D0/PSSI_D0 ,LCD_HSYNC ,EVENTOUT,
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PortC,PC6 , , ,TIM3_CH1 ,TIM8_CH1 ,DFSDM1_CKIN3 ,I2S2_MCK , ,USART6_TX ,SDMMC1_D0DIR ,FMC_NWAIT ,SDMMC2_D6 , ,SDMMC1_D6 ,DCMI_D0/PSSI_D0 ,LCD_HSYNC ,EVENTOUT,
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@ -1,7 +1,9 @@
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Port ,Pin ,AF0 ,AF1 ,AF2 ,AF3 ,AF4 ,AF5 ,AF6 ,AF7 ,AF8 ,AF9 ,AF10 ,AF11 ,AF12 ,AF13 ,AF14 ,AF15 ,ADC
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Port ,Pin ,AF0 ,AF1 ,AF2 ,AF3 ,AF4 ,AF5 ,AF6 ,AF7 ,AF8 ,AF9 ,AF10 ,AF11 ,AF12 ,AF13 ,AF14 ,AF15 ,ADC
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, ,SYS ,TIM1/2/16/17/LPTIM1/HRTIM1,SAI1/TIM3/4/5/12/HRTIM1,LPUART/TIM8/LPTIM2/3/4/5/HRTIM1/DFSDM,I2C1/2/3/4/USART1/TIM15/LPTIM2/DFSDM/CEC,SPI1/2/3/4/5/6/CEC,SPI2/3/SAI1/3/I2C4/UART4/DFSDM,SPI2/3/6/USART1/2/3/6/UART7/SDMMC1,SPI6/SAI2/4/UART4/5/8/LPUART/SDMMC1/SPDIFRX,SAI4/FDCAN1/2/TIM13/14/QUADSPI/FMC/SDMMC2/LCD/SPDIFRX,SAI2/4/TIM8/QUADSPI/SDMMC2/OTG1_HS/OTG2_FS/LCD,I2C4/UART7/SWPMI1/TIM1/8/DFSDM/SDMMC2/MDIOS/ETH,TIM1/8/FMC/SDMMC1/MDIOS/OTG1_FS/LCD,TIM1/DCMI/LCD/COMP,UART5/LCD,SYS ,ADC
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, ,SYS ,TIM1/2/16/17/LPTIM1/HRTIM1,SAI1/TIM3/4/5/12/HRTIM1,LPUART/TIM8/LPTIM2/3/4/5/HRTIM1/DFSDM,I2C1/2/3/4/USART1/TIM15/LPTIM2/DFSDM/CEC,SPI1/2/3/4/5/6/CEC,SPI2/3/SAI1/3/I2C4/UART4/DFSDM,SPI2/3/6/USART1/2/3/6/UART7/SDMMC1,SPI6/SAI2/4/UART4/5/8/LPUART/SDMMC1/SPDIFRX,SAI4/FDCAN1/2/TIM13/14/QUADSPI/FMC/SDMMC2/LCD/SPDIFRX,SAI2/4/TIM8/QUADSPI/SDMMC2/OTG1_HS/OTG2_FS/LCD,I2C4/UART7/SWPMI1/TIM1/8/DFSDM/SDMMC2/MDIOS/ETH,TIM1/8/FMC/SDMMC1/MDIOS/OTG1_FS/LCD,TIM1/DCMI/LCD/COMP,UART5/LCD,SYS ,ADC
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PortA,PA0 , ,TIM2_CH1/TIM2_ETR ,TIM5_CH1 ,TIM8_ETR ,TIM15_BKIN , , ,USART2_CTS/USART2_NSS ,UART4_TX ,SDMMC2_CMD ,SAI2_SD_B ,ETH_MII_CRS , , , ,EVENTOUT,ADC1_INP16/C_ADC12_INN1/C_ADC12_INP0
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PortA,PA0 , ,TIM2_CH1/TIM2_ETR ,TIM5_CH1 ,TIM8_ETR ,TIM15_BKIN , , ,USART2_CTS/USART2_NSS ,UART4_TX ,SDMMC2_CMD ,SAI2_SD_B ,ETH_MII_CRS , , , ,EVENTOUT,ADC1_INP16
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PortA,PA1 , ,TIM2_CH2 ,TIM5_CH2 ,LPTIM3_OUT ,TIM15_CH1N , , ,USART2_RTS ,UART4_RX ,QUADSPI_BK1_IO3 ,SAI2_MCK_B ,ETH_MII_RX_CLK/ETH_RMII_REF_CLK , , ,LCD_R2 ,EVENTOUT,ADC1_INN16/ADC1_INP17/C_ADC12_INP1
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PortA,PA0_C, , , , , , , , , , , , , , , , ,ADC12_INP0
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PortA,PA1 , ,TIM2_CH2 ,TIM5_CH2 ,LPTIM3_OUT ,TIM15_CH1N , , ,USART2_RTS ,UART4_RX ,QUADSPI_BK1_IO3 ,SAI2_MCK_B ,ETH_MII_RX_CLK/ETH_RMII_REF_CLK , , ,LCD_R2 ,EVENTOUT,ADC1_INN16/ADC1_INP17/ADC12_INP1
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PortA,PA1_C, , , , , , , , , , , , , , , , ,ADC12_INP1
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PortA,PA2 , ,TIM2_CH3 ,TIM5_CH3 ,LPTIM4_OUT ,TIM15_CH1 , , ,USART2_TX ,SAI2_SCK_B , , ,ETH_MDIO ,MDIOS_MDIO , ,LCD_R1 ,EVENTOUT,ADC12_INP14
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PortA,PA2 , ,TIM2_CH3 ,TIM5_CH3 ,LPTIM4_OUT ,TIM15_CH1 , , ,USART2_TX ,SAI2_SCK_B , , ,ETH_MDIO ,MDIOS_MDIO , ,LCD_R1 ,EVENTOUT,ADC12_INP14
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PortA,PA3 , ,TIM2_CH4 ,TIM5_CH4 ,LPTIM5_OUT ,TIM15_CH2 , , ,USART2_RX , ,LCD_B2 ,OTG_HS_ULPI_D0 ,ETH_MII_COL , , ,LCD_B5 ,EVENTOUT,ADC12_INP15
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PortA,PA3 , ,TIM2_CH4 ,TIM5_CH4 ,LPTIM5_OUT ,TIM15_CH2 , , ,USART2_RX , ,LCD_B2 ,OTG_HS_ULPI_D0 ,ETH_MII_COL , , ,LCD_B5 ,EVENTOUT,ADC12_INP15
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PortA,PA4 , , ,TIM5_ETR , , ,SPI1_NSS/I2S1_WS ,SPI3_NSS/I2S3_WS ,USART2_CK ,SPI6_NSS , , , ,OTG_HS_SOF ,DCMI_HSYNC ,LCD_VSYNC,EVENTOUT,ADC12_INP18
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PortA,PA4 , , ,TIM5_ETR , , ,SPI1_NSS/I2S1_WS ,SPI3_NSS/I2S3_WS ,USART2_CK ,SPI6_NSS , , , ,OTG_HS_SOF ,DCMI_HSYNC ,LCD_VSYNC,EVENTOUT,ADC12_INP18
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@ -34,8 +36,10 @@ PortB,PB14, ,TIM1_CH2N ,TIM12_CH1 ,TIM8
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PortB,PB15,RTC_REFIN ,TIM1_CH3N ,TIM12_CH2 ,TIM8_CH3N ,USART1_RX ,SPI2_MOSI/I2S2_SDO,DFSDM_CKIN2 , ,UART4_CTS ,SDMMC2_D1 , , ,OTG_HS_DP , , ,EVENTOUT,
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PortB,PB15,RTC_REFIN ,TIM1_CH3N ,TIM12_CH2 ,TIM8_CH3N ,USART1_RX ,SPI2_MOSI/I2S2_SDO,DFSDM_CKIN2 , ,UART4_CTS ,SDMMC2_D1 , , ,OTG_HS_DP , , ,EVENTOUT,
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PortC,PC0 , , , ,DFSDM_CKIN0 , , ,DFSDM_DATIN4 , ,SAI2_FS_B , ,OTG_HS_ULPI_STP , ,FMC_SDNWE , ,LCD_R5 ,EVENTOUT,ADC123_INP10
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PortC,PC0 , , , ,DFSDM_CKIN0 , , ,DFSDM_DATIN4 , ,SAI2_FS_B , ,OTG_HS_ULPI_STP , ,FMC_SDNWE , ,LCD_R5 ,EVENTOUT,ADC123_INP10
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PortC,PC1 ,TRACED0 , ,SAI1_D1 ,DFSDM_DATIN0 ,DFSDM_CKIN4 ,SPI2_MOSI/I2S2_SDO,SAI1_SD_A , ,SAI4_SD_A ,SDMMC2_CK ,SAI4_D1 ,ETH_MDC ,MDIOS_MDC , , ,EVENTOUT,ADC123_INN10/ADC123_INP11
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PortC,PC1 ,TRACED0 , ,SAI1_D1 ,DFSDM_DATIN0 ,DFSDM_CKIN4 ,SPI2_MOSI/I2S2_SDO,SAI1_SD_A , ,SAI4_SD_A ,SDMMC2_CK ,SAI4_D1 ,ETH_MDC ,MDIOS_MDC , , ,EVENTOUT,ADC123_INN10/ADC123_INP11
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PortC,PC2 , , , ,DFSDM_CKIN1 , ,SPI2_MISO/I2S2_SDI,DFSDM_CKOUT , , , ,OTG_HS_ULPI_DIR ,ETH_MII_TXD2 ,FMC_SDNE0 , , ,EVENTOUT,ADC123_INN11/ADC123_INP12/C_ADC3_INN1/C_ADC3_INP0
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PortC,PC2 , , , ,DFSDM_CKIN1 , ,SPI2_MISO/I2S2_SDI,DFSDM_CKOUT , , , ,OTG_HS_ULPI_DIR ,ETH_MII_TXD2 ,FMC_SDNE0 , , ,EVENTOUT,ADC123_INN11/ADC123_INP12
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PortC,PC3 , , , ,DFSDM_DATIN1 , ,SPI2_MOSI/I2S2_SDO, , , , ,OTG_HS_ULPI_NXT ,ETH_MII_TX_CLK ,FMC_SDCKE0 , , ,EVENTOUT,ADC12_INN12/ADC12_INP13/C_ADC3_INP1
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PortC,PC2_C, , , , , , , , , , , , , , , , ,ADC3_INP0
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PortC,PC3 , , , ,DFSDM_DATIN1 , ,SPI2_MOSI/I2S2_SDO, , , , ,OTG_HS_ULPI_NXT ,ETH_MII_TX_CLK ,FMC_SDCKE0 , , ,EVENTOUT,ADC12_INN12/ADC12_INP13
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PortC,PC3_C, , , , , , , , , , , , , , , , ,ADC3_INP1
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PortC,PC4 , , , ,DFSDM_CKIN2 , ,I2S1_MCK , , , ,SPDIFRX_IN2 , ,ETH_MII_RXD0/ETH_RMII_RXD0 ,FMC_SDNE0 , , ,EVENTOUT,ADC12_INP4
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PortC,PC4 , , , ,DFSDM_CKIN2 , ,I2S1_MCK , , , ,SPDIFRX_IN2 , ,ETH_MII_RXD0/ETH_RMII_RXD0 ,FMC_SDNE0 , , ,EVENTOUT,ADC12_INP4
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PortC,PC5 , , ,SAI1_D3 ,DFSDM_DATIN2 , , , , , ,SPDIFRX_IN3 ,SAI4_D3 ,ETH_MII_RXD1/ETH_RMII_RXD1 ,FMC_SDCKE0 ,COMP_1_OUT , ,EVENTOUT,ADC12_INN4/ADC12_INP8
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PortC,PC5 , , ,SAI1_D3 ,DFSDM_DATIN2 , , , , , ,SPDIFRX_IN3 ,SAI4_D3 ,ETH_MII_RXD1/ETH_RMII_RXD1 ,FMC_SDCKE0 ,COMP_1_OUT , ,EVENTOUT,ADC12_INN4/ADC12_INP8
|
||||||
PortC,PC6 , ,HRTIM_CHA1 ,TIM3_CH1 ,TIM8_CH1 ,DFSDM_CKIN3 ,I2S2_MCK , ,USART6_TX ,SDMMC1_D0DIR ,FMC_NWAIT ,SDMMC2_D6 , ,SDMMC1_D6 ,DCMI_D0 ,LCD_HSYNC,EVENTOUT,
|
PortC,PC6 , ,HRTIM_CHA1 ,TIM3_CH1 ,TIM8_CH1 ,DFSDM_CKIN3 ,I2S2_MCK , ,USART6_TX ,SDMMC1_D0DIR ,FMC_NWAIT ,SDMMC2_D6 , ,SDMMC1_D6 ,DCMI_D0 ,LCD_HSYNC,EVENTOUT,
|
||||||
|
|
|
||||||
|
|
|
@ -1,7 +1,9 @@
|
||||||
Port ,Pin ,AF0 ,AF1 ,AF2 ,AF3 ,AF4 ,AF5 ,AF6 ,AF7 ,AF8 ,AF9 ,AF10 ,AF11 ,AF12 ,AF13 ,AF14 ,AF15 ,ADC
|
Port ,Pin ,AF0 ,AF1 ,AF2 ,AF3 ,AF4 ,AF5 ,AF6 ,AF7 ,AF8 ,AF9 ,AF10 ,AF11 ,AF12 ,AF13 ,AF14 ,AF15 ,ADC
|
||||||
, ,SYS ,LPTIM1/TIM1/2/16/17,PDM_SAI1/TIM3/4/5/12/15,DFSDM1/LPTIM2/3/LPUART1/OCTOSPIM_P1/2/TIM8,CEC/DCMI/PSSI/DFSDM1/2/I2C1/2/3/4/LPTIM2/TIM15/USART1,CEC/SPI1/I2S1/SPI2/I2S2/SPI3/I2S3/SPI4/5/SPI6/I2S6,DFSDM1/2/I2C4/OCTOSPIM_P1/SAI1/SPI3/I2S3/UART4,SDMMC1/SPI2/I2S2/SPI3/I2S3/SPI6/I2S6/UART7/USART1/2/3/6,LPUART1/SAI2/SDMMC1/SPDIFRX1/SPI6/I2S6/UART4/5/8,FDCAN1/2/FMC/LCD/OCTOSPIM_P1/2/SDMMC2/SPDIFRX1/TIM13/14,CRS/FMC/LCD/OCTOSPIM_P1/OTG1_FS/OTG1_HS/SAI2/SDMMC2/TIM8,DFSDM1/2/I2C4/LCD/MDIOS/OCTOSPIM_P1/SDMMC2/SWPMI1/TIM1/8/UART7/9/USART10,FMC/LCD/MDIOS/SDMMC1/TIM1/8 ,COMP/DCMI/PSSI/LCD/TIM1 ,LCD/UART5 ,SYS ,ADC
|
, ,SYS ,LPTIM1/TIM1/2/16/17,PDM_SAI1/TIM3/4/5/12/15,DFSDM1/LPTIM2/3/LPUART1/OCTOSPIM_P1/2/TIM8,CEC/DCMI/PSSI/DFSDM1/2/I2C1/2/3/4/LPTIM2/TIM15/USART1,CEC/SPI1/I2S1/SPI2/I2S2/SPI3/I2S3/SPI4/5/SPI6/I2S6,DFSDM1/2/I2C4/OCTOSPIM_P1/SAI1/SPI3/I2S3/UART4,SDMMC1/SPI2/I2S2/SPI3/I2S3/SPI6/I2S6/UART7/USART1/2/3/6,LPUART1/SAI2/SDMMC1/SPDIFRX1/SPI6/I2S6/UART4/5/8,FDCAN1/2/FMC/LCD/OCTOSPIM_P1/2/SDMMC2/SPDIFRX1/TIM13/14,CRS/FMC/LCD/OCTOSPIM_P1/OTG1_FS/OTG1_HS/SAI2/SDMMC2/TIM8,DFSDM1/2/I2C4/LCD/MDIOS/OCTOSPIM_P1/SDMMC2/SWPMI1/TIM1/8/UART7/9/USART10,FMC/LCD/MDIOS/SDMMC1/TIM1/8 ,COMP/DCMI/PSSI/LCD/TIM1 ,LCD/UART5 ,SYS ,ADC
|
||||||
PortA,PA0 , ,TIM2_CH1/TIM2_ETR ,TIM5_CH1 ,TIM8_ETR ,TIM15_BKIN ,I2S6_WS/SPI6_NSS , ,USART2_CTS/USART2_NSS ,UART4_TX ,SDMMC2_CMD ,SAI2_SD_B , , , , ,EVENTOUT,ADC1_INP16/C_ADC1_INP0/C_ADC1_INN1
|
PortA,PA0 , ,TIM2_CH1/TIM2_ETR ,TIM5_CH1 ,TIM8_ETR ,TIM15_BKIN ,I2S6_WS/SPI6_NSS , ,USART2_CTS/USART2_NSS ,UART4_TX ,SDMMC2_CMD ,SAI2_SD_B , , , , ,EVENTOUT,ADC1_INP16
|
||||||
PortA,PA1 , ,TIM2_CH2 ,TIM5_CH2 ,LPTIM3_OUT ,TIM15_CH1N , , ,USART2_DE/USART2_RTS ,UART4_RX ,OCTOSPIM_P1_IO3 ,SAI2_MCLK_B ,OCTOSPIM_P1_DQS , , ,LTDC_R2 ,EVENTOUT,ADC1_INN16/ADC1_INP17/C_ADC1_INP1
|
PortA,PA0_C, , , , , , , , , , , , , , , , ,ADC1_INP0/ADC1_INN1
|
||||||
|
PortA,PA1 , ,TIM2_CH2 ,TIM5_CH2 ,LPTIM3_OUT ,TIM15_CH1N , , ,USART2_DE/USART2_RTS ,UART4_RX ,OCTOSPIM_P1_IO3 ,SAI2_MCLK_B ,OCTOSPIM_P1_DQS , , ,LTDC_R2 ,EVENTOUT,ADC1_INN16/ADC1_INP17
|
||||||
|
PortA,PA1_C, , , , , , , , , , , , , , , , ,ADC1_INP1
|
||||||
PortA,PA2 , ,TIM2_CH3 ,TIM5_CH3 , ,TIM15_CH1 , ,DFSDM2_CKIN1 ,USART2_TX ,SAI2_SCK_B , , , ,MDIOS_MDIO , ,LTDC_R1 ,EVENTOUT,ADC1_INP14
|
PortA,PA2 , ,TIM2_CH3 ,TIM5_CH3 , ,TIM15_CH1 , ,DFSDM2_CKIN1 ,USART2_TX ,SAI2_SCK_B , , , ,MDIOS_MDIO , ,LTDC_R1 ,EVENTOUT,ADC1_INP14
|
||||||
PortA,PA3 , ,TIM2_CH4 ,TIM5_CH4 ,OCTOSPIM_P1_CLK ,TIM15_CH2 ,I2S6_MCK , ,USART2_RX , ,LTDC_B2 ,USB_OTG_HS_ULPI_D0 , , , ,LTDC_B5 ,EVENTOUT,ADC1_INP15
|
PortA,PA3 , ,TIM2_CH4 ,TIM5_CH4 ,OCTOSPIM_P1_CLK ,TIM15_CH2 ,I2S6_MCK , ,USART2_RX , ,LTDC_B2 ,USB_OTG_HS_ULPI_D0 , , , ,LTDC_B5 ,EVENTOUT,ADC1_INP15
|
||||||
PortA,PA4 , , ,TIM5_ETR , , ,I2S1_WS/SPI1_NSS ,I2S3_WS/SPI3_NSS ,USART2_CK ,I2S6_WS/SPI6_NSS , , , , ,DCMI_HSYNC/PSSI_DE ,LTDC_VSYNC,EVENTOUT,ADC1_INP18
|
PortA,PA4 , , ,TIM5_ETR , , ,I2S1_WS/SPI1_NSS ,I2S3_WS/SPI3_NSS ,USART2_CK ,I2S6_WS/SPI6_NSS , , , , ,DCMI_HSYNC/PSSI_DE ,LTDC_VSYNC,EVENTOUT,ADC1_INP18
|
||||||
|
|
@ -34,8 +36,10 @@ PortB,PB14, ,TIM1_CH2N ,TIM12_CH1 ,TIM8_CH2
|
||||||
PortB,PB15,RTC_REFIN ,TIM1_CH3N ,TIM12_CH2 ,TIM8_CH3N ,USART1_RX ,I2S2_SDO/SPI2_MOSI ,DFSDM1_CKIN2 , ,UART4_CTS ,SDMMC2_D1 , , , , ,LTDC_G7 ,EVENTOUT,
|
PortB,PB15,RTC_REFIN ,TIM1_CH3N ,TIM12_CH2 ,TIM8_CH3N ,USART1_RX ,I2S2_SDO/SPI2_MOSI ,DFSDM1_CKIN2 , ,UART4_CTS ,SDMMC2_D1 , , , , ,LTDC_G7 ,EVENTOUT,
|
||||||
PortC,PC0 , , , ,DFSDM1_CKIN0 , , ,DFSDM1_DATIN4 , ,SAI2_FS_B ,FMC_A25 ,USB_OTG_HS_ULPI_STP ,LTDC_G2 ,FMC_SDNWE , ,LTDC_R5 ,EVENTOUT,ADC12_INP10
|
PortC,PC0 , , , ,DFSDM1_CKIN0 , , ,DFSDM1_DATIN4 , ,SAI2_FS_B ,FMC_A25 ,USB_OTG_HS_ULPI_STP ,LTDC_G2 ,FMC_SDNWE , ,LTDC_R5 ,EVENTOUT,ADC12_INP10
|
||||||
PortC,PC1 ,DEBUG_TRACED0 , ,SAI1_D1 ,DFSDM1_DATIN0 ,DFSDM1_CKIN4 ,I2S2_SDO/SPI2_MOSI ,SAI1_SD_A , , ,SDMMC2_CK ,OCTOSPIM_P1_IO4 , ,MDIOS_MDC , ,LTDC_G5 ,EVENTOUT,ADC12_INN10/ADC12_INP11
|
PortC,PC1 ,DEBUG_TRACED0 , ,SAI1_D1 ,DFSDM1_DATIN0 ,DFSDM1_CKIN4 ,I2S2_SDO/SPI2_MOSI ,SAI1_SD_A , , ,SDMMC2_CK ,OCTOSPIM_P1_IO4 , ,MDIOS_MDC , ,LTDC_G5 ,EVENTOUT,ADC12_INN10/ADC12_INP11
|
||||||
PortC,PC2 ,PWR_CSTOP , , ,DFSDM1_CKIN1 , ,I2S2_SDI/SPI2_MISO ,DFSDM1_CKOUT , , ,OCTOSPIM_P1_IO2 ,USB_OTG_HS_ULPI_DIR ,OCTOSPIM_P1_IO5 ,FMC_SDNE0 , , ,EVENTOUT,ADC12_INN11/ADC12_INP12/C_ADC2_INP0/C_ADC2_INN1
|
PortC,PC2 ,PWR_CSTOP , , ,DFSDM1_CKIN1 , ,I2S2_SDI/SPI2_MISO ,DFSDM1_CKOUT , , ,OCTOSPIM_P1_IO2 ,USB_OTG_HS_ULPI_DIR ,OCTOSPIM_P1_IO5 ,FMC_SDNE0 , , ,EVENTOUT,ADC12_INN11/ADC12_INP12
|
||||||
PortC,PC3 ,PWR_CSLEEP , , ,DFSDM1_DATIN1 , ,I2S2_SDO/SPI2_MOSI , , , ,OCTOSPIM_P1_IO0 ,USB_OTG_HS_ULPI_NXT ,OCTOSPIM_P1_IO6 ,FMC_SDCKE0 , , ,EVENTOUT,ADC12_INP13,ADC12_INN12/C_ADC2_INP1
|
PortC,PC2_C, , , , , , , , , , , , , , , , ,ADC2_INP0/ADC2_INN1
|
||||||
|
PortC,PC3 ,PWR_CSLEEP , , ,DFSDM1_DATIN1 , ,I2S2_SDO/SPI2_MOSI , , , ,OCTOSPIM_P1_IO0 ,USB_OTG_HS_ULPI_NXT ,OCTOSPIM_P1_IO6 ,FMC_SDCKE0 , , ,EVENTOUT,ADC12_INP13,ADC12_INN12
|
||||||
|
PortC,PC3_C, , , , , , , , , , , , , , , , ,ADC2_INP1
|
||||||
PortC,PC4 , , , ,DFSDM1_CKIN2 , ,I2S1_MCK , , , ,SPDIFRX_IN3 , , ,FMC_SDNE0 , ,LTDC_R7 ,EVENTOUT,ADC12_INP4
|
PortC,PC4 , , , ,DFSDM1_CKIN2 , ,I2S1_MCK , , , ,SPDIFRX_IN3 , , ,FMC_SDNE0 , ,LTDC_R7 ,EVENTOUT,ADC12_INP4
|
||||||
PortC,PC5 , , ,SAI1_D3 ,DFSDM1_DATIN2 ,PSSI_D15 , , , , ,SPDIFRX_IN4 ,OCTOSPIM_P1_DQS , ,FMC_SDCKE0 ,COMP1_OUT ,LTDC_DE ,EVENTOUT,ADC12_INN4/ADC12_INP8
|
PortC,PC5 , , ,SAI1_D3 ,DFSDM1_DATIN2 ,PSSI_D15 , , , , ,SPDIFRX_IN4 ,OCTOSPIM_P1_DQS , ,FMC_SDCKE0 ,COMP1_OUT ,LTDC_DE ,EVENTOUT,ADC12_INN4/ADC12_INP8
|
||||||
PortC,PC6 , , ,TIM3_CH1 ,TIM8_CH1 ,DFSDM1_CKIN3 ,I2S2_MCK , ,USART6_TX ,SDMMC1_D0DIR ,FMC_NWAIT ,SDMMC2_D6 , ,SDMMC1_D6 ,DCMI_D0/PSSI_D0 ,LTDC_HSYNC,EVENTOUT,
|
PortC,PC6 , , ,TIM3_CH1 ,TIM8_CH1 ,DFSDM1_CKIN3 ,I2S2_MCK , ,USART6_TX ,SDMMC1_D0DIR ,FMC_NWAIT ,SDMMC2_D6 , ,SDMMC1_D6 ,DCMI_D0/PSSI_D0 ,LTDC_HSYNC,EVENTOUT,
|
||||||
|
|
|
||||||
|
Nie można renderować tego pliku, ponieważ ma nieprawidłową liczbę pól w wierszu 38.
|
|
|
@ -390,6 +390,15 @@
|
||||||
#define MICROPY_HW_MAX_UART (8)
|
#define MICROPY_HW_MAX_UART (8)
|
||||||
#define MICROPY_HW_MAX_LPUART (1)
|
#define MICROPY_HW_MAX_LPUART (1)
|
||||||
|
|
||||||
|
#if defined(MICROPY_HW_ANALOG_SWITCH_PA0) \
|
||||||
|
|| defined(MICROPY_HW_ANALOG_SWITCH_PA1) \
|
||||||
|
|| defined(MICROPY_HW_ANALOG_SWITCH_PC2) \
|
||||||
|
|| defined(MICROPY_HW_ANALOG_SWITCH_PC3)
|
||||||
|
#define MICROPY_HW_ENABLE_ANALOG_ONLY_PINS (1)
|
||||||
|
#else
|
||||||
|
#define MICROPY_HW_ENABLE_ANALOG_ONLY_PINS (0)
|
||||||
|
#endif
|
||||||
|
|
||||||
// Configuration for STM32L0 series
|
// Configuration for STM32L0 series
|
||||||
#elif defined(STM32L0)
|
#elif defined(STM32L0)
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -103,7 +103,11 @@ const machine_pin_obj_t *pin_find(mp_obj_t user_obj) {
|
||||||
const machine_pin_obj_t *pin_obj;
|
const machine_pin_obj_t *pin_obj;
|
||||||
|
|
||||||
// If a pin was provided, then use it
|
// If a pin was provided, then use it
|
||||||
if (mp_obj_is_type(user_obj, &pin_type)) {
|
if (mp_obj_is_type(user_obj, &pin_type)
|
||||||
|
#if MICROPY_HW_ENABLE_ANALOG_ONLY_PINS
|
||||||
|
|| mp_obj_is_type(user_obj, &pin_analog_type)
|
||||||
|
#endif
|
||||||
|
) {
|
||||||
pin_obj = MP_OBJ_TO_PTR(user_obj);
|
pin_obj = MP_OBJ_TO_PTR(user_obj);
|
||||||
if (pin_class_debug) {
|
if (pin_class_debug) {
|
||||||
mp_printf(print, "Pin map passed pin ");
|
mp_printf(print, "Pin map passed pin ");
|
||||||
|
|
@ -601,6 +605,44 @@ MP_DEFINE_CONST_OBJ_TYPE(
|
||||||
locals_dict, &pin_locals_dict
|
locals_dict, &pin_locals_dict
|
||||||
);
|
);
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
// Special analog-only pin.
|
||||||
|
|
||||||
|
#if MICROPY_HW_ENABLE_ANALOG_ONLY_PINS
|
||||||
|
|
||||||
|
// When both normal and _C pins are defined in pins.csv, force the corresponding
|
||||||
|
// analog switch to be open. The macro code below will produce a compiler warning
|
||||||
|
// if the board defines the switch as closed.
|
||||||
|
#if defined(pin_A0) && defined(pin_A0_C)
|
||||||
|
#define MICROPY_HW_ANALOG_SWITCH_PA0 (SYSCFG_SWITCH_PA0_OPEN)
|
||||||
|
#endif
|
||||||
|
#if defined(pin_A1) && defined(pin_A1_C)
|
||||||
|
#define MICROPY_HW_ANALOG_SWITCH_PA1 (SYSCFG_SWITCH_PA1_OPEN)
|
||||||
|
#endif
|
||||||
|
#if defined(pin_C2) && defined(pin_C2_C)
|
||||||
|
#define MICROPY_HW_ANALOG_SWITCH_PC2 (SYSCFG_SWITCH_PC2_OPEN)
|
||||||
|
#endif
|
||||||
|
#if defined(pin_C3) && defined(pin_C3_C)
|
||||||
|
#define MICROPY_HW_ANALOG_SWITCH_PC3 (SYSCFG_SWITCH_PC3_OPEN)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static void pin_analog_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
|
||||||
|
machine_pin_obj_t *self = MP_OBJ_TO_PTR(self_in);
|
||||||
|
mp_printf(print, "Pin(Pin.cpu.%q, mode=Pin.ANALOG)", self->name);
|
||||||
|
}
|
||||||
|
|
||||||
|
MP_DEFINE_CONST_OBJ_TYPE(
|
||||||
|
pin_analog_type,
|
||||||
|
MP_QSTR_Pin,
|
||||||
|
MP_TYPE_FLAG_NONE,
|
||||||
|
print, pin_analog_print
|
||||||
|
);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
// PinAF class
|
||||||
|
|
||||||
/// \moduleref pyb
|
/// \moduleref pyb
|
||||||
/// \class PinAF - Pin Alternate Functions
|
/// \class PinAF - Pin Alternate Functions
|
||||||
///
|
///
|
||||||
|
|
|
||||||
|
|
@ -56,6 +56,7 @@ typedef struct {
|
||||||
} machine_pin_obj_t;
|
} machine_pin_obj_t;
|
||||||
|
|
||||||
extern const mp_obj_type_t pin_type;
|
extern const mp_obj_type_t pin_type;
|
||||||
|
extern const mp_obj_type_t pin_analog_type;
|
||||||
extern const mp_obj_type_t pin_af_type;
|
extern const mp_obj_type_t pin_af_type;
|
||||||
|
|
||||||
// Include all of the individual pin objects
|
// Include all of the individual pin objects
|
||||||
|
|
|
||||||
Ładowanie…
Reference in New Issue