kopia lustrzana https://github.com/micropython/micropython
samd/ADC: Add a callback keyword option to machine.ADC().
Enabling a callback that will be called when a adc.read_timed_into() run is finished. That's especially useful with slow sampling rates and/or many samples, avoiding to guess the sampling time. Raise an error is adc.read_u16() is called while a read_timed_into() is active. Other ADC changes: - SAMD51: use ADC1 if both ADC1 and ADC0 are available at a Pin. Signed-off-by: robert-hh <robert@hammelrath.com>pull/9624/head
robert-hh
rodzic
f6c41257e9
commit
7197c8adc0
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@ -28,6 +28,13 @@
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// This file is never compiled standalone, it's included directly from
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// extmod/machine_adc.c via MICROPY_PY_MACHINE_ADC_INCLUDEFILE.
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#if MICROPY_PY_MACHINE_ADC
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#include <stdint.h>
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#include "py/obj.h"
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#include "py/runtime.h"
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#include "py/mperrno.h"
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#include "py/mphal.h"
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#include "sam.h"
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#include "pin_af.h"
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@ -51,6 +58,7 @@ typedef struct _machine_adc_obj_t {
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#define DEFAULT_ADC_AVG 16
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#if defined(MCU_SAMD21)
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static uint8_t adc_vref_table[] = {
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ADC_REFCTRL_REFSEL_INT1V_Val, ADC_REFCTRL_REFSEL_INTVCC0_Val,
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ADC_REFCTRL_REFSEL_INTVCC1_Val, ADC_REFCTRL_REFSEL_AREFA_Val, ADC_REFCTRL_REFSEL_AREFB_Val
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@ -60,9 +68,19 @@ static uint8_t adc_vref_table[] = {
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#else
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#define DEFAULT_ADC_VREF (3)
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#endif
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#define MAX_ADC_VREF (4)
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#define ADC_EVSYS_CHANNEL 0
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typedef struct _device_mgmt_t {
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bool init;
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bool busy;
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mp_obj_t callback;
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mp_obj_t self;
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} device_mgmt_t;
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device_mgmt_t device_mgmt[ADC_INST_NUM];
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#elif defined(MCU_SAMD51)
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static uint8_t adc_vref_table[] = {
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@ -75,6 +93,20 @@ static uint8_t adc_vref_table[] = {
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#else
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#define DEFAULT_ADC_VREF (3)
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#endif
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#define MAX_ADC_VREF (5)
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typedef struct _device_mgmt_t {
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bool init;
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bool busy;
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int8_t dma_channel;
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mp_obj_t callback;
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mp_obj_t self;
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} device_mgmt_t;
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device_mgmt_t device_mgmt[ADC_INST_NUM] = {
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{ 0, 0, -1, MP_OBJ_NULL, MP_OBJ_NULL},
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{ 0, 0, -1, MP_OBJ_NULL, MP_OBJ_NULL}
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};
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#endif // defined(MCU_SAMD21)
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@ -82,12 +114,12 @@ static uint8_t adc_vref_table[] = {
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#define MICROPY_PY_MACHINE_ADC_CLASS_CONSTANTS
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Adc *const adc_bases[] = ADC_INSTS;
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uint32_t busy_flags = 0;
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bool init_flags[2] = {false, false};
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static void adc_init(machine_adc_obj_t *self);
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uint32_t ch_busy_flags = 0;
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static uint8_t resolution[] = {
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ADC_CTRLB_RESSEL_8BIT_Val, ADC_CTRLB_RESSEL_10BIT_Val, ADC_CTRLB_RESSEL_12BIT_Val
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};
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static void adc_init(machine_adc_obj_t *self);
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extern mp_int_t log2i(mp_int_t num);
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@ -97,11 +129,27 @@ void adc_irq_handler(int dma_channel) {
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#if defined(MCU_SAMD21)
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DMAC->CHID.reg = dma_channel;
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DMAC->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
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DMAC->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL | DMAC_CHINTFLAG_TERR | DMAC_CHINTFLAG_SUSP;
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ADC->EVCTRL.bit.STARTEI = 0;
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device_mgmt[0].busy = 0;
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if (device_mgmt[0].callback != MP_OBJ_NULL) {
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mp_sched_schedule(device_mgmt[0].callback, device_mgmt[0].self);
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}
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#elif defined(MCU_SAMD51)
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DMAC->Channel[dma_channel].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
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DMAC->Channel[dma_channel].CHINTFLAG.reg =
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DMAC_CHINTFLAG_TCMPL | DMAC_CHINTFLAG_TERR | DMAC_CHINTFLAG_SUSP;
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if (device_mgmt[0].dma_channel == dma_channel) {
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device_mgmt[0].busy = 0;
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if (device_mgmt[0].callback != MP_OBJ_NULL) {
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mp_sched_schedule(device_mgmt[0].callback, device_mgmt[0].self);
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}
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} else if (device_mgmt[1].dma_channel == dma_channel) {
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device_mgmt[1].busy = 0;
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if (device_mgmt[1].callback != MP_OBJ_NULL) {
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mp_sched_schedule(device_mgmt[1].callback, device_mgmt[1].self);
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}
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}
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#endif
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}
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@ -114,13 +162,16 @@ static void mp_machine_adc_print(const mp_print_t *print, mp_obj_t self_in, mp_p
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self->adc_config.channel, self->bits, 1 << self->avg, self->vref);
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}
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static mp_obj_t mp_machine_adc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
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enum { ARG_id, ARG_bits, ARG_average, ARG_vref };
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static mp_obj_t adc_obj_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw,
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const mp_obj_t *all_args) {
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enum { ARG_id, ARG_bits, ARG_average, ARG_vref, ARG_callback };
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static const mp_arg_t allowed_args[] = {
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{ MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_OBJ },
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{ MP_QSTR_bits, MP_ARG_INT, {.u_int = DEFAULT_ADC_BITS} },
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{ MP_QSTR_average, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_ADC_AVG} },
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{ MP_QSTR_vref, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_ADC_VREF} },
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{ MP_QSTR_callback, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
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};
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// Parse the arguments.
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@ -129,7 +180,7 @@ static mp_obj_t mp_machine_adc_make_new(const mp_obj_type_t *type, size_t n_args
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// Unpack and check, whether the pin has ADC capability
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int id = mp_hal_get_pin_obj(args[ARG_id].u_obj);
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adc_config_t adc_config = get_adc_config(id, busy_flags);
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adc_config_t adc_config = get_adc_config(id, ch_busy_flags);
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// Now that we have a valid device and channel, create and populate the ADC instance
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machine_adc_obj_t *self = mp_obj_malloc(machine_adc_obj_t, &machine_adc_type);
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@ -145,13 +196,20 @@ static mp_obj_t mp_machine_adc_make_new(const mp_obj_type_t *type, size_t n_args
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self->avg = (avg <= 10 ? avg : 10);
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uint8_t vref = args[ARG_vref].u_int;
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if (0 <= vref && vref < sizeof(adc_vref_table)) {
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if (0 <= vref && vref <= MAX_ADC_VREF) {
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self->vref = vref;
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}
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device_mgmt[adc_config.device].callback = args[ARG_callback].u_obj;
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if (device_mgmt[adc_config.device].callback == mp_const_none) {
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device_mgmt[adc_config.device].callback = MP_OBJ_NULL;
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} else {
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device_mgmt[adc_config.device].self = self;
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}
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// flag the device/channel as being in use.
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busy_flags |= (1 << (self->adc_config.device * 16 + self->adc_config.channel));
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init_flags[self->adc_config.device] = false;
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ch_busy_flags |= (1 << (self->adc_config.device * 16 + self->adc_config.channel));
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self->dma_channel = -1;
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self->tc_index = -1;
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adc_init(self);
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@ -163,6 +221,10 @@ static mp_int_t mp_machine_adc_read_u16(machine_adc_obj_t *self) {
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Adc *adc = adc_bases[self->adc_config.device];
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// Set the reference voltage. Default: external AREFA.
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adc->REFCTRL.reg = adc_vref_table[self->vref];
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if (device_mgmt[self->adc_config.device].busy != 0) {
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mp_raise_OSError(MP_EBUSY);
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}
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// Set Input channel and resolution
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// Select the pin as positive input and gnd as negative input reference, non-diff mode by default
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adc->INPUTCTRL.reg = ADC_INPUTCTRL_MUXNEG_GND | self->adc_config.channel;
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@ -194,6 +256,7 @@ static void machine_adc_read_timed(mp_obj_t self_in, mp_obj_t values, mp_obj_t f
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if (self->dma_channel == -1) {
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self->dma_channel = allocate_dma_channel();
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dma_init();
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dma_register_irq(self->dma_channel, adc_irq_handler);
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}
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if (self->tc_index == -1) {
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self->tc_index = allocate_tc_instance();
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@ -206,8 +269,6 @@ static void machine_adc_read_timed(mp_obj_t self_in, mp_obj_t values, mp_obj_t f
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// Configure DMA for halfword output to the DAC
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#if defined(MCU_SAMD21)
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// dma irq just for SAMD21 to stop the timer based acquisition
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dma_register_irq(self->dma_channel, adc_irq_handler);
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configure_tc(self->tc_index, freq, TC_EVCTRL_OVFEO);
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// Enable APBC clock
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PM->APBCMASK.reg |= PM_APBCMASK_EVSYS;
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@ -241,9 +302,11 @@ static void machine_adc_read_timed(mp_obj_t self_in, mp_obj_t values, mp_obj_t f
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NVIC_EnableIRQ(DMAC_IRQn);
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adc->EVCTRL.bit.STARTEI = 1;
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device_mgmt[0].busy = 1;
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#elif defined(MCU_SAMD51)
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configure_tc(self->tc_index, freq, 0);
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device_mgmt[self->adc_config.device].dma_channel = self->dma_channel;
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// Restart ADC after data has bee read
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adc->DSEQCTRL.reg = ADC_DSEQCTRL_AUTOSTART;
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@ -265,8 +328,16 @@ static void machine_adc_read_timed(mp_obj_t self_in, mp_obj_t values, mp_obj_t f
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DMAC_CHCTRLA_BURSTLEN(DMAC_CHCTRLA_BURSTLEN_SINGLE_Val) |
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DMAC_CHCTRLA_TRIGACT(DMAC_CHCTRLA_TRIGACT_BURST_Val) |
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DMAC_CHCTRLA_TRIGSRC(TC0_DMAC_ID_OVF + 3 * self->tc_index);
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DMAC->Channel[self->dma_channel].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
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DMAC->Channel[self->dma_channel].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
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if (self->dma_channel < 4) {
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NVIC_EnableIRQ(DMAC_0_IRQn + self->dma_channel);
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} else {
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NVIC_EnableIRQ(DMAC_4_IRQn);
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}
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device_mgmt[self->adc_config.device].busy = 1;
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#endif // defined SAMD21 or SAMD51
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}
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@ -277,6 +348,11 @@ static void machine_adc_read_timed(mp_obj_t self_in, mp_obj_t values, mp_obj_t f
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static void mp_machine_adc_deinit(machine_adc_obj_t *self) {
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busy_flags &= ~((1 << (self->adc_config.device * 16 + self->adc_config.channel)));
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if (self->dma_channel >= 0) {
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#if defined(MCU_SAMD51)
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if (self->dma_channel == device_mgmt[self->adc_config.device].dma_channel) {
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device_mgmt[self->adc_config.device].dma_channel = -1;
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}
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#endif
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dac_stop_dma(self->dma_channel, true);
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free_dma_channel(self->dma_channel);
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self->dma_channel = -1;
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@ -288,17 +364,21 @@ static void mp_machine_adc_deinit(machine_adc_obj_t *self) {
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}
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void adc_deinit_all(void) {
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busy_flags = 0;
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init_flags[0] = 0;
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init_flags[1] = 0;
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ch_busy_flags = 0;
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device_mgmt[0].init = 0;
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#if defined(MCU_SAMD51)
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device_mgmt[0].dma_channel = -1;
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device_mgmt[1].init = 0;
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device_mgmt[1].dma_channel = -1;
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#endif
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}
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static void adc_init(machine_adc_obj_t *self) {
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// ADC & clock init is done only once per ADC
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if (init_flags[self->adc_config.device] == false) {
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if (device_mgmt[self->adc_config.device].init == false) {
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Adc *adc = adc_bases[self->adc_config.device];
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init_flags[self->adc_config.device] = true;
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device_mgmt[self->adc_config.device].init = true;
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#if defined(MCU_SAMD21)
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// Configuration SAMD21
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@ -320,7 +400,7 @@ static void adc_init(machine_adc_obj_t *self) {
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// Divide a 48MHz clock by 32 to obtain 1.5 MHz clock to adc
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adc->CTRLB.reg = ADC_CTRLB_PRESCALER_DIV32;
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// Select external AREFA as reference voltage.
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adc->REFCTRL.reg = adc_vref_table[self->vref];
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adc->REFCTRL.reg = self->vref;
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// Average: Accumulate samples and scale them down accordingly
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adc->AVGCTRL.reg = self->avg | ADC_AVGCTRL_ADJRES(self->avg);
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// Enable ADC and wait to be ready
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