kopia lustrzana https://github.com/espressif/esp-idf
132 wiersze
3.8 KiB
C
132 wiersze
3.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <stddef.h>
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#include <assert.h>
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#include "soc/soc.h"
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#include "riscv/interrupt.h"
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#include "soc/interrupt_reg.h"
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#include "riscv/csr.h"
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#include "esp_attr.h"
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#include "riscv/rv_utils.h"
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// TODO: [ESP32C61] IDF-9261, added in verify code, pls check
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// #if SOC_INT_CLIC_SUPPORTED
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// /**
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// * If the target is using the CLIC as the interrupt controller, we have 32 external interrupt lines and 16 internal
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// * lines. Let's consider the internal ones reserved and not mappable to any handler.
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// */
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// #define RV_EXTERNAL_INT_COUNT 32
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// #define RV_EXTERNAL_INT_OFFSET (CLIC_EXT_INTR_NUM_OFFSET)
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// #else // !SOC_INT_CLIC_SUPPORTED
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// /**
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// * In the case of INTC, all the interrupt lines are dedicated to external peripherals, so the offset is 0.
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// * In the case of PLIC, the reserved interrupts are not contiguous, moreover, they are already marked as
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// * unusable by the interrupt allocator, so the offset can also be 0 here.
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// */
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// #define RV_EXTERNAL_INT_COUNT 32
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// #define RV_EXTERNAL_INT_OFFSET 0
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// #endif // SOC_INT_CLIC_SUPPORTED
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typedef struct {
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intr_handler_t handler;
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void *arg;
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} intr_handler_item_t;
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static intr_handler_item_t s_intr_handlers[SOC_CPU_CORES_NUM][RV_EXTERNAL_INT_COUNT];
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static intr_handler_item_t* intr_get_item(int int_no)
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{
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assert_valid_rv_int_num(int_no);
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const uint32_t id = rv_utils_get_core_id();
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return &s_intr_handlers[id][int_no];
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}
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/*************************** Software interrupt dispatcher ***************************/
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void intr_handler_set(int int_no, intr_handler_t fn, void *arg)
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{
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intr_handler_item_t* item = intr_get_item(int_no);
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*item = (intr_handler_item_t) {
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.handler = fn,
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.arg = arg
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};
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}
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intr_handler_t intr_handler_get(int rv_int_num)
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{
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const intr_handler_item_t* item = intr_get_item(rv_int_num);
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return item->handler;
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}
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void *intr_handler_get_arg(int rv_int_num)
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{
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const intr_handler_item_t* item = intr_get_item(rv_int_num);
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return item->arg;
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}
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/* called from vectors.S */
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void _global_interrupt_handler(intptr_t sp, int mcause)
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{
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/* mcause contains the interrupt number that triggered the current interrupt, this number
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* also take into account local/internal interrupt, however, this should not happen in practice,
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* since we never map any peripheral to those. */
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assert(mcause >= RV_EXTERNAL_INT_OFFSET && "Interrupt sources must not be mapped to local interrupts");
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const intr_handler_item_t* item = intr_get_item(mcause - RV_EXTERNAL_INT_OFFSET);
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if (item->handler) {
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(*item->handler)(item->arg);
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}
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}
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// TODO: [ESP32C61] IDF-9261, added in verify code, pls check
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// /*************************** ESP-RV Interrupt Controller ***************************/
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// #if SOC_INT_CLIC_SUPPORTED
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// bool esprv_intc_int_is_vectored(int rv_int_num)
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// {
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// const uint32_t shv = REG_GET_FIELD(CLIC_INT_CTRL_REG(rv_int_num + RV_EXTERNAL_INT_OFFSET), CLIC_INT_ATTR_SHV);
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// return shv != 0;
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// }
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// void esprv_intc_int_set_vectored(int rv_int_num, bool vectored)
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// {
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// REG_SET_FIELD(CLIC_INT_CTRL_REG(rv_int_num + RV_EXTERNAL_INT_OFFSET), CLIC_INT_ATTR_SHV, vectored ? 1 : 0);
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// }
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// #endif // SOC_INT_CLIC_SUPPORTED
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/*************************** Exception names. Used in .gdbinit file. ***************************/
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const char *riscv_excp_names[16] __attribute__((used)) = {
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"misaligned_fetch",
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"fault_fetch",
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"illegal_instruction",
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"breakpoint",
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"misaligned_load",
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"fault_load",
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"misaligned_store",
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"fault_store",
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"user_ecall",
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"supervisor_ecall",
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"hypervisor_ecall",
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"machine_ecall",
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"exec_page_fault",
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"load_page_fault",
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"reserved",
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"store_page_fault"
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};
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