Merge 3bf85ea8fa into c686e23038

fix(wifi): fixed lmacEndFrameExchangeSequence assert issue(Backport v5.1)

See merge request espressif/esp-idf!30316

components/bt/CMakeLists.txt

@@ -756,13 +756,13 @@ if(CONFIG_BT_ENABLED)
         target_link_directories(${COMPONENT_LIB} INTERFACE
                 "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c3_family/esp32s3")
         target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app)
-    elseif(CONFIG_IDF_TARGET_ESP32C2)
+    elseif(CONFIG_IDF_TARGET_ESP32C2 AND CONFIG_BT_CONTROLLER_ENABLED)
         add_prebuilt_library(libble_app "controller/lib_esp32c2/esp32c2-bt-lib/libble_app.a")
         target_link_libraries(${COMPONENT_LIB} PRIVATE libble_app)
-    elseif(CONFIG_IDF_TARGET_ESP32C6)
+    elseif(CONFIG_IDF_TARGET_ESP32C6 AND CONFIG_BT_CONTROLLER_ENABLED)
         add_prebuilt_library(libble_app "controller/lib_esp32c6/esp32c6-bt-lib/libble_app.a")
         target_link_libraries(${COMPONENT_LIB} PRIVATE libble_app)
-    elseif(CONFIG_IDF_TARGET_ESP32H2)
+    elseif(CONFIG_IDF_TARGET_ESP32H2 AND CONFIG_BT_CONTROLLER_ENABLED)
         add_prebuilt_library(libble_app "controller/lib_esp32h2/esp32h2-bt-lib/libble_app.a")
         target_link_libraries(${COMPONENT_LIB} PRIVATE libble_app)
     endif()

components/bt/controller/esp32c2/Kconfig.in

@@ -147,7 +147,7 @@ if BT_LE_EXT_ADV
             Enable this option to start periodic advertisement.
 
     config BT_LE_PERIODIC_ADV_SYNC_TRANSFER
-        bool "Enable Transer Sync Events"
+        bool "Enable Transfer Sync Events"
         depends on BT_LE_ENABLE_PERIODIC_ADV
         default y
         help
@@ -421,6 +421,26 @@ config BT_LE_SLEEP_ENABLE
     help
         Enable BLE sleep
 
+choice BT_LE_LP_CLK_SRC
+    prompt "BLE low power clock source"
+    default BT_LE_LP_CLK_SRC_MAIN_XTAL
+    config BT_LE_LP_CLK_SRC_MAIN_XTAL
+        bool "Use main XTAL as RTC clock source"
+        help
+            User main XTAL as RTC clock source.
+            This option is recommended if external 32.768k XTAL is not available.
+            Using the external 32.768 kHz XTAL will have lower current consumption
+            in light sleep compared to using the main XTAL.
+
+    config BT_LE_LP_CLK_SRC_DEFAULT
+        bool "Use system RTC slow clock source"
+        help
+            Use the same slow clock source as system RTC
+            Using any clock source other than external 32.768 kHz XTAL at pin0 supports only
+            legacy ADV and SCAN due to low clock accuracy.
+
+endchoice
+
 config BT_LE_USE_ESP_TIMER
     bool "Use Esp Timer for callout"
     depends on !BT_NIMBLE_ENABLED
@@ -463,3 +483,17 @@ config BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD
 config BT_LE_RELEASE_IRAM_SUPPORTED
     bool
     default y
+
+config BT_LE_TX_CCA_ENABLED
+    bool "Enable TX CCA feature"
+    default n
+    help
+        Enable CCA feature to cancel sending the packet if the signal power is stronger than CCA threshold.
+
+config BT_LE_CCA_RSSI_THRESH
+    int "CCA RSSI threshold value"
+    depends on BT_LE_TX_CCA_ENABLED
+    range 20 100
+    default 20
+    help
+        Power threshold of CCA in unit of -1 dBm.

components/bt/controller/esp32c2/bt.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -54,12 +54,14 @@
 #include "freertos/task.h"
 
 #include "esp_private/periph_ctrl.h"
+#include "esp_private/esp_clk.h"
 #include "esp_sleep.h"
 
 #include "soc/syscon_reg.h"
 #include "soc/dport_access.h"
 
 #include "hal/efuse_ll.h"
+#include "soc/rtc.h"
 /* Macro definition
  ************************************************************************
  */
@@ -78,6 +80,11 @@
 #define ACL_DATA_MBUF_LEADINGSPCAE    4
 #endif // CONFIG_BT_BLUEDROID_ENABLED
 
+typedef enum ble_rtc_slow_clk_src {
+    BT_SLOW_CLK_SRC_MAIN_XTAL,
+    BT_SLOW_CLK_SRC_32K_XTAL_ON_PIN0,
+} ble_rtc_slow_clk_src_t;
+
 /* Types definition
  ************************************************************************
  */
@@ -487,7 +494,7 @@ IRAM_ATTR void controller_wakeup_cb(void *arg)
     s_ble_active = true;
 }
 
-esp_err_t controller_sleep_init(void)
+esp_err_t controller_sleep_init(ble_rtc_slow_clk_src_t slow_clk_src)
 {
     esp_err_t rc = 0;
 #ifdef CONFIG_BT_LE_SLEEP_ENABLE
@@ -495,7 +502,11 @@ esp_err_t controller_sleep_init(void)
     r_ble_lll_rfmgmt_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0, 500 + BLE_RTC_DELAY_US);
 
 #ifdef CONFIG_PM_ENABLE
-    esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON);
+    if (slow_clk_src == BT_SLOW_CLK_SRC_MAIN_XTAL) {
+        esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON);
+    } else {
+        esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_AUTO);
+    }
 #endif // CONFIG_PM_ENABLE
 
 #endif // CONFIG_BT_LE_SLEEP_ENABLE
@@ -546,37 +557,74 @@ void controller_sleep_deinit(void)
 #endif //CONFIG_PM_ENABLE
 }
 
-void ble_rtc_clk_init(void)
+static void esp_bt_rtc_slow_clk_select(ble_rtc_slow_clk_src_t slow_clk_src)
 {
-    // modem_clkrst_reg
-    // LP_TIMER_SEL_XTAL32K -> 0
-    // LP_TIMER_SEL_XTAL -> 1
-    // LP_TIMER_SEL_8M -> 0
-    // LP_TIMER_SEL_RTC_SLOW -> 0
-    SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
-    SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
-    SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_8M_S);
-    SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S);
-
+    /* Select slow clock source for BT momdule */
+    switch (slow_clk_src) {
+        case BT_SLOW_CLK_SRC_MAIN_XTAL:
+            ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using main XTAL as clock source");
+            SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
+            SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
+            SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_8M_S);
+            SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S);
 #ifdef CONFIG_XTAL_FREQ_26
-    // LP_TIMER_CLK_DIV_NUM -> 130
-    SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 129, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
+            SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 129, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
 #else
-    // LP_TIMER_CLK_DIV_NUM -> 250
-    SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 249, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
+            SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 249, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
 #endif // CONFIG_XTAL_FREQ_26
-
-    // MODEM_CLKRST_ETM_CLK_ACTIVE -> 1
-    // MODEM_CLKRST_ETM_CLK_SEL -> 0
+            break;
+        case BT_SLOW_CLK_SRC_32K_XTAL_ON_PIN0:
+            ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using external 32.768 kHz XTAL as clock source");
+            SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
+            SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
+            SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_8M_S);
+            SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S);
+            SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 0, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
+            break;
+        default:
+            ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported slow clock");
+            assert(0);
+            break;
+    }
     SET_PERI_REG_BITS(MODEM_CLKRST_ETM_CLK_CONF_REG, 1, 1, MODEM_CLKRST_ETM_CLK_ACTIVE_S);
     SET_PERI_REG_BITS(MODEM_CLKRST_ETM_CLK_CONF_REG, 1, 0, MODEM_CLKRST_ETM_CLK_SEL_S);
+}
 
+static ble_rtc_slow_clk_src_t ble_rtc_clk_init(esp_bt_controller_config_t *cfg)
+{
+    ble_rtc_slow_clk_src_t slow_clk_src;
+
+#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
+#ifdef CONFIG_XTAL_FREQ_26
+   cfg->rtc_freq = 40000;
+#else
+   cfg->rtc_freq = 32000;
+#endif // CONFIG_XTAL_FREQ_26
+    slow_clk_src = BT_SLOW_CLK_SRC_MAIN_XTAL;
+#else
+    if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
+        cfg->rtc_freq = 32768;
+        slow_clk_src = BT_SLOW_CLK_SRC_32K_XTAL_ON_PIN0;
+    } else {
+        ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
+#ifdef CONFIG_XTAL_FREQ_26
+        cfg->rtc_freq = 40000;
+#else
+        cfg->rtc_freq = 32000;
+#endif // CONFIG_XTAL_FREQ_26
+        slow_clk_src = BT_SLOW_CLK_SRC_MAIN_XTAL;
+    }
+#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
+    esp_bt_rtc_slow_clk_select(slow_clk_src);
+    return slow_clk_src;
 }
 
 esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
 {
     esp_err_t ret = ESP_OK;
     ble_npl_count_info_t npl_info;
+    ble_rtc_slow_clk_src_t rtc_clk_src;
+
     memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
     if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) {
         ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
@@ -588,7 +636,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
         return ESP_ERR_INVALID_ARG;
     }
 
-    ble_rtc_clk_init();
+    rtc_clk_src = ble_rtc_clk_init(cfg);
 
     ret = esp_register_ext_funcs(&ext_funcs_ro);
     if (ret != ESP_OK) {
@@ -644,7 +692,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
 #if CONFIG_SW_COEXIST_ENABLE
     coex_init();
 #endif
-
     ret = ble_controller_init(cfg);
     if (ret != ESP_OK) {
         ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret);
@@ -675,7 +722,7 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
     }
 #endif // CONFIG_BT_CONTROLLER_LOG_ENABLED
 
-    ret = controller_sleep_init();
+    ret = controller_sleep_init(rtc_clk_src);
     if (ret != ESP_OK) {
         ESP_LOGW(NIMBLE_PORT_LOG_TAG, "controller_sleep_init failed %d", ret);
         goto free_controller;

components/bt/controller/esp32c2/esp_bt_cfg.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */

components/bt/controller/esp32c6/Kconfig.in

@@ -147,7 +147,7 @@ if BT_LE_EXT_ADV
             Enable this option to start periodic advertisement.
 
     config BT_LE_PERIODIC_ADV_SYNC_TRANSFER
-        bool "Enable Transer Sync Events"
+        bool "Enable Transfer Sync Events"
         depends on BT_LE_ENABLE_PERIODIC_ADV
         default y
         help
@@ -562,3 +562,17 @@ config BT_LE_SCAN_DUPL_CACHE_REFRESH_PERIOD
 config BT_LE_MSYS_INIT_IN_CONTROLLER
     bool "Msys Mbuf Init in Controller"
     default y
+
+config BT_LE_TX_CCA_ENABLED
+    bool "Enable TX CCA feature"
+    default n
+    help
+        Enable CCA feature to cancel sending the packet if the signal power is stronger than CCA threshold.
+
+config BT_LE_CCA_RSSI_THRESH
+    int "CCA RSSI threshold value"
+    depends on BT_LE_TX_CCA_ENABLED
+    range 20 100
+    default 20
+    help
+        Power threshold of CCA in unit of -1 dBm.

components/bt/controller/esp32c6/bt.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -780,13 +780,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
     coex_init();
 #endif // CONFIG_SW_COEXIST_ENABLE
 
-    ret = ble_controller_init(cfg);
-    if (ret != ESP_OK) {
-        ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret);
-        goto modem_deint;
-    }
-
-    ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version());
 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
     interface_func_t bt_controller_log_interface;
     bt_controller_log_interface = esp_bt_controller_log_interface;
@@ -804,10 +797,16 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
 #endif // CONFIG_BT_CONTROLLER_LOG_DUMP
     if (ret != ESP_OK) {
         ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_log_init failed %d", ret);
-        goto controller_init_err;
+        goto modem_deint;
     }
 #endif // CONFIG_BT_CONTROLLER_LOG_ENABLED
+    ret = ble_controller_init(cfg);
+    if (ret != ESP_OK) {
+        ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret);
+        goto modem_deint;
+    }
 
+    ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version());
     esp_ble_change_rtc_freq(slow_clk_freq);
 
     ble_controller_scan_duplicate_config();
@@ -835,13 +834,12 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
 
 free_controller:
     controller_sleep_deinit();
-#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
-controller_init_err:
-    r_ble_log_deinit_async();
-#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
     os_msys_deinit();
     ble_controller_deinit();
 modem_deint:
+#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
+    r_ble_log_deinit_async();
+#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
     esp_phy_modem_deinit();
     modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
     modem_clock_module_disable(PERIPH_BT_MODULE);
@@ -872,10 +870,10 @@ esp_err_t esp_bt_controller_deinit(void)
     modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
     modem_clock_module_disable(PERIPH_BT_MODULE);
 
+    ble_controller_deinit();
 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
     r_ble_log_deinit_async();
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
-    ble_controller_deinit();
 
 #if CONFIG_BT_NIMBLE_ENABLED
     /* De-initialize default event queue */

components/bt/controller/esp32h2/Kconfig.in

@@ -147,7 +147,7 @@ if BT_LE_EXT_ADV
             Enable this option to start periodic advertisement.
 
     config BT_LE_PERIODIC_ADV_SYNC_TRANSFER
-        bool "Enable Transer Sync Events"
+        bool "Enable Transfer Sync Events"
         depends on BT_LE_ENABLE_PERIODIC_ADV
         default y
         help
@@ -554,3 +554,17 @@ config BT_LE_SCAN_DUPL_CACHE_REFRESH_PERIOD
 config BT_LE_MSYS_INIT_IN_CONTROLLER
     bool
     default y
+
+config BT_LE_TX_CCA_ENABLED
+    bool "Enable TX CCA feature"
+    default n
+    help
+        Enable CCA feature to cancel sending the packet if the signal power is stronger than CCA threshold.
+
+config BT_LE_CCA_RSSI_THRESH
+    int "CCA RSSI threshold value"
+    depends on BT_LE_TX_CCA_ENABLED
+    range 20 100
+    default 20
+    help
+        Power threshold of CCA in unit of -1 dBm.

components/bt/controller/esp32h2/bt.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -752,14 +752,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
 #if CONFIG_SW_COEXIST_ENABLE
     coex_init();
 #endif // CONFIG_SW_COEXIST_ENABLE
-
-    ret = ble_controller_init(cfg);
-    if (ret != ESP_OK) {
-        ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret);
-        goto modem_deint;
-    }
-
-    ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version());
 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
     interface_func_t bt_controller_log_interface;
     bt_controller_log_interface = esp_bt_controller_log_interface;
@@ -777,10 +769,18 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
 #endif // CONFIG_BT_CONTROLLER_LOG_DUMP
     if (ret != ESP_OK) {
         ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_log_init failed %d", ret);
-        goto controller_init_err;
+        goto modem_deint;
     }
 #endif // CONFIG_BT_CONTROLLER_LOG_ENABLED
 
+    ret = ble_controller_init(cfg);
+    if (ret != ESP_OK) {
+        ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret);
+        goto modem_deint;
+    }
+
+    ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version());
+
     esp_ble_change_rtc_freq(slow_clk_freq);
 
     ble_controller_scan_duplicate_config();
@@ -809,13 +809,12 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
 
 free_controller:
     controller_sleep_deinit();
-#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
-controller_init_err:
-    r_ble_log_deinit_async();
-#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
     os_msys_deinit();
     ble_controller_deinit();
 modem_deint:
+#if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
+    r_ble_log_deinit_async();
+#endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
     modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
     modem_clock_module_disable(PERIPH_BT_MODULE);
 #if CONFIG_BT_NIMBLE_ENABLED
@@ -844,10 +843,10 @@ esp_err_t esp_bt_controller_deinit(void)
     modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
     modem_clock_module_disable(PERIPH_BT_MODULE);
 
+    ble_controller_deinit();
 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
     r_ble_log_deinit_async();
 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
-    ble_controller_deinit();
 
 #if CONFIG_BT_NIMBLE_ENABLED
     /* De-initialize default event queue */

components/bt/controller/lib_esp32c2/esp32c2-bt-lib

@@ -1 +1 @@
-Subproject commit cb051020d238fb6e2d1e5f4f23a9678912a1fe28
+Subproject commit ea4595a5630326d428ee3457df654e1840b5e101

components/bt/controller/lib_esp32c6/esp32c6-bt-lib

@@ -1 +1 @@
-Subproject commit 9c0690805642cd9653e4c9acff31de59a670b225
+Subproject commit 0af472c6f95858e638565dad19a79fe47de1fff2

components/bt/controller/lib_esp32h2/esp32h2-bt-lib

@@ -1 +1 @@
-Subproject commit 18a00c3fe8e35cdfef280c9465692ebc74e4e1ca
+Subproject commit 70612d08d1ff94dfb5da99d6a68aa4032cd63276

components/bt/esp_ble_mesh/README.md

@@ -15,7 +15,7 @@ The ESP-BLE-MESH networking enables many-to-many (m:m) device communications and
 - [FAQ](https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/esp_ble_mesh/ble_mesh_faq.html)
 - [API Reference](https://docs.espressif.com/projects/esp-idf/en/latest/api-reference/bluetooth/ble_mesh.html)
 
- 
-### [ESP-BLE-MESH Examples](https://github.com/espressif/esp-idf/tree/master/examples/bluetooth/esp_ble_mesh)
+
+### [ESP-BLE-MESH Examples](../../../examples/bluetooth/esp_ble_mesh)
 
 - Refer to **ESP-BLE-MESH Examples** of [Getting Started](https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/esp_ble_mesh/index.html##getting-started-with-ble-mesh) for the tutorials of ESP BLE Mesh examples.

components/bt/esp_ble_mesh/mesh_core/net.c

@@ -1432,9 +1432,7 @@ static bool ignore_net_msg(uint16_t src, uint16_t dst)
     }
 
     if (IS_ENABLED(CONFIG_BLE_MESH_PROVISIONER) &&
-        bt_mesh_is_provisioner_en() &&
-        BLE_MESH_ADDR_IS_UNICAST(dst) &&
-        bt_mesh_elem_find(dst)) {
+        bt_mesh_is_provisioner_en()) {
         /* If the destination address of the message is the element
          * address of Provisioner, but Provisioner fails to find the
          * node in its provisioning database, then this message will

components/driver/gptimer/gptimer.c

@@ -262,6 +262,9 @@ esp_err_t gptimer_set_alarm_action(gptimer_handle_t timer, const gptimer_alarm_c
 {
     ESP_RETURN_ON_FALSE_ISR(timer, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
     if (config) {
+#if CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM
+        ESP_RETURN_ON_FALSE_ISR(esp_ptr_internal(config), ESP_ERR_INVALID_ARG, TAG, "alarm config struct not in internal RAM");
+#endif
         // When auto_reload is enabled, alarm_count should not be equal to reload_count
         bool valid_auto_reload = !config->flags.auto_reload_on_alarm || config->alarm_count != config->reload_count;
         ESP_RETURN_ON_FALSE_ISR(valid_auto_reload, ESP_ERR_INVALID_ARG, TAG, "reload count can't equal to alarm count");

components/driver/i2c/i2c.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -1503,7 +1503,7 @@ esp_err_t i2c_master_cmd_begin(i2c_port_t i2c_num, i2c_cmd_handle_t cmd_handle,
     // Sometimes when the FSM get stuck, the ACK_ERR interrupt will occur endlessly until we reset the FSM and clear bus.
     esp_err_t ret = ESP_FAIL;
     i2c_obj_t *p_i2c = p_i2c_obj[i2c_num];
-    TickType_t ticks_start = xTaskGetTickCount();
+    const TickType_t ticks_start = xTaskGetTickCount();
     portBASE_TYPE res = xSemaphoreTake(p_i2c->cmd_mux, ticks_to_wait);
     if (res == pdFALSE) {
         return ESP_ERR_TIMEOUT;
@@ -1543,13 +1543,15 @@ esp_err_t i2c_master_cmd_begin(i2c_port_t i2c_num, i2c_cmd_handle_t cmd_handle,
     i2c_cmd_evt_t evt;
     while (1) {
         TickType_t wait_time = xTaskGetTickCount();
-        if (wait_time - ticks_start > ticks_to_wait) { // out of time
-            wait_time = I2C_CMD_ALIVE_INTERVAL_TICK;
+        const TickType_t elapsed = wait_time - ticks_start;
+        if (elapsed >= ticks_to_wait) { // out of time
+            /* Before triggering a timeout, empty the queue by giving a wait_time of 0:
+             * - if the queue is empty, `pdFALSE` will be returned and the loop will be exited
+             * - if the queue is not empty, we will pop an element and come back here again
+             */
+            wait_time = 0;
         } else {
-            wait_time = ticks_to_wait - (wait_time - ticks_start);
-            if (wait_time < I2C_CMD_ALIVE_INTERVAL_TICK) {
-                wait_time = I2C_CMD_ALIVE_INTERVAL_TICK;
-            }
+            wait_time = MIN(ticks_to_wait - elapsed, I2C_CMD_ALIVE_INTERVAL_TICK);
         }
         // In master mode, since we don't have an interrupt to detective bus error or FSM state, what we do here is to make
         // sure the interrupt mechanism for master mode is still working.

components/esp_http_client/esp_http_client.c

@@ -233,6 +233,7 @@ static int http_on_header_event(esp_http_client_handle_t client)
 static int http_on_header_field(http_parser *parser, const char *at, size_t length)
 {
     esp_http_client_t *client = parser->data;
+    http_on_header_event(client);
     http_utils_append_string(&client->current_header_key, at, length);
 
     return 0;
@@ -253,7 +254,6 @@ static int http_on_header_value(http_parser *parser, const char *at, size_t leng
         http_utils_append_string(&client->auth_header, at, length);
     }
     http_utils_append_string(&client->current_header_value, at, length);
-    http_on_header_event(client);
     return 0;
 }
 

components/esp_hw_support/include/esp_private/esp_sleep_internal.h

@@ -7,6 +7,7 @@
 #pragma once
 #include <stdbool.h>
 #include "sdkconfig.h"
+#include "esp_sleep.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -47,6 +48,29 @@ void esp_sleep_enable_adc_tsens_monitor(bool enable);
 void esp_sleep_isolate_digital_gpio(void);
 #endif
 
+/**
+  * Register a callback to be called from the deep sleep prepare for maintain the PHY state
+  *          CPU is equal to min_freq_mhz (if DFS is enabled) when running this callback,
+  *          and PLL clock is exists)
+  *
+  * @warning deepsleep PHY callbacks should without parameters, and MUST NOT,
+  *          UNDER ANY CIRCUMSTANCES, CALL A FUNCTION THAT MIGHT BLOCK.
+  *
+  * @param new_dslp_cb     Callback to be called to close PHY related modules
+  *
+  * @return
+  *     - ESP_OK:         PHY callback registered to the phy modules deepsleep prepare
+  *     - ESP_ERR_NO_MEM: No more hook space for register the callback
+  */
+esp_err_t esp_deep_sleep_register_phy_hook(esp_deep_sleep_cb_t new_dslp_cb);
+
+/**
+  * @brief Unregister an PHY deepsleep callback
+  *
+  * @param old_dslp_cb     Callback to be unregistered
+  */
+void esp_deep_sleep_deregister_phy_hook(esp_deep_sleep_cb_t old_dslp_cb);
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hw_support/port/esp32/rtc_init.c

@@ -28,6 +28,7 @@ void rtc_init(rtc_config_t cfg)
      * No worry about the power consumption, Because modem Force PD will be set at the end of this function.
      */
     CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
+    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
 
     CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU | RTC_CNTL_TXRF_I2C_PU |
             RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU);

components/esp_hw_support/port/esp32/rtc_sleep.c

@@ -183,7 +183,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
     }
 
     if (cfg.modem_pd_en) {
-        REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | RTC_CNTL_WIFI_FORCE_ISO);
+        REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
         REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
         SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
     } else {

components/esp_hw_support/port/esp32c3/rtc_init.c

@@ -40,6 +40,7 @@ void rtc_init(rtc_config_t cfg)
      * No worry about the power consumption, Because modem Force PD will be set at the end of this function.
      */
     CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
+    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
 
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
@@ -263,7 +264,7 @@ uint32_t get_rtc_dbias_by_efuse(uint8_t chip_version, uint32_t dig_dbias)
 static void set_rtc_dig_dbias()
 {
     /*
-    1. a reasonable dig_dbias which by scaning pvt to make 160 CPU run successful stored in efuse;
+    1. a reasonable dig_dbias which by scanning pvt to make 160 CPU run successful stored in efuse;
     2. also we store some value in efuse, include:
         k_rtc_ldo (slope of rtc voltage & rtc_dbias);
         k_dig_ldo (slope of digital voltage & digital_dbias);

components/esp_hw_support/port/esp32c3/rtc_sleep.c

@@ -174,14 +174,14 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
         rtc_sleep_pu(pu_cfg);
     }
     if (cfg.wifi_pd_en) {
-        REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | RTC_CNTL_WIFI_FORCE_ISO);
+        REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
         REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
         SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
     } else {
         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
     }
     if (cfg.bt_pd_en) {
-        REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO | RTC_CNTL_BT_FORCE_ISO);
+        REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO);
         REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU);
         SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN);
     } else {

components/esp_hw_support/port/esp32c6/cpu_region_protect.c

@@ -29,29 +29,6 @@
 #define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) (((addr) + (SOC_MMU_PAGE_SIZE) - 1) & ~((SOC_MMU_PAGE_SIZE) - 1))
 #define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr)  ((addr) & ~((SOC_MMU_PAGE_SIZE) - 1))
 
-/**
- * @brief Generate the PMP address field value for PMPCFG.A == NAPOT
- *
- * NOTE: Here, (end-start) must be a power of 2 size and start must
- * be aligned to this size. This API returns UINT32_MAX on failing
- * these conditions, which when plugged into the PMP entry registers
- * does nothing. This skips the corresponding region's protection.
- *
- * @param start      Region starting address
- * @param end        Region ending address
- *
- * @return uint32_t PMP address field value
- */
-static inline uint32_t pmpaddr_napot(uint32_t start, uint32_t end)
-{
-    uint32_t size = end - start;
-    if ((size & (size - 1)) || (start % size)) {
-        return UINT32_MAX;
-    }
-
-    return start | ((size - 1) >> 1);
-}
-
 static void esp_cpu_configure_invalid_regions(void)
 {
     const unsigned PMA_NONE                            = PMA_L | PMA_EN;
@@ -180,22 +157,18 @@ void esp_cpu_configure_region_protection(void)
 
 #if CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT && !BOOTLOADER_BUILD
     extern int _instruction_reserved_end;
-    extern int _rodata_reserved_start;
     extern int _rodata_reserved_end;
 
     const uint32_t irom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_instruction_reserved_end));
-    const uint32_t drom_resv_start = ALIGN_DOWN_TO_MMU_PAGE_SIZE((uint32_t)(&_rodata_reserved_start));
     const uint32_t drom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_rodata_reserved_end));
 
-    // 4. I_Cache (flash)
+    // 4. I_Cache / D_Cache (flash)
     PMP_ENTRY_CFG_RESET(8);
-    const uint32_t pmpaddr8 = pmpaddr_napot(SOC_IROM_LOW, irom_resv_end);
-    PMP_ENTRY_SET(8, pmpaddr8, PMP_NAPOT | RX);
-
-    // 5. D_Cache (flash)
     PMP_ENTRY_CFG_RESET(9);
-    const uint32_t pmpaddr9 = pmpaddr_napot(drom_resv_start, drom_resv_end);
-    PMP_ENTRY_SET(9, pmpaddr9, PMP_NAPOT | R);
+    PMP_ENTRY_CFG_RESET(10);
+    PMP_ENTRY_SET(8, SOC_IROM_LOW, NONE);
+    PMP_ENTRY_SET(9, irom_resv_end, PMP_TOR | RX);
+    PMP_ENTRY_SET(10, drom_resv_end, PMP_TOR | R);
 #else
     // 4. I_Cache / D_Cache (flash)
     const uint32_t pmpaddr8 = PMPADDR_NAPOT(SOC_IROM_LOW, SOC_IROM_HIGH);
@@ -209,29 +182,29 @@ void esp_cpu_configure_region_protection(void)
     /* Reset the corresponding PMP config because PMP_ENTRY_SET only sets the given bits
      * Bootloader might have given extra permissions and those won't be cleared
      */
-    PMP_ENTRY_CFG_RESET(10);
     PMP_ENTRY_CFG_RESET(11);
     PMP_ENTRY_CFG_RESET(12);
     PMP_ENTRY_CFG_RESET(13);
-    PMP_ENTRY_SET(10, SOC_RTC_IRAM_LOW, NONE);
+    PMP_ENTRY_CFG_RESET(14);
+    PMP_ENTRY_SET(11, SOC_RTC_IRAM_LOW, NONE);
 #if CONFIG_ULP_COPROC_RESERVE_MEM
     // First part of LP mem is reserved for coprocessor
-    PMP_ENTRY_SET(11, SOC_RTC_IRAM_LOW + CONFIG_ULP_COPROC_RESERVE_MEM, PMP_TOR | RW);
+    PMP_ENTRY_SET(12, SOC_RTC_IRAM_LOW + CONFIG_ULP_COPROC_RESERVE_MEM, PMP_TOR | RW);
 #else // CONFIG_ULP_COPROC_RESERVE_MEM
     // Repeat same previous entry, to ensure next entry has correct base address (TOR)
-    PMP_ENTRY_SET(11, SOC_RTC_IRAM_LOW, NONE);
+    PMP_ENTRY_SET(12, SOC_RTC_IRAM_LOW, NONE);
 #endif // !CONFIG_ULP_COPROC_RESERVE_MEM
-    PMP_ENTRY_SET(12, (int)&_rtc_text_end, PMP_TOR | RX);
-    PMP_ENTRY_SET(13, SOC_RTC_IRAM_HIGH, PMP_TOR | RW);
+    PMP_ENTRY_SET(13, (int)&_rtc_text_end, PMP_TOR | RX);
+    PMP_ENTRY_SET(14, SOC_RTC_IRAM_HIGH, PMP_TOR | RW);
 #else
-    const uint32_t pmpaddr10 = PMPADDR_NAPOT(SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH);
-    PMP_ENTRY_SET(10, pmpaddr10, PMP_NAPOT | CONDITIONAL_RWX);
+    const uint32_t pmpaddr11 = PMPADDR_NAPOT(SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH);
+    PMP_ENTRY_SET(11, pmpaddr11, PMP_NAPOT | CONDITIONAL_RWX);
     _Static_assert(SOC_RTC_IRAM_LOW < SOC_RTC_IRAM_HIGH, "Invalid RTC IRAM region");
 #endif
 
 
     // 7. Peripheral addresses
-    const uint32_t pmpaddr14 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH);
-    PMP_ENTRY_SET(14, pmpaddr14, PMP_NAPOT | RW);
+    const uint32_t pmpaddr15 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH);
+    PMP_ENTRY_SET(15, pmpaddr15, PMP_NAPOT | RW);
     _Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region");
 }

components/esp_hw_support/port/esp32c6/pmu_init.c

@@ -137,22 +137,22 @@ static inline void pmu_power_domain_force_default(pmu_context_t *ctx)
     };
 
     for (uint8_t idx = 0; idx < (sizeof(pmu_hp_domains) / sizeof(pmu_hp_power_domain_t)); idx++) {
-        pmu_ll_hp_set_power_force_reset     (ctx->hal->dev, pmu_hp_domains[idx], false);
-        pmu_ll_hp_set_power_force_isolate   (ctx->hal->dev, pmu_hp_domains[idx], false);
         pmu_ll_hp_set_power_force_power_up  (ctx->hal->dev, pmu_hp_domains[idx], false);
         pmu_ll_hp_set_power_force_no_reset  (ctx->hal->dev, pmu_hp_domains[idx], false);
         pmu_ll_hp_set_power_force_no_isolate(ctx->hal->dev, pmu_hp_domains[idx], false);
         pmu_ll_hp_set_power_force_power_down(ctx->hal->dev, pmu_hp_domains[idx], false);
+        pmu_ll_hp_set_power_force_isolate   (ctx->hal->dev, pmu_hp_domains[idx], false);
+        pmu_ll_hp_set_power_force_reset     (ctx->hal->dev, pmu_hp_domains[idx], false);
     }
     /* Isolate all memory banks while sleeping, avoid memory leakage current */
     pmu_ll_hp_set_memory_no_isolate     (ctx->hal->dev, 0);
 
-    pmu_ll_lp_set_power_force_reset     (ctx->hal->dev, false);
-    pmu_ll_lp_set_power_force_isolate   (ctx->hal->dev, false);
     pmu_ll_lp_set_power_force_power_up  (ctx->hal->dev, false);
     pmu_ll_lp_set_power_force_no_reset  (ctx->hal->dev, false);
     pmu_ll_lp_set_power_force_no_isolate(ctx->hal->dev, false);
     pmu_ll_lp_set_power_force_power_down(ctx->hal->dev, false);
+    pmu_ll_lp_set_power_force_isolate   (ctx->hal->dev, false);
+    pmu_ll_lp_set_power_force_reset     (ctx->hal->dev, false);
 }
 
 static inline void pmu_hp_system_param_default(pmu_hp_mode_t mode, pmu_hp_system_param_t *param)

components/esp_hw_support/port/esp32h2/cpu_region_protect.c

@@ -29,29 +29,6 @@
 #define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) (((addr) + (SOC_MMU_PAGE_SIZE) - 1) & ~((SOC_MMU_PAGE_SIZE) - 1))
 #define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr)  ((addr) & ~((SOC_MMU_PAGE_SIZE) - 1))
 
-/**
- * @brief Generate the PMP address field value for PMPCFG.A == NAPOT
- *
- * NOTE: Here, (end-start) must be a power of 2 size and start must
- * be aligned to this size. This API returns UINT32_MAX on failing
- * these conditions, which when plugged into the PMP entry registers
- * does nothing. This skips the corresponding region's protection.
- *
- * @param start      Region starting address
- * @param end        Region ending address
- *
- * @return uint32_t PMP address field value
- */
-static inline uint32_t pmpaddr_napot(uint32_t start, uint32_t end)
-{
-    uint32_t size = end - start;
-    if ((size & (size - 1)) || (start % size)) {
-        return UINT32_MAX;
-    }
-
-    return start | ((size - 1) >> 1);
-}
-
 static void esp_cpu_configure_invalid_regions(void)
 {
     const unsigned PMA_NONE                            = PMA_L | PMA_EN;
@@ -180,22 +157,18 @@ void esp_cpu_configure_region_protection(void)
 
 #if CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT && !BOOTLOADER_BUILD
     extern int _instruction_reserved_end;
-    extern int _rodata_reserved_start;
     extern int _rodata_reserved_end;
 
     const uint32_t irom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_instruction_reserved_end));
-    const uint32_t drom_resv_start = ALIGN_DOWN_TO_MMU_PAGE_SIZE((uint32_t)(&_rodata_reserved_start));
     const uint32_t drom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_rodata_reserved_end));
 
-    // 4. I_Cache (flash)
+    // 4. I_Cache / D_Cache (flash)
     PMP_ENTRY_CFG_RESET(8);
-    const uint32_t pmpaddr8 = pmpaddr_napot(SOC_IROM_LOW, irom_resv_end);
-    PMP_ENTRY_SET(8, pmpaddr8, PMP_NAPOT | RX);
-
-    // 5. D_Cache (flash)
     PMP_ENTRY_CFG_RESET(9);
-    const uint32_t pmpaddr9 = pmpaddr_napot(drom_resv_start, drom_resv_end);
-    PMP_ENTRY_SET(9, pmpaddr9, PMP_NAPOT | R);
+    PMP_ENTRY_CFG_RESET(10);
+    PMP_ENTRY_SET(8, SOC_IROM_LOW, NONE);
+    PMP_ENTRY_SET(9, irom_resv_end, PMP_TOR | RX);
+    PMP_ENTRY_SET(10, drom_resv_end, PMP_TOR | R);
 #else
     // 4. I_Cache / D_Cache (flash)
     const uint32_t pmpaddr8 = PMPADDR_NAPOT(SOC_IROM_LOW, SOC_IROM_HIGH);
@@ -209,20 +182,20 @@ void esp_cpu_configure_region_protection(void)
     /* Reset the corresponding PMP config because PMP_ENTRY_SET only sets the given bits
      * Bootloader might have given extra permissions and those won't be cleared
      */
-    PMP_ENTRY_CFG_RESET(10);
     PMP_ENTRY_CFG_RESET(11);
     PMP_ENTRY_CFG_RESET(12);
-    PMP_ENTRY_SET(10, SOC_RTC_IRAM_LOW, NONE);
-    PMP_ENTRY_SET(11, (int)&_rtc_text_end, PMP_TOR | RX);
-    PMP_ENTRY_SET(12, SOC_RTC_IRAM_HIGH, PMP_TOR | RW);
+    PMP_ENTRY_CFG_RESET(13);
+    PMP_ENTRY_SET(11, SOC_RTC_IRAM_LOW, NONE);
+    PMP_ENTRY_SET(12, (int)&_rtc_text_end, PMP_TOR | RX);
+    PMP_ENTRY_SET(13, SOC_RTC_IRAM_HIGH, PMP_TOR | RW);
 #else
-    const uint32_t pmpaddr10 = PMPADDR_NAPOT(SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH);
-    PMP_ENTRY_SET(10, pmpaddr10, PMP_NAPOT | CONDITIONAL_RWX);
+    const uint32_t pmpaddr11 = PMPADDR_NAPOT(SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH);
+    PMP_ENTRY_SET(11, pmpaddr11, PMP_NAPOT | CONDITIONAL_RWX);
     _Static_assert(SOC_RTC_IRAM_LOW < SOC_RTC_IRAM_HIGH, "Invalid RTC IRAM region");
 #endif
 
     // 7. Peripheral addresses
-    const uint32_t pmpaddr13 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH);
-    PMP_ENTRY_SET(13, pmpaddr13, PMP_NAPOT | RW);
+    const uint32_t pmpaddr14 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH);
+    PMP_ENTRY_SET(14, pmpaddr14, PMP_NAPOT | RW);
     _Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region");
 }

components/esp_hw_support/port/esp32h2/pmu_init.c

@@ -136,23 +136,23 @@ static inline void pmu_power_domain_force_default(pmu_context_t *ctx)
     };
 
     for (uint8_t idx = 0; idx < (sizeof(pmu_hp_domains) / sizeof(pmu_hp_power_domain_t)); idx++) {
-        pmu_ll_hp_set_power_force_reset     (ctx->hal->dev, pmu_hp_domains[idx], false);
-        pmu_ll_hp_set_power_force_isolate   (ctx->hal->dev, pmu_hp_domains[idx], false);
         pmu_ll_hp_set_power_force_power_up  (ctx->hal->dev, pmu_hp_domains[idx], false);
         pmu_ll_hp_set_power_force_no_reset  (ctx->hal->dev, pmu_hp_domains[idx], false);
         pmu_ll_hp_set_power_force_no_isolate(ctx->hal->dev, pmu_hp_domains[idx], false);
         pmu_ll_hp_set_power_force_power_down(ctx->hal->dev, pmu_hp_domains[idx], false);
+        pmu_ll_hp_set_power_force_isolate   (ctx->hal->dev, pmu_hp_domains[idx], false);
+        pmu_ll_hp_set_power_force_reset     (ctx->hal->dev, pmu_hp_domains[idx], false);
     }
 
     /* Isolate all memory banks while sleeping, avoid memory leakage current */
     pmu_ll_hp_set_memory_no_isolate     (ctx->hal->dev, 0);
 
-    pmu_ll_lp_set_power_force_reset     (ctx->hal->dev, false);
-    pmu_ll_lp_set_power_force_isolate   (ctx->hal->dev, false);
     pmu_ll_lp_set_power_force_power_up  (ctx->hal->dev, false);
     pmu_ll_lp_set_power_force_no_reset  (ctx->hal->dev, false);
     pmu_ll_lp_set_power_force_no_isolate(ctx->hal->dev, false);
     pmu_ll_lp_set_power_force_power_down(ctx->hal->dev, false);
+    pmu_ll_lp_set_power_force_isolate   (ctx->hal->dev, false);
+    pmu_ll_lp_set_power_force_reset     (ctx->hal->dev, false);
 }
 
 static inline void pmu_hp_system_param_default(pmu_hp_mode_t mode, pmu_hp_system_param_t *param)

components/esp_hw_support/port/esp32s2/rtc_init.c

@@ -37,6 +37,7 @@ void rtc_init(rtc_config_t cfg)
      * No worry about the power consumption, Because modem Force PD will be set at the end of this function.
      */
     CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
+    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
 
     CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU);
     REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait);
@@ -46,7 +47,7 @@ void rtc_init(rtc_config_t cfg)
     // set shortest possible sleep time limit
     REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, RTC_CNTL_MIN_SLP_VAL_MIN);
 
-    /* This power domian removed
+    /* This power domain removed
     * set rom&ram timer
     * REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_POWERUP_TIMER, ROM_RAM_POWERUP_CYCLES);
     * REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_WAIT_TIMER, ROM_RAM_WAIT_CYCLES);

components/esp_hw_support/port/esp32s2/rtc_sleep.c

@@ -200,7 +200,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
     }
 
     if (cfg.wifi_pd_en) {
-        REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | RTC_CNTL_WIFI_FORCE_ISO);
+        REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
         REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
         SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
     } else {

components/esp_hw_support/port/esp32s3/rtc_init.c

@@ -54,6 +54,7 @@ void rtc_init(rtc_config_t cfg)
      * No worry about the power consumption, Because modem Force PD will be set at the end of this function.
      */
     CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
+    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
 
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
@@ -382,7 +383,7 @@ static uint32_t get_dig1v3_dbias_by_efuse(uint8_t pvt_scheme_ver)
 static void rtc_set_stored_dbias(void)
 {
     /*
-    1. a reasonable dig_dbias which by scaning pvt to make 240 CPU run successful stored in efuse;
+    1. a reasonable dig_dbias which by scanning pvt to make 240 CPU run successful stored in efuse;
     2. also we store some value in efuse, include:
         k_rtc_ldo (slope of rtc voltage & rtc_dbias);
         k_dig_ldo (slope of digital voltage & digital_dbias);

components/esp_hw_support/port/esp32s3/rtc_sleep.c

@@ -178,7 +178,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
     }
 
     if (cfg.modem_pd_en) {
-        REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | RTC_CNTL_WIFI_FORCE_ISO);
+        REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
         REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
         SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
     } else {

components/esp_hw_support/sleep_modes.c

@@ -173,7 +173,8 @@
 
 #define MAX_DSLP_HOOKS      3
 
-static esp_deep_sleep_cb_t s_dslp_cb[MAX_DSLP_HOOKS]={0};
+static esp_deep_sleep_cb_t s_dslp_cb[MAX_DSLP_HOOKS] = {0};
+static esp_deep_sleep_cb_t s_dslp_phy_cb[MAX_DSLP_HOOKS] = {0};
 
 /**
  * Internal structure which holds all requested deep sleep parameters
@@ -390,12 +391,12 @@ esp_err_t esp_deep_sleep_try(uint64_t time_in_us)
     return esp_deep_sleep_try_to_start();
 }
 
-esp_err_t esp_deep_sleep_register_hook(esp_deep_sleep_cb_t new_dslp_cb)
+static esp_err_t s_sleep_hook_register(esp_deep_sleep_cb_t new_cb, esp_deep_sleep_cb_t s_cb_array[MAX_DSLP_HOOKS])
 {
     portENTER_CRITICAL(&spinlock_rtc_deep_sleep);
-    for(int n = 0; n < MAX_DSLP_HOOKS; n++){
-        if (s_dslp_cb[n]==NULL || s_dslp_cb[n]==new_dslp_cb) {
-            s_dslp_cb[n]=new_dslp_cb;
+    for (int n = 0; n < MAX_DSLP_HOOKS; n++) {
+        if (s_cb_array[n]==NULL || s_cb_array[n]==new_cb) {
+            s_cb_array[n]=new_cb;
             portEXIT_CRITICAL(&spinlock_rtc_deep_sleep);
             return ESP_OK;
         }
@@ -405,17 +406,46 @@ esp_err_t esp_deep_sleep_register_hook(esp_deep_sleep_cb_t new_dslp_cb)
     return ESP_ERR_NO_MEM;
 }
 
-void esp_deep_sleep_deregister_hook(esp_deep_sleep_cb_t old_dslp_cb)
+static void s_sleep_hook_deregister(esp_deep_sleep_cb_t old_cb, esp_deep_sleep_cb_t s_cb_array[MAX_DSLP_HOOKS])
 {
     portENTER_CRITICAL(&spinlock_rtc_deep_sleep);
-    for(int n = 0; n < MAX_DSLP_HOOKS; n++){
-        if(s_dslp_cb[n] == old_dslp_cb) {
-            s_dslp_cb[n] = NULL;
+    for (int n = 0; n < MAX_DSLP_HOOKS; n++) {
+        if(s_cb_array[n] == old_cb) {
+            s_cb_array[n] = NULL;
         }
     }
     portEXIT_CRITICAL(&spinlock_rtc_deep_sleep);
 }
 
+esp_err_t esp_deep_sleep_register_hook(esp_deep_sleep_cb_t new_dslp_cb)
+{
+    return s_sleep_hook_register(new_dslp_cb, s_dslp_cb);
+}
+
+void esp_deep_sleep_deregister_hook(esp_deep_sleep_cb_t old_dslp_cb)
+{
+    s_sleep_hook_deregister(old_dslp_cb, s_dslp_cb);
+}
+
+esp_err_t esp_deep_sleep_register_phy_hook(esp_deep_sleep_cb_t new_dslp_cb)
+{
+    return s_sleep_hook_register(new_dslp_cb, s_dslp_phy_cb);
+}
+
+void esp_deep_sleep_deregister_phy_hook(esp_deep_sleep_cb_t old_dslp_cb)
+{
+    s_sleep_hook_deregister(old_dslp_cb, s_dslp_phy_cb);
+}
+
+static void s_do_deep_sleep_phy_callback(void)
+{
+    for (int n = 0; n < MAX_DSLP_HOOKS; n++) {
+        if (s_dslp_phy_cb[n] != NULL) {
+            s_dslp_phy_cb[n]();
+        }
+    }
+}
+
 static int s_cache_suspend_cnt = 0;
 
 static void IRAM_ATTR suspend_cache(void) {
@@ -658,6 +688,12 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
         should_skip_sleep = light_sleep_uart_prepare(pd_flags, sleep_duration);
     }
 
+    // Do deep-sleep PHY related callback, which need to be executed when the PLL clock is exists.
+    // For light-sleep, PHY state is managed by the upper layer of the wifi/bt protocol stack.
+    if (deep_sleep) {
+        s_do_deep_sleep_phy_callback();
+    }
+
 #if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
     if (!deep_sleep && (pd_flags & PMU_SLEEP_PD_TOP)) {
         sleep_retention_do_system_retention(true);

components/esp_phy/lib

@@ -1 +1 @@
-Subproject commit 2d319a382336cf0522ea4bb5a3fbd6701a8633c6
+Subproject commit c28825eb1be6bbe30e0ee8cfcd54614bf86273e7

components/esp_phy/src/phy_init.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,7 +20,7 @@
 #include "nvs_flash.h"
 #include "esp_efuse.h"
 #include "esp_timer.h"
-#include "esp_sleep.h"
+#include "esp_private/esp_sleep_internal.h"
 #include "sdkconfig.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/portmacro.h"
@@ -865,9 +865,9 @@ void esp_phy_load_cal_and_init(void)
     esp_phy_release_init_data(init_data);
 #endif
 
-    ESP_ERROR_CHECK(esp_deep_sleep_register_hook(&phy_close_rf));
+    ESP_ERROR_CHECK(esp_deep_sleep_register_phy_hook(&phy_close_rf));
 #if !CONFIG_IDF_TARGET_ESP32
-    ESP_ERROR_CHECK(esp_deep_sleep_register_hook(&phy_xpd_tsens));
+    ESP_ERROR_CHECK(esp_deep_sleep_register_phy_hook(&phy_xpd_tsens));
 #endif
 
     free(cal_data); // PHY maintains a copy of calibration data, so we can free this

components/esp_rom/esp32c2/ld/esp32c2.rom.ld

@@ -1093,7 +1093,6 @@ r_ble_lll_conn_coex_dpc_update_on_event_scheduled = 0x400014e4;
 r_ble_lll_conn_coex_dpc_update_on_event_started = 0x400014e8;
 r_ble_lll_conn_cth_flow_alloc_credit = 0x400014ec;
 r_ble_lll_conn_current_sm_over = 0x400014f4;
-r_ble_lll_conn_event_end_timer_cb = 0x40001508;
 r_ble_lll_conn_event_is_over = 0x40001510;
 r_ble_lll_conn_event_start_cb = 0x40001514;
 r_ble_lll_conn_free_rx_mbuf = 0x40001518;
@@ -1483,7 +1482,7 @@ is_lmac_idle = 0x40001b0c;
 /*lmacAdjustTimestamp = 0x40001b10;*/
 lmacDiscardAgedMSDU = 0x40001b14;
 /*lmacDiscardMSDU = 0x40001b18;*/
-lmacEndFrameExchangeSequence = 0x40001b1c;
+/*lmacEndFrameExchangeSequence = 0x40001b1c;*/
 lmacIsIdle = 0x40001b20;
 lmacIsLongFrame = 0x40001b24;
 /*lmacMSDUAged = 0x40001b28;*/
@@ -1845,7 +1844,7 @@ ic_ebuf_recycle_rx = 0x40001fa0;
 ic_ebuf_recycle_tx = 0x40001fa4;
 ic_reset_rx_ba = 0x40001fa8;
 ieee80211_align_eb = 0x40001fac;
-ieee80211_ampdu_reorder = 0x40001fb0;
+/*ieee80211_ampdu_reorder = 0x40001fb0;*/
 ieee80211_ampdu_start_age_timer = 0x40001fb4;
 /*ieee80211_encap_esfbuf = 0x40001fb8;*/
 ieee80211_is_tx_allowed = 0x40001fbc;
@@ -1975,12 +1974,12 @@ esp_coex_rom_version_get = 0x40002168;
 coex_bt_release = 0x4000216c;
 coex_bt_request = 0x40002170;
 coex_core_ble_conn_dyn_prio_get = 0x40002174;
-coex_core_event_duration_get = 0x40002178;
+/*coex_core_event_duration_get = 0x40002178;*/
 coex_core_pti_get = 0x4000217c;
 coex_core_release = 0x40002180;
 coex_core_request = 0x40002184;
 coex_core_status_get = 0x40002188;
-coex_core_timer_idx_get = 0x4000218c;
+/*coex_core_timer_idx_get = 0x4000218c;*/
 coex_event_duration_get = 0x40002190;
 coex_hw_timer_disable = 0x40002194;
 coex_hw_timer_enable = 0x40002198;

components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld

@@ -39,7 +39,7 @@ ppMapWaitTxq = 0x40001810;
 /*sta_input = 0x40001870;*/
 ieee80211_crypto_decap = 0x4000189c;
 ieee80211_decap = 0x400018a0;
-coex_core_timer_idx_get = 0x400018d0;
+/*coex_core_timer_idx_get = 0x400018d0;*/
 rom1_chip_i2c_readReg = 0x40001924;
 rom1_chip_i2c_writeReg = 0x40001928;
 rom_index_to_txbbgain = 0x40001964;

components/esp_rom/esp32c3/ld/esp32c3.rom.ld

@@ -1516,7 +1516,7 @@ is_lmac_idle = 0x400015e8;
 /*lmacAdjustTimestamp = 0x400015ec;*/
 lmacDiscardAgedMSDU = 0x400015f0;
 /*lmacDiscardMSDU = 0x400015f4;*/
-lmacEndFrameExchangeSequence = 0x400015f8;
+/*lmacEndFrameExchangeSequence = 0x400015f8;*/
 lmacIsIdle = 0x400015fc;
 lmacIsLongFrame = 0x40001600;
 /*lmacMSDUAged = 0x40001604;*/
@@ -1717,7 +1717,7 @@ ic_ebuf_recycle_rx = 0x40001844;
 ic_ebuf_recycle_tx = 0x40001848;
 ic_reset_rx_ba = 0x4000184c;
 ieee80211_align_eb = 0x40001850;
-ieee80211_ampdu_reorder = 0x40001854;
+/*ieee80211_ampdu_reorder = 0x40001854;*/
 ieee80211_ampdu_start_age_timer = 0x40001858;
 /*ieee80211_encap_esfbuf = 0x4000185c;*/
 ieee80211_is_tx_allowed = 0x40001860;
@@ -1760,7 +1760,7 @@ esp_coex_rom_version_get = 0x400018ac;
 coex_bt_release = 0x400018b0;
 coex_bt_request = 0x400018b4;
 coex_core_ble_conn_dyn_prio_get = 0x400018b8;
-coex_core_event_duration_get = 0x400018bc;
+/*coex_core_event_duration_get = 0x400018bc;*/
 coex_core_pti_get = 0x400018c0;
 coex_core_release = 0x400018c4;
 coex_core_request = 0x400018c8;

components/esp_rom/esp32c6/ld/esp32c6.rom.coexist.ld

@@ -22,12 +22,12 @@ esp_coex_rom_version_get = 0x40000afc;
 coex_bt_release = 0x40000b00;
 coex_bt_request = 0x40000b04;
 coex_core_ble_conn_dyn_prio_get = 0x40000b08;
-coex_core_event_duration_get = 0x40000b0c;
+/*coex_core_event_duration_get = 0x40000b0c;*/
 coex_core_pti_get = 0x40000b10;
 coex_core_release = 0x40000b14;
 coex_core_request = 0x40000b18;
 coex_core_status_get = 0x40000b1c;
-coex_core_timer_idx_get = 0x40000b20;
+/*coex_core_timer_idx_get = 0x40000b20;*/
 coex_event_duration_get = 0x40000b24;
 coex_hw_timer_disable = 0x40000b28;
 coex_hw_timer_enable = 0x40000b2c;

components/esp_rom/esp32c6/ld/esp32c6.rom.net80211.ld

@@ -31,7 +31,7 @@ ic_ebuf_recycle_rx = 0x40000b70;
 ic_ebuf_recycle_tx = 0x40000b74;
 ic_reset_rx_ba = 0x40000b78;
 ieee80211_align_eb = 0x40000b7c;
-ieee80211_ampdu_reorder = 0x40000b80;
+/*ieee80211_ampdu_reorder = 0x40000b80;*/
 ieee80211_ampdu_start_age_timer = 0x40000b84;
 /*ieee80211_encap_esfbuf = 0x40000b88;*/
 ieee80211_is_tx_allowed = 0x40000b8c;

components/esp_rom/esp32c6/ld/esp32c6.rom.pp.ld

@@ -37,7 +37,7 @@ is_lmac_idle = 0x40000c14;
 /*lmacAdjustTimestamp = 0x40000c18;*/
 lmacDiscardAgedMSDU = 0x40000c1c;
 /*lmacDiscardMSDU = 0x40000c20;*/
-lmacEndFrameExchangeSequence = 0x40000c24;
+/*lmacEndFrameExchangeSequence = 0x40000c24;*/
 lmacIsIdle = 0x40000c28;
 lmacIsLongFrame = 0x40000c2c;
 /*lmacMSDUAged = 0x40000c30;*/
@@ -80,7 +80,7 @@ pm_on_data_rx = 0x40000ca8;
 pm_sleep_for = 0x40000cc4;
 //pm_tbtt_process = 0x40000cc8;
 ppAMPDU2Normal = 0x40000ccc;
-ppAssembleAMPDU = 0x40000cd0;
+/* ppAssembleAMPDU = 0x40000cd0; */
 ppCalFrameTimes = 0x40000cd4;
 ppCalSubFrameLength = 0x40000cd8;
 //ppCalTxAMPDULength = 0x40000cdc;

components/esp_rom/esp32s3/ld/esp32s3.rom.ld

@@ -1817,7 +1817,7 @@ is_lmac_idle = 0x400052f8;
 /*lmacAdjustTimestamp = 0x40005304;*/
 lmacDiscardAgedMSDU = 0x40005310;
 /*lmacDiscardMSDU = 0x4000531c;*/
-lmacEndFrameExchangeSequence = 0x40005328;
+/*lmacEndFrameExchangeSequence = 0x40005328;*/
 lmacIsIdle = 0x40005334;
 lmacIsLongFrame = 0x40005340;
 /*lmacMSDUAged = 0x4000534c;*/
@@ -2025,7 +2025,7 @@ ic_ebuf_recycle_rx = 0x40005a24;
 ic_ebuf_recycle_tx = 0x40005a30;
 ic_reset_rx_ba = 0x40005a3c;
 ieee80211_align_eb = 0x40005a48;
-ieee80211_ampdu_reorder = 0x40005a54;
+/* ieee80211_ampdu_reorder = 0x40005a54; */
 ieee80211_ampdu_start_age_timer = 0x40005a60;
 /* ieee80211_encap_esfbuf = 0x40005a6c; */
 ieee80211_is_tx_allowed = 0x40005a78;
@@ -2069,7 +2069,7 @@ esp_coex_rom_version_get = 0x40005b68;
 coex_bt_release = 0x40005b74;
 coex_bt_request = 0x40005b80;
 coex_core_ble_conn_dyn_prio_get = 0x40005b8c;
-coex_core_event_duration_get = 0x40005b98;
+/*coex_core_event_duration_get = 0x40005b98;*/
 coex_core_pti_get = 0x40005ba4;
 coex_core_release = 0x40005bb0;
 coex_core_request = 0x40005bbc;

components/esp_wifi/lib

@@ -1 +1 @@
-Subproject commit 1cc8f30b8f519b7355f6cdd1e456e43b9a231cfb
+Subproject commit fef75ab8170fa5123fdb56f12852e5d2481a0d69

components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h

@@ -332,6 +332,8 @@ FORCE_INLINE_ATTR BaseType_t xPortGetCoreID(void)
     } else {                                \
         portENTER_CRITICAL(mux);            \
     }                                       \
+    BaseType_t ret = pdPASS;                \
+    ret;                                    \
 })
 #define portEXIT_CRITICAL_SAFE(mux)     ({  \
     if (xPortInIsrContext()) {              \
@@ -340,7 +342,7 @@ FORCE_INLINE_ATTR BaseType_t xPortGetCoreID(void)
         portEXIT_CRITICAL(mux);             \
     }                                       \
 })
-#define portTRY_ENTER_CRITICAL_SAFE(mux, timeout)   portENTER_CRITICAL_SAFE(mux, timeout)
+#define portTRY_ENTER_CRITICAL_SAFE(mux, timeout)   portENTER_CRITICAL_SAFE(mux)
 
 // ---------------------- Yielding -------------------------
 

components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h

@@ -464,7 +464,7 @@ FORCE_INLINE_ATTR BaseType_t xPortGetCoreID(void);
 #define portENTER_CRITICAL_ISR(mux)                 vPortEnterCritical(mux)
 #define portEXIT_CRITICAL_ISR(mux)                  vPortExitCritical(mux)
 
-#define portTRY_ENTER_CRITICAL_SAFE(mux, timeout)   xPortEnterCriticalTimeoutSafe(mux)
+#define portTRY_ENTER_CRITICAL_SAFE(mux, timeout)   xPortEnterCriticalTimeoutSafe(mux, timeout)
 #define portENTER_CRITICAL_SAFE(mux)                vPortEnterCriticalSafe(mux)
 #define portEXIT_CRITICAL_SAFE(mux)                 vPortExitCriticalSafe(mux)
 

components/heap/heap_caps.c

@@ -507,7 +507,7 @@ HEAP_IRAM_ATTR void *heap_caps_calloc( size_t n, size_t size, uint32_t caps)
 
 
     if (!ptr && size > 0){
-        heap_caps_alloc_failed(size, caps, __func__);
+        heap_caps_alloc_failed(n * size, caps, __func__);
     }
 
     return ptr;

components/soc/esp32s3/include/soc/rtc_cntl_reg.h

@@ -3689,7 +3689,7 @@ Due to the LDO slaves, RTC_CNTL_DATE_REG[18:13] can only be used for LDO adjustm
 /*LDO SLAVE : R/W ;bitpos:[18:13] ; default: 6'd0 ;*/
 /*description: .*/
 #define RTC_CNTL_SLAVE_PD    0x0000003F
-#define RTC_CNTL_SLAVE_PD_M  ((RTC_CNTL_SLAVE_V)<<(RTC_CNTL_SLAVE_S))
+#define RTC_CNTL_SLAVE_PD_M  ((RTC_CNTL_SLAVE_PD_V)<<(RTC_CNTL_SLAVE_PD_S))
 #define RTC_CNTL_SLAVE_PD_V  0x3F
 #define RTC_CNTL_SLAVE_PD_S  13
 

components/wpa_supplicant/esp_supplicant/src/esp_hostap.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -59,10 +59,7 @@ void *hostap_init(void)
     auth_conf = (struct wpa_auth_config *)os_zalloc(sizeof(struct  wpa_auth_config));
 
     if (auth_conf == NULL) {
-        os_free(hapd->conf);
-        os_free(hapd);
-        hapd = NULL;
-        return NULL;
+        goto fail;
     }
 
     hapd->conf->sae_pwe = esp_wifi_get_config_sae_pwe_h2e_internal(WIFI_IF_AP);
@@ -145,23 +142,14 @@ void *hostap_init(void)
     hapd->conf->wpa_key_mgmt = auth_conf->wpa_key_mgmt;
     hapd->conf->ssid.wpa_passphrase = (char *)os_zalloc(WIFI_PASSWORD_LEN_MAX);
     if (hapd->conf->ssid.wpa_passphrase == NULL) {
-        os_free(auth_conf);
-        os_free(hapd->conf);
-        os_free(hapd);
-        hapd = NULL;
-        return NULL;
+        goto fail;
     }
 
 #ifdef CONFIG_SAE
     if (authmode == WIFI_AUTH_WPA3_PSK ||
         authmode == WIFI_AUTH_WPA2_WPA3_PSK) {
         if (wpa3_hostap_auth_init(hapd) != 0) {
-            os_free(hapd->conf->ssid.wpa_passphrase);
-            os_free(auth_conf);
-            os_free(hapd->conf);
-            os_free(hapd);
-            hapd = NULL;
-            return NULL;
+            goto fail;
         }
     }
 #endif /* CONFIG_SAE */
@@ -176,11 +164,26 @@ void *hostap_init(void)
     esp_wifi_get_macaddr_internal(WIFI_IF_AP, hapd->own_addr);
 
     hapd->wpa_auth = wpa_init(hapd->own_addr, auth_conf, NULL);
+    if (hapd->wpa_auth == NULL) {
+        goto fail;
+    }
+
     esp_wifi_set_appie_internal(WIFI_APPIE_WPA, hapd->wpa_auth->wpa_ie, (uint16_t)hapd->wpa_auth->wpa_ie_len, 0);
     os_free(auth_conf);
     global_hapd = hapd;
 
     return (void *)hapd;
+fail:
+    if (hapd->conf->ssid.wpa_passphrase != NULL) {
+        os_free(hapd->conf->ssid.wpa_passphrase);
+    }
+    if (auth_conf != NULL) {
+        os_free(auth_conf);
+    }
+    os_free(hapd->conf);
+    os_free(hapd);
+    hapd = NULL;
+    return NULL;
 }
 
 void hostapd_cleanup(struct hostapd_data *hapd)
@@ -278,8 +281,8 @@ int esp_wifi_build_rsnxe(struct hostapd_data *hapd, u8 *eid, size_t len)
     return pos - eid;
 }
 
-u16 esp_send_assoc_resp(struct hostapd_data *hapd, struct sta_info *sta,
-        const u8 *addr, u16 status_code, bool omit_rsnxe, int subtype)
+u16 esp_send_assoc_resp(struct hostapd_data *hapd, const u8 *addr,
+        u16 status_code, bool omit_rsnxe, int subtype)
 {
 #define ASSOC_RESP_LENGTH 20
     u8 buf[ASSOC_RESP_LENGTH];

components/wpa_supplicant/esp_supplicant/src/esp_hostap.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,9 +15,8 @@ extern "C" {
 #ifdef CONFIG_ESP_WIFI_SOFTAP_SUPPORT
 void *hostap_init(void);
 bool hostap_deinit(void *data);
-u16 esp_send_assoc_resp(struct hostapd_data *data, struct sta_info *sta,
-                    const u8 *addr, u16 status_code, bool omit_rsnxe,
-                    int subtype);
+u16 esp_send_assoc_resp(struct hostapd_data *data, const u8 *addr,
+                    u16 status_code, bool omit_rsnxe, int subtype);
 #endif
 
 #ifdef __cplusplus

components/wpa_supplicant/esp_supplicant/src/esp_wpa3.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -415,10 +415,6 @@ static void wpa3_process_rx_commit(wpa3_hostap_auth_event_t *evt)
         }
     }
 
-    if (!sta->lock) {
-        sta->lock = os_semphr_create(1, 1);
-    }
-
     if (sta->lock && os_semphr_take(sta->lock, 0)) {
         sta->sae_commit_processing = true;
         ret = handle_auth_sae(hapd, sta, frm->msg, frm->len, frm->bssid, frm->auth_transaction, frm->status);

components/wpa_supplicant/esp_supplicant/src/esp_wpa_main.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -295,7 +295,7 @@ static int check_n_add_wps_sta(struct hostapd_data *hapd, struct sta_info *sta_i
 
     if (sta_info->eapol_sm) {
         wpa_printf(MSG_DEBUG, "considering station " MACSTR " for WPS", MAC2STR(sta_info->addr));
-        if (esp_send_assoc_resp(hapd, sta_info, sta_info->addr, WLAN_STATUS_SUCCESS, true, subtype) != WLAN_STATUS_SUCCESS) {
+        if (esp_send_assoc_resp(hapd, sta_info->addr, WLAN_STATUS_SUCCESS, true, subtype) != WLAN_STATUS_SUCCESS) {
             wpa_printf(MSG_ERROR, "failed to send assoc response " MACSTR, MAC2STR(sta_info->addr));
             return -1;
         }
@@ -314,52 +314,79 @@ static bool hostap_sta_join(void **sta, u8 *bssid, u8 *wpa_ie, u8 wpa_ie_len,u8
         goto fail;
     }
 
-    if (*sta && !esp_wifi_ap_is_sta_sae_reauth_node(bssid)) {
-        ap_free_sta(hapd, *sta);
+    if (*sta) {
+        struct sta_info *old_sta = *sta;
+#ifdef CONFIG_SAE
+        if (old_sta->lock && os_semphr_take(old_sta->lock, 0) != TRUE) {
+            wpa_printf(MSG_INFO, "Ignore assoc request as softap is busy with sae calculation for station "MACSTR, MAC2STR(bssid));
+            if (esp_send_assoc_resp(hapd, bssid, WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY, rsnxe ? false : true, subtype) != WLAN_STATUS_SUCCESS) {
+                goto fail;
+            }
+            return false;
+        }
+#endif /* CONFIG_SAE */
+        if (!esp_wifi_ap_is_sta_sae_reauth_node(bssid)) {
+            ap_free_sta(hapd, old_sta);
+        }
+#ifdef CONFIG_SAE
+          else if (old_sta && old_sta->lock) {
+            sta_info = old_sta;
+            goto process_old_sta;
+        }
+#endif /* CONFIG_SAE */
     }
 
-    sta_info = ap_sta_add(hapd, bssid);
+    sta_info = ap_get_sta(hapd, bssid);
     if (!sta_info) {
-        wpa_printf(MSG_ERROR, "failed to add station " MACSTR, MAC2STR(bssid));
-        goto fail;
+        sta_info = ap_sta_add(hapd,bssid);
+        if (!sta_info) {
+            wpa_printf(MSG_ERROR, "failed to add station " MACSTR, MAC2STR(bssid));
+            goto fail;
+        }
     }
-
 #ifdef CONFIG_SAE
     if (sta_info->lock && os_semphr_take(sta_info->lock, 0) != TRUE) {
         wpa_printf(MSG_INFO, "Ignore assoc request as softap is busy with sae calculation for station "MACSTR, MAC2STR(bssid));
-        if (esp_send_assoc_resp(hapd, sta_info, bssid, WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY, rsnxe ? false : true, subtype) != WLAN_STATUS_SUCCESS) {
+        if (esp_send_assoc_resp(hapd, bssid, WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY, rsnxe ? false : true, subtype) != WLAN_STATUS_SUCCESS) {
             goto fail;
         }
         return false;
     }
+
+process_old_sta:
 #endif /* CONFIG_SAE */
 
+
 #ifdef CONFIG_WPS_REGISTRAR
     if (check_n_add_wps_sta(hapd, sta_info, wpa_ie, wpa_ie_len, pmf_enable, subtype) == 0) {
         if (sta_info->eapol_sm) {
-            *sta = sta_info;
-#ifdef CONFIG_SAE
-            if (sta_info->lock) {
-                os_semphr_give(sta_info->lock);
-            }
-#endif /* CONFIG_SAE */
-            return true;
+            goto done;
         }
     } else {
         goto fail;
     }
 #endif
     if (wpa_ap_join(sta_info, bssid, wpa_ie, wpa_ie_len, rsnxe, rsnxe_len, pmf_enable, subtype)) {
-        *sta = sta_info;
-#ifdef CONFIG_SAE
-        if (sta_info->lock) {
-            os_semphr_give(sta_info->lock);
-        }
-#endif /* CONFIG_SAE */
-        return true;
+        goto done;
+    } else {
+        goto fail;
     }
+done:
+    *sta = sta_info;
+#ifdef CONFIG_SAE
+    if (sta_info->lock) {
+        os_semphr_give(sta_info->lock);
+    }
+#endif /* CONFIG_SAE */
+    return true;
 
 fail:
+
+#ifdef CONFIG_SAE
+    if (sta_info && sta_info->lock) {
+        os_semphr_give(sta_info->lock);
+    }
+#endif /* CONFIG_SAE */
     esp_wifi_ap_deauth_internal(bssid, WLAN_REASON_PREV_AUTH_NOT_VALID);
     return false;
 }

components/wpa_supplicant/src/ap/sta_info.c

@@ -175,6 +175,7 @@ struct sta_info * ap_sta_add(struct hostapd_data *hapd, const u8 *addr)
 #ifdef CONFIG_SAE
 	sta->sae_commit_processing = false;
 	sta->remove_pending = false;
+	sta->lock = os_semphr_create(1, 1);
 #endif /* CONFIG_SAE */
 
 	return sta;

components/wpa_supplicant/src/ap/wpa_auth.c

@@ -789,7 +789,7 @@ continue_processing:
              * strong random numbers. Reject the first 4-way
              * handshake(s) and collect some entropy based on the
              * information from it. Once enough entropy is
-             * available, the next atempt will trigger GMK/Key
+             * available, the next attempt will trigger GMK/Key
              * Counter update and the station will be allowed to
              * continue.
              */
@@ -2601,7 +2601,7 @@ send_resp:
                 omit_rsnxe = true;
             }
 
-            if (esp_send_assoc_resp(hapd, sta, bssid, resp, omit_rsnxe, subtype) != WLAN_STATUS_SUCCESS) {
+            if (esp_send_assoc_resp(hapd, bssid, resp, omit_rsnxe, subtype) != WLAN_STATUS_SUCCESS) {
                 resp = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA;
             }
 

examples/bluetooth/esp_ble_mesh/ble_mesh_fast_provision/fast_prov_server/tutorial/EspBleMesh.md

@@ -12,7 +12,7 @@ A video of this example can be seen from [here](https://dl.espressif.com/BLE/pub
 
 > Note:
 > 
-> 1. Please flash the [`fast_prov_server`](https://github.com/espressif/esp-idf/tree/master/examples/bluetooth/esp_ble_mesh/ble_mesh_fast_provision/fast_prov_server) to the development boards first;
+> 1. Please flash the [`fast_prov_server`](../../) to the development boards first;
 > 2. To have a better understanding of the performance of the BLE Mesh network, we recommend that at least 3 devices should be added in your network.
 > 3. We recommend that you solder LED indicators if your development board does not come with lights. 
 > 4. Please check the type of board and LED pin definition enabled in `Example BLE Mesh Config` by running `idf.py menuconfig`

examples/bluetooth/nimble/blecent/main/main.c

@@ -28,6 +28,26 @@
 #include "services/gap/ble_svc_gap.h"
 #include "blecent.h"
 
+#if CONFIG_EXAMPLE_USE_CI_ADDRESS
+#ifdef CONFIG_IDF_TARGET_ESP32
+#define TEST_CI_ADDRESS_CHIP_OFFSET (0)
+#elif CONFIG_IDF_TARGET_ESP32C2
+#define TEST_CI_ADDRESS_CHIP_OFFSET (1)
+#elif CONFIG_IDF_TARGET_ESP32C3
+#define TEST_CI_ADDRESS_CHIP_OFFSET (2)
+#elif CONFIG_IDF_TARGET_ESP32C6
+#define TEST_CI_ADDRESS_CHIP_OFFSET (3)
+#elif CONFIG_IDF_TARGET_ESP32C5
+#define TEST_CI_ADDRESS_CHIP_OFFSET (4)
+#elif CONFIG_IDF_TARGET_ESP32H2
+#define TEST_CI_ADDRESS_CHIP_OFFSET (5)
+#elif CONFIG_IDF_TARGET_ESP32P4
+#define TEST_CI_ADDRESS_CHIP_OFFSET (6)
+#elif CONFIG_IDF_TARGET_ESP32S3
+#define TEST_CI_ADDRESS_CHIP_OFFSET (7)
+#endif
+#endif
+
 /*** The UUID of the service containing the subscribable characterstic ***/
 static const ble_uuid_t * remote_svc_uuid =
     BLE_UUID128_DECLARE(0x2d, 0x71, 0xa2, 0x59, 0xb4, 0x58, 0xc8, 0x12,
@@ -474,6 +494,7 @@ ext_blecent_should_connect(const struct ble_gap_ext_disc_desc *disc)
         addr_offset = (uint32_t *)&peer_addr[1];
         *addr_offset = atoi(CONFIG_EXAMPLE_PEER_ADDR);
         peer_addr[5] = 0xC3;
+        peer_addr[0] = TEST_CI_ADDRESS_CHIP_OFFSET;
 #endif // !CONFIG_EXAMPLE_USE_CI_ADDRESS
         if (memcmp(peer_addr, disc->addr.val, sizeof(disc->addr.val)) != 0) {
             return 0;
@@ -537,6 +558,7 @@ blecent_should_connect(const struct ble_gap_disc_desc *disc)
         addr_offset = (uint32_t *)&peer_addr[1];
         *addr_offset = atoi(CONFIG_EXAMPLE_PEER_ADDR);
         peer_addr[5] = 0xC3;
+        peer_addr[0] = TEST_CI_ADDRESS_CHIP_OFFSET;
 #endif // !CONFIG_EXAMPLE_USE_CI_ADDRESS
         if (memcmp(peer_addr, disc->addr.val, sizeof(disc->addr.val)) != 0) {
             return 0;

examples/bluetooth/nimble/blecent/sdkconfig.ci

@@ -1,2 +1,2 @@
 CONFIG_EXAMPLE_USE_CI_ADDRESS=y
-CONFIG_EXAMPLE_PEER_ADDR="${CI_JOB_ID}"
+CONFIG_EXAMPLE_PEER_ADDR="${CI_PIPELINE_ID}"

examples/bluetooth/nimble/blecent/sdkconfig.ci.esp32c2_xtal26m

@@ -1,4 +1,4 @@
 CONFIG_IDF_TARGET="esp32c2"
 CONFIG_XTAL_FREQ_26=y
 CONFIG_EXAMPLE_USE_CI_ADDRESS=y
-CONFIG_EXAMPLE_PEER_ADDR="${CI_JOB_ID}"
+CONFIG_EXAMPLE_PEER_ADDR="${CI_PIPELINE_ID}"

examples/bluetooth/nimble/power_save/README.md

@@ -20,7 +20,9 @@ This example contains some build configurations. For each configuration, a few c
 - `sdkconfig.40m.esp32s3`: ESP32S3 uses main XTAL as low power clock in light sleep enabled.
 - `sdkconfig.defaults.esp32h2`: ESP32H2 uses 32kHz XTAL as low power clock in light sleep enabled.
 - `sdkconfig.32m.esp32h2`: ESP32H2 uses main XTAL as low power clock in light sleep enabled.
-- `sdkconfig.defaults.esp32c2`: ESP32C2 uses main XTAL as low power clock in light sleep enabled.
+- `sdkconfig.defaults.esp32c2`: ESP32C2 uses 32kHz XTAL as low power clock in light sleep enabled.
+- `sdkconfig.26m.esp32c2`: ESP32C2 uses main XTAL as low power clock in light sleep enabled.
+
 ## How to use example
 
 ### Hardware Required
@@ -39,9 +41,10 @@ idf.py menuconfig
    - `Component config > Power Management > [*] Support for power management`
 3. Configure FreeRTOS:
    - `Component config > FreeRTOS > Kernel`
-      -  `(1000) configTICK_RATE_HZ`
-      -  `[*] configUSE_TICKLESS_IDLE`
-      -  `(3)     configEXPECTED_IDLE_TIME_BEFORE_SLEEP`
+     -  `(1000) configTICK_RATE_HZ`
+     -  `[*] configUSE_TICKLESS_IDLE`
+     -  `(3)     configEXPECTED_IDLE_TIME_BEFORE_SLEEP`
+
 #### For Chip ESP32/ESP32-C3/ESP32-S3
 
 4. Enable power down MAC and baseband:
@@ -55,28 +58,19 @@ idf.py menuconfig
 7. Enable power up main XTAL during light sleep:
    - `Component config > Bluetooth > Controller Options > MODEM SLEEP Options > [*] power up main XTAL during light sleep`
 
-#### For Chip ESP32-C6/ESP32-H2
+#### For Chip ESP32-C6/ESP32-H2/ESP32-C2
 
 4. Enable bluetooth modem sleep:
    - `Component config > Bluetooth > Controller Options`
      - `[*] Enable BLE sleep`
 5. Configure bluetooth low power clock:
    - `Component config > Bluetooth > Controller Options > BLE low power clock source`
-   - Use RTC clock source as low power clock sourceduring light sleep:
+   - Use RTC clock source as low power clock source during light sleep:
      - `(X) Use system RTC slow clock source`
 6. Power down flash during light sleep:
    - `Component config > Hardware Settings > Sleep Config`
      - `[*] Power down flash in light sleep when there is no SPIRAM`
 
-#### For Chip ESP32-C2
-
-4. Enable bluetooth modem sleep:
-   - `Component config > Bluetooth > Controller Options`
-     - `[*] Enable BLE sleep`
-5. Power down flash during light sleep:
-   - `Component config > Hardware Settings > Sleep Config`
-     - `[*] Power down flash in light sleep when there is no SPIRAM`
-
 ### Build and Flash
 
 ```
@@ -102,7 +96,7 @@ See the Getting Started Guide for full steps to configure and use ESP-IDF to bui
 
 ## Example Output
 
-When you run this example, the prints the following at the very begining:
+When you run this example, the prints the following at the very beginning:
 
 ```
 I (333) cpu_start: Starting scheduler.
@@ -138,10 +132,11 @@ I (463) NimBLE:
 | ESP32S3                                     | 240 mA      | 17.9 mA     | 3.3 mA                  | 230 uA                   |
 | ESP32H2                                     | 82 mA       | 16.0 mA     | 4.0 mA                  | 24 uA                    |
 | ESP32C6                                     | 240 mA      | 22 mA       | 3.3 mA                  | 34  uA                   |
-| ESP32C2                                     | 130 mA      | 18.0 mA     | 2.5 mA                  | X                        |
+| ESP32C2                                     | 130 mA      | 18.0 mA     | 2.5 mA                  | 169 uA                   |
 X: This feature is currently not supported.
 
 ## Example Breakdown
 
 - ESP32 does not support the use of main XTAL in light sleep mode, so an external 32kHz crystal is required.
-- ESP32C2 does not support the use of 32KHz XTAL in light sleep mode, the XTAL frequency is set to 26MHz in default.
+- ESP32C2 support XTAL frequency of 26MHz and 40MHz, the XTAL frequency is set to 26MHz in default.
+- ESP32C2 support external 32kHz crystal by connecting the crystal to the chip through pin0

examples/bluetooth/nimble/power_save/main/main.c

@@ -17,6 +17,26 @@
 #include "services/gap/ble_svc_gap.h"
 #include "bleprph.h"
 
+#if CONFIG_EXAMPLE_USE_CI_ADDRESS
+#ifdef CONFIG_IDF_TARGET_ESP32
+#define TEST_CI_ADDRESS_CHIP_OFFSET (0)
+#elif CONFIG_IDF_TARGET_ESP32C2
+#define TEST_CI_ADDRESS_CHIP_OFFSET (1)
+#elif CONFIG_IDF_TARGET_ESP32C3
+#define TEST_CI_ADDRESS_CHIP_OFFSET (2)
+#elif CONFIG_IDF_TARGET_ESP32C6
+#define TEST_CI_ADDRESS_CHIP_OFFSET (3)
+#elif CONFIG_IDF_TARGET_ESP32C5
+#define TEST_CI_ADDRESS_CHIP_OFFSET (4)
+#elif CONFIG_IDF_TARGET_ESP32H2
+#define TEST_CI_ADDRESS_CHIP_OFFSET (5)
+#elif CONFIG_IDF_TARGET_ESP32P4
+#define TEST_CI_ADDRESS_CHIP_OFFSET (6)
+#elif CONFIG_IDF_TARGET_ESP32S3
+#define TEST_CI_ADDRESS_CHIP_OFFSET (7)
+#endif
+#endif
+
 #if CONFIG_EXAMPLE_EXTENDED_ADV
 static uint8_t ext_adv_pattern_1[] = {
     0x02, 0x01, 0x06,
@@ -468,6 +488,7 @@ bleprph_on_sync(void)
         uint32_t *offset = (uint32_t *)&addr[1];
         *offset = atoi(CONFIG_EXAMPLE_CI_ADDRESS_OFFSET);
         addr[5] = 0xC3;
+        addr[0] = TEST_CI_ADDRESS_CHIP_OFFSET;
         rc = ble_hs_id_set_rnd(addr);
         assert(rc == 0);
     }

examples/bluetooth/nimble/power_save/sdkconfig.26m.esp32c2

@@ -0,0 +1,24 @@
+CONFIG_IDF_TARGET="esp32c2"
+
+# Bluetooth Low Power Config
+CONFIG_BT_LE_SLEEP_ENABLE=y
+CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL=y
+
+#
+# Power Management
+#
+CONFIG_PM_ENABLE=y
+CONFIG_PM_DFS_INIT_AUTO=y
+
+# XTAL Freq Config
+CONFIG_XTAL_FREQ_26=y
+CONFIG_XTAL_FREQ=26
+
+#
+# Sleep Config
+#
+CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y
+CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION=y
+
+# RTC clock source
+CONFIG_RTC_CLK_SRC_INT_RC=y

examples/bluetooth/nimble/power_save/sdkconfig.ci

@@ -2,4 +2,4 @@
 # Test Config
 #
 CONFIG_EXAMPLE_USE_CI_ADDRESS=y
-CONFIG_EXAMPLE_CI_ADDRESS_OFFSET="${CI_JOB_ID}"
+CONFIG_EXAMPLE_CI_ADDRESS_OFFSET="${CI_PIPELINE_ID}"

examples/bluetooth/nimble/power_save/sdkconfig.ci.esp32c2_xtal26m

@@ -4,4 +4,4 @@ CONFIG_XTAL_FREQ_26=y
 # Test Config
 #
 CONFIG_EXAMPLE_USE_CI_ADDRESS=y
-CONFIG_EXAMPLE_CI_ADDRESS_OFFSET="${CI_JOB_ID}"
+CONFIG_EXAMPLE_CI_ADDRESS_OFFSET="${CI_PIPELINE_ID}"

examples/bluetooth/nimble/power_save/sdkconfig.defaults.esp32c2

@@ -1,7 +1,8 @@
-CONFIG_IDF_TARGET="esp32h2"
+CONFIG_IDF_TARGET="esp32c2"
 
 # Bluetooth Low Power Config
 CONFIG_BT_LE_SLEEP_ENABLE=y
+CONFIG_BT_LE_LP_CLK_SRC_DEFAULT=y
 
 #
 # Power Management
@@ -18,3 +19,6 @@ CONFIG_XTAL_FREQ=26
 #
 CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y
 CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION=y
+
+# RTC clock source
+CONFIG_RTC_CLK_SRC_EXT_OSC=y

examples/openthread/ot_sleepy_device/light_sleep/README.md

@@ -6,34 +6,100 @@ The example demonstrates the Thread Sleepy End Device (SED), the device will ent
 ## How to use example
 
 ### Hardware Required
+* One 802.15.4 SoC (for example ESP32-H2) runs [ot_cli](../../ot_cli/) example, and forms a Thread network.
+* A second 802.15.4 SoC runs this example.
 
-* Prepare an 802.15.4 SoC development board as an OpenThread Sleepy End Device (SED).
-* Connect the board using a USB cable for power supply and programming.
-* Choose another 802.15.4 SoC as the OpenThread Leader.
+### Configure the project
 
-## Configure the Openthread Dataset
+Set the chip target: `idf.py set-target <chip_name>`, then configure the project via `idf.py menuconfig`.
 
-* Run [ot_cli](../../ot_cli/) on another 802.15.4 SoC device to create openthread dataset configuration and start an openthread network as the leader.
-* Configure the Openthread dataset using `idf.py menuconfig` in `Component config ---> Openthread ---> Thread Operation Dataset`, ensuring that the openthread sleepy device's dataset matches the dataset of the leader.
+There are two options to configure Openthread Dataset:
+
+* Auto start mode: Enable `OPENTHREAD_AUTO_START` under `OpenThread Sleepy Example---> Enable the automatic start mode`, and configure the dataset under `Component config ---> Openthread ---> Thread Operation Dataset`.
+* Manual mode: Disable `OPENTHREAD_AUTO_START`, use the CLI command to configure the dataset and start network.
 
 ### Build and Flash
 
 Build the project and flash it to the board. Use the following command: `idf.py -p <PORT> erase-flash flash monitor`.
 
+### Configure the Openthread sleepy device
+```
+> mode -
+> pollperiod 3000
+> dataset set active <the same as dataset of the leader>
+> ifconfig up
+> thread start
+```
+
 ### Example Output
 
 As the example runs, you will see the log output indicating the initialization and operation of OpenThread, including the device joining the OpenThread network as a Sleepy End Device (SED) and periodic polling of the leader.
 
 ```
-I (769) btbb_init: btbb sleep retention initialization
-I (769) ieee802154: ieee802154 mac sleep retention initialization
-I(769) OPENTHREAD:[I] ChildSupervsn-: Timeout: 0 -> 190
-I (699) main_task: Returned from app_main()
-I (799) OPENTHREAD: OpenThread attached to netif
-I(799) OPENTHREAD:[N] Mle-----------: Mode 0x0f -> 0x04 [rx-on:no ftd:no full-net:no]
-I(809) OPENTHREAD:[N] Mle-----------: Role disabled -> detached
-I (819) OPENTHREAD: netif up
-I(1519) OPENTHREAD:[N] Mle-----------: Attach attempt 1, AnyPartition reattaching with Active Dataset
-I(2479) OPENTHREAD:[N] Mle-----------: RLOC16 fffe -> 5023
-I(2529) OPENTHREAD:[N] Mle-----------: Role detached -> child
-```  
+I (486) app_init: ESP-IDF:          v5.3-dev-2053-g4d7e86eeb6-dirty
+I (493) app_init: Min chip rev:     v0.0
+I (497) app_init: Max chip rev:     v0.99
+I (502) app_init: Chip rev:         v0.1
+I (507) sleep: Enable automatic switching of GPIO sleep configuration
+I (514) sleep_clock: System Power, Clock and Reset sleep retention initialization
+I (522) sleep_clock: Modem Power, Clock and Reset sleep retention initialization
+I (530) sleep_sys_periph: Interrupt Matrix sleep retention initialization
+I (538) sleep_sys_periph: HP System sleep retention initialization
+I (545) sleep_sys_periph: TEE/APM sleep retention initialization
+I (551) sleep_sys_periph: UART sleep retention initialization
+I (558) sleep_sys_periph: Timer Group sleep retention initialization
+I (565) sleep_sys_periph: IO Matrix sleep retention initialization
+I (572) sleep_sys_periph: SPI Mem sleep retention initialization
+I (579) sleep_sys_periph: SysTimer sleep retention initialization
+I (597) main_task: Started on CPU0
+I (597) main_task: Calling app_main()
+I (608) pm: Frequency switching config: CPU_MAX: 96, APB_MAX: 96, APB_MIN: 96, Light sleep: ENABLED
+I (609) ot_esp_power_save: Create ot cI (631) phy: phy_version: 230,2, 9aae6ea, Jan 15 2024, 11:17:12
+I (633) phy: libbtbb version: 944f18e, Jan 15 2024, 11:17:25
+I (634) btbb_init: btbb sleep retention initialization
+I (646) ieee802154: ieee802154 mac sleep retention initialization
+I (652) gdma: GDMA pair (0, 0) retention initialization
+I(660) OPENTHREAD:[I] ChildSupervsn-: Timeout: 0 -> 190
+> I (664) OPENTHREAD: OpenThread attached to netif
+I (635) main_task: Returned from app_main()
+> mode -
+
+I(2250683) OPENTHREAD:[N] Mle-----------: Mode 0x0f -> 0x04 [rx-on:no ftd:no full-net:no]
+Done
+> pollperiod 3000
+
+Done
+
+> dataset set active 0e080000000000010000000300001a35060004001fffe00208dead00beef00cafe0708fd000db800a00000051000112233445566778899aabbccdd0000030e4f70656e5468726561642d455350010212340410104810e2315100afd6bc9215a6bfac530c0402a0f7f8
+
+Done
+
+> ifconfig up
+
+Done
+I (2274801) OT_STATE: netif up
+> thread start
+
+I(2279917) OPENTHREAD:[N] Mle-----------: Role disabled -> detached
+Done
+> I(2280368) OPENTHREAD:[N] Mle-----------: Attach attempt 1, AnyPartition reattaching with Active Dataset
+I(2281262) OPENTHREAD:[N] Mle-----------: RLOC16 fffe -> 5019
+I(2281264) OPENTHREAD:[N] Mle-----------: Role detached -> child
+
+```
+
+When the device is running in auto start mode, the running log is as follows:
+
+```
+I(662) OPENTHREAD:[I] ChildSupervsn-: Timeout: 0 -> 190
+> I (666) OPENTHREAD: OpenThread attached to netif
+I(668) OPENTHREAD:[N] Mle-----------: Mode 0x0f -> 0x04 [rx-on:no ftd:no full-net:no]
+I (637) main_task: Returned from app_main()
+I(693) OPENTHREAD:[N] Mle-----------: Role disabled -> detached
+I (705) OT_STATE: netif up
+I(867) OPENTHREAD:[N] Mle-----------: Attach attempt 1, AnyPartition reattaching with Active Dataset
+I(1819) OPENTHREAD:[N] Mle-----------: RLOC16 fffe -> 500b
+I(1821) OPENTHREAD:[N] Mle-----------: Role detached -> child
+```
+### Note
+Currently, UART wakeup is not enabled. Once the device joins the network as a child and enters sleep mode, the OT CLI will become inaccessible.

examples/openthread/ot_sleepy_device/light_sleep/main/Kconfig.projbuild

@@ -0,0 +1,9 @@
+menu "OpenThread Sleepy Example"
+
+    config OPENTHREAD_AUTO_START
+        bool 'Enable the automatic start mode.'
+        default False
+        help
+            If enabled, the Openthread Device will create or connect to thread network with pre-configured
+            network parameters automatically. Otherwise, user need to configure Thread via CLI command manually.
+endmenu

examples/openthread/ot_sleepy_device/light_sleep/main/esp_ot_sleepy_device.c

@@ -20,6 +20,8 @@
 #include "esp_event.h"
 #include "esp_log.h"
 #include "esp_openthread.h"
+#include "esp_openthread_cli.h"
+#include "esp_openthread_lock.h"
 #include "esp_openthread_netif_glue.h"
 #include "esp_ot_sleepy_device_config.h"
 #include "esp_vfs_eventfd.h"
@@ -27,7 +29,6 @@
 #include "nvs_flash.h"
 #include "openthread/logging.h"
 #include "openthread/thread.h"
-
 #if CONFIG_ESP_SLEEP_DEBUG
 #include "esp_timer.h"
 #include "esp_sleep.h"
@@ -45,6 +46,9 @@
 
 #define TAG "ot_esp_power_save"
 
+static esp_pm_lock_handle_t s_cli_pm_lock = NULL;
+
+#if CONFIG_OPENTHREAD_AUTO_START
 static void create_config_network(otInstance *instance)
 {
     otLinkModeConfig linkMode = { 0 };
@@ -62,7 +66,41 @@ static void create_config_network(otInstance *instance)
         ESP_LOGE(TAG, "Failed to set OpenThread linkmode.");
         abort();
     }
-    ESP_ERROR_CHECK(esp_openthread_auto_start(NULL));
+
+    otOperationalDatasetTlvs dataset;
+    otError error = otDatasetGetActiveTlvs(esp_openthread_get_instance(), &dataset);
+    ESP_ERROR_CHECK(esp_openthread_auto_start((error == OT_ERROR_NONE) ? &dataset : NULL));
+}
+#endif // CONFIG_OPENTHREAD_AUTO_START
+
+static esp_err_t esp_openthread_sleep_device_init(void)
+{
+    esp_err_t ret = ESP_OK;
+
+    ret = esp_pm_lock_create(ESP_PM_CPU_FREQ_MAX, 0, "otcli", &s_cli_pm_lock);
+    if (ret == ESP_OK) {
+        esp_pm_lock_acquire(s_cli_pm_lock);
+        ESP_LOGI(TAG, "Successfully created CLI pm lock");
+    } else {
+        if (s_cli_pm_lock != NULL) {
+            esp_pm_lock_delete(s_cli_pm_lock);
+            s_cli_pm_lock = NULL;
+        }
+        ESP_LOGI(TAG, " Failed to create CLI pm lock");
+    }
+    return ret;
+}
+
+static void process_state_change(otChangedFlags flags, void* context)
+{
+    otDeviceRole ot_device_role = otThreadGetDeviceRole(esp_openthread_get_instance());
+    if(ot_device_role == OT_DEVICE_ROLE_CHILD) {
+        if (s_cli_pm_lock != NULL) {
+            esp_pm_lock_release(s_cli_pm_lock);
+            esp_pm_lock_delete(s_cli_pm_lock);
+            s_cli_pm_lock = NULL;
+        }
+    }
 }
 
 static esp_netif_t *init_openthread_netif(const esp_openthread_platform_config_t *config)
@@ -88,6 +126,7 @@ static void print_sleep_flag(void *arg)
 
 static void ot_task_worker(void *aContext)
 {
+    otError ret;
     esp_openthread_platform_config_t config = {
         .radio_config = ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG(),
         .host_config = ESP_OPENTHREAD_DEFAULT_HOST_CONFIG(),
@@ -97,17 +136,31 @@ static void ot_task_worker(void *aContext)
     // Initialize the OpenThread stack
     ESP_ERROR_CHECK(esp_openthread_init(&config));
 
+    esp_openthread_lock_acquire(portMAX_DELAY);
+    ret = otSetStateChangedCallback(esp_openthread_get_instance(), process_state_change, esp_openthread_get_instance());
+    esp_openthread_lock_release();
+    if(ret != OT_ERROR_NONE) {
+        ESP_LOGE(TAG, "Failed to set state changed callback");
+    }
 #if CONFIG_OPENTHREAD_LOG_LEVEL_DYNAMIC
     // The OpenThread log level directly matches ESP log level
     (void)otLoggingSetLevel(CONFIG_LOG_DEFAULT_LEVEL);
+#endif
+    // Initialize the OpenThread cli
+#if CONFIG_OPENTHREAD_CLI
+    esp_openthread_cli_init();
 #endif
     esp_netif_t *openthread_netif;
     // Initialize the esp_netif bindings
     openthread_netif = init_openthread_netif(&config);
     esp_netif_set_default_netif(openthread_netif);
-
+#if CONFIG_OPENTHREAD_AUTO_START
     create_config_network(esp_openthread_get_instance());
+#endif // CONFIG_OPENTHREAD_AUTO_START
 
+#if CONFIG_OPENTHREAD_CLI
+    esp_openthread_cli_create_task();
+#endif
 #if CONFIG_ESP_SLEEP_DEBUG
     esp_sleep_set_sleep_context(&s_sleep_ctx);
     esp_log_level_set(TAG, ESP_LOG_DEBUG);
@@ -170,6 +223,6 @@ void app_main(void)
     ESP_ERROR_CHECK(esp_netif_init());
     ESP_ERROR_CHECK(esp_vfs_eventfd_register(&eventfd_config));
     ESP_ERROR_CHECK(ot_power_save_init());
-
+    ESP_ERROR_CHECK(esp_openthread_sleep_device_init());
     xTaskCreate(ot_task_worker, "ot_power_save_main", 4096, NULL, 5, NULL);
 }

examples/openthread/ot_sleepy_device/light_sleep/sdkconfig.defaults

@@ -21,6 +21,7 @@ CONFIG_MBEDTLS_ECJPAKE_C=y
 CONFIG_OPENTHREAD_ENABLED=y
 CONFIG_OPENTHREAD_BORDER_ROUTER=n
 CONFIG_OPENTHREAD_DNS64_CLIENT=y
+CONFIG_OPENTHREAD_CLI=y
 # end of OpenThread
 
 #

examples/openthread/pytest_otbr.py

@@ -1,8 +1,6 @@
 # SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Unlicense OR CC0-1.0
 # !/usr/bin/env python3
-
-
 import os.path
 import re
 import subprocess
@@ -567,17 +565,14 @@ def test_ot_sleepy_device(dut: Tuple[IdfDut, IdfDut]) -> None:
         ocf.init_thread(leader)
         time.sleep(3)
         leader_para = ocf.thread_parameter('leader', '', '12', '7766554433221100', False)
-        leader_para.setnetworkname('OpenThread-ESP')
-        leader_para.setpanid('0x1234')
-        leader_para.setextpanid('dead00beef00cafe')
-        leader_para.setnetworkkey('aabbccddeeff00112233445566778899')
-        leader_para.setpskc('104810e2315100afd6bc9215a6bfac53')
         ocf.joinThreadNetwork(leader, leader_para)
         ocf.wait(leader, 5)
-        output = sleepy_device.expect(pexpect.TIMEOUT, timeout=5)
-        assert not bool(fail_info.search(str(output)))
-        ocf.clean_buffer(sleepy_device)
-        sleepy_device.serial.hard_reset()
+        dataset = ocf.getDataset(leader)
+        ocf.execute_command(sleepy_device, 'mode -')
+        ocf.execute_command(sleepy_device, 'pollperiod 3000')
+        ocf.execute_command(sleepy_device, 'dataset set active ' + dataset)
+        ocf.execute_command(sleepy_device, 'ifconfig up')
+        ocf.execute_command(sleepy_device, 'thread start')
         info = sleepy_device.expect(r'(.+)detached -> child', timeout=20)[1].decode(errors='replace')
         assert not bool(fail_info.search(str(info)))
         info = sleepy_device.expect(r'(.+)PMU_SLEEP_PD_TOP: True', timeout=10)[1].decode(errors='replace')

examples/wifi/wifi_easy_connect/dpp-enrollee/main/dpp_enrollee_main.c

@@ -155,9 +155,9 @@ void dpp_enrollee_init(void)
     wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT();
     ESP_ERROR_CHECK(esp_wifi_init(&cfg));
 
+    ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_STA));
     ESP_ERROR_CHECK(esp_supp_dpp_init(dpp_enrollee_event_cb));
     ESP_ERROR_CHECK(dpp_enrollee_bootstrap());
-    ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_STA));
     ESP_ERROR_CHECK(esp_wifi_start());
 
     /* Waiting until either the connection is established (WIFI_CONNECTED_BIT) or connection failed for the maximum

tools/test_apps/system/panic/pytest_panic.py

@@ -778,10 +778,7 @@ def test_rtc_slow_reg2_execute_violation(dut: PanicTestDut, test_func_name: str)
 @pytest.mark.generic
 def test_irom_reg_write_violation(dut: PanicTestDut, test_func_name: str) -> None:
     dut.run_test_func(test_func_name)
-    if dut.target == 'esp32c6':
-        dut.expect_gme('Store access fault')
-    elif dut.target == 'esp32h2':
-        dut.expect_gme('Cache error')
+    dut.expect_gme('Store access fault')
     dut.expect_reg_dump(0)