2b36636f6f
fix(system): print warning if stray section is found while linking
2024-05-17 13:37:42 +04:00
8b93323da6
Merge branch 'upgrade_clang_toolchain' into 'master'
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Upgrade clang toolchain version to 'esp-17.0.1_20240419'
See merge request espressif/esp-idf!29811
2024-05-14 21:47:06 +08:00
8e524d708c
fix(coredump): fix buffer overflow inside esp_core_dump_get_summary
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Closes https://github.com/espressif/esp-idf/issues/13754
2024-05-07 06:49:28 +02:00
94fc3630f5
ci(panic): add flash encrypted coredump tests
2024-05-06 15:54:33 +02:00
551d91ea8a
ci(coredump): fix capture dram tests
2024-05-06 15:43:43 +02:00
86ef0c23fd
refactor(test): Change clang build tests app name
2024-05-03 16:55:18 +03:00
57f61d2311
feat(tools): Update Clang version to esp-17.0.1_20240419
2024-05-03 16:55:13 +03:00
8b418d4b09
feat(esp_system): Print backtrace for both CPUs when cache error does not determine CPU
2024-04-30 15:20:58 +03:00
3b8191cf5d
feat(coredump): save .bss, .data and .heap sections to the elf file
2024-04-23 19:07:51 +03:00
6f2de1fb23
fix(system): esp32p4: fix mepc when load/store failure occurred
2024-04-18 19:49:19 +04:00
842b6a1dc4
Merge branch 'bugfix/p4_ulp_wakeup' into 'master'
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fix(ulp): fixed lp-core not booting during sleep
Closes IDF-9407
See merge request espressif/esp-idf!30296
2024-04-18 16:23:16 +08:00
1fa59c442b
fix(ulp): fixed lp-core not booting during sleep
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LP core was unable to boot when system was in deepsleep.
This was due to lp uart init in LP rom using XTAL as clk source,
which is normally powered down during sleep.
This would cause lp uart to get stuck while printing ROM output,
and the app would never boot.
Also fixed wrong wakeup cause used by HP core for ULP wake up
2024-04-18 11:36:30 +08:00
8a66e059e9
Merge branch 'feature/sdmmc_p4_psram' into 'master'
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feat(sdmmc): add support for PSRAM DMA
Closes IDF-9662
See merge request espressif/esp-idf!30044
2024-04-17 18:10:00 +08:00
545203f1c8
change(ci): split test_apps build-test-rules, add missing code owners
2024-04-17 11:54:33 +02:00
c9efc9cc83
Merge branch 'bugfix/p4_reserved_rtc_mem' into 'master'
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fix(rtc_memory): fix conflict between LP-ROM and RTC reserved
Closes IDF-9408
See merge request espressif/esp-idf!30012
2024-04-17 16:45:57 +08:00
4533f16c34
fix(rtc_memory): fix conflict between LP-ROM and RTC reserved
2024-04-17 13:37:56 +08:00
b6c8a139be
Merge branch 'feature/linux_improve_delay_func' into 'master'
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feat(esp_rom): Improves esp_rom_delay_us for linux target
See merge request espressif/esp-idf!30217
2024-04-16 14:44:21 +08:00
024b040300
test(memprot): enable memory protection tests for P4
2024-04-14 21:16:42 +05:30
49b4bc175e
feat(sdmmc): add support for PSRAM DMA on ESP32-P4
2024-04-12 12:56:18 +02:00
b3d1b1783b
feat(esp_rom): Improves esp_rom_delay_us for linux target
2024-04-12 12:52:38 +03:00
d9a6ae2b3c
Merge branch 'refactor/simplify_mock_build_tests' into 'master'
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refactor(cmock): simplified mock build tests
See merge request espressif/esp-idf!30038
2024-04-12 16:09:39 +08:00
483b4cd65b
ci(coredump): enable custom stack tests for riscv chips
2024-04-09 13:36:30 +08:00
432864e917
Merge branch 'ci/enable_c5_mp_ci_jobs' into 'master'
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ci(esp32c5mp): enable esp32c5 build on CI
See merge request espressif/esp-idf!29895
2024-04-08 12:16:16 +08:00
65b1fd33d3
ci(esp32c5mp): disable the unsupported tests
2024-04-07 12:13:29 +08:00
51f6bb8931
refactor(cmock): simplified mock build tests
2024-04-04 16:14:13 +02:00
7d13f8210f
ci: fix pytest generic env markers
2024-04-03 18:10:43 +08:00
48503dd39f
fix(esp_hw_support): Fix the flash I/DROM region PMP protection
2024-04-02 18:41:07 +05:30
8da9eb5168
Merge branch 'ci/reenable_bootloader_sections_test_esp32c2' into 'master'
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ci(system): re-enable bootloader_sections test for ESP32-C2
See merge request espressif/esp-idf!29852
2024-04-01 23:13:00 +08:00
b8a254f33f
test(storage): fixed failing c-file api test
2024-04-01 15:14:22 +08:00
d434034513
Merge branch 'bugfix/storage_spelling' into 'master'
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fix(storage,esp_pm): spelling fixes by codespell pre-commit hook
See merge request espressif/esp-idf!29898
2024-03-29 11:59:48 +08:00
5d6c56c20d
Merge branch 'fix/unused_mmap_include' into 'master'
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fix(all): remove unused header includes
See merge request espressif/esp-idf!29816
2024-03-29 10:20:08 +08:00
10cc15b150
fix(storage): applied spelling fixes by codespell pre-commit hook
2024-03-28 13:00:54 +01:00
e84c7f00a5
Merge branch 'feat/c6lite_c61_ci_header_tmp_app' into 'master'
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feat(esp32c61): ci enable header check (stage 7/8)
See merge request espressif/esp-idf!29775
2024-03-28 11:45:20 +08:00
535afdd7f4
feat(esp32c61): ci enable header check, fix c61 build
2024-03-27 19:39:59 +08:00
a79c6f7f67
fix(esp_hw_support): clear reserved interrupts that are not applicable for each target
2024-03-27 16:21:25 +08:00
ce2ce972b8
ci(system): re-enable bootloader_sections test for ESP32-C2
2024-03-26 16:04:09 +01:00
313c4f2cdc
fix(all): remove unused header includes
2024-03-25 13:58:40 +08:00
cb82161dae
feat(system): esp32p4: support panic tests
2024-03-21 15:36:36 +04:00
e4aa326c3a
feat(log): Added PRIuSIZE printf formatter macro
2024-03-20 16:41:22 +08:00
85c2daee5b
test(esp_intr_dump): Enable test for esp32p4
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Added back intr_dump test on esp32p4 target.
Added esp32p4.txt expected output file containing
the list of interrupts.
2024-03-14 11:35:24 +01:00
3f76aca0a3
Merge branch 'contrib/github_pr_13256' into 'master'
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Use __builtin_unreachable in HAL_ASSERT no-assert mode (GitHub PR)
Closes IDFGH-12202
See merge request espressif/esp-idf!29237
2024-03-06 18:45:29 +08:00
efc3f9fa88
Merge branch 'bugfix/rom_systimer_config' into 'master'
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fix(rom): fixed systimer always using ROM implementation
See merge request espressif/esp-idf!29354
2024-03-06 12:26:06 +08:00
be8033701c
fix(hal): use __builtin_unreachable in no-assert mode
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otherwise due to esp-idf using -Werror, we can get errors in code which
uses HAL_ASSERT if for example the compiler believes that a variable is
used uninitialised, or similar.
Inspired by https://github.com/espressif/esp-idf/pull/13256
2024-03-06 11:50:32 +08:00
b809267359
fix(rom): fixed systimer always using ROM implementation
2024-03-06 09:47:12 +08:00
43c604f145
Merge branch 'feature/move_efuse_related_inits_into_component' into 'master'
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feat(efuse): Move efuse-related init steps into the component
Closes IDF-8759 and IDF-8761
See merge request espressif/esp-idf!28422
2024-03-04 17:34:44 +08:00
f9800e0726
feat(efuse): Move efuse-related init steps into the component
2024-03-01 21:07:03 +02:00
e18fd01d0d
Merge branch 'fix/pmp_idcache_reg_prot' into 'master'
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fix(esp_hw_support): Fix the I/DCACHE region PMP protection
See merge request espressif/esp-idf!28525
2024-02-29 21:39:11 +08:00
fdb7a43752
Merge branch 'feature/esp32p4_concontiguous_mem_mvp' into 'master'
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feat(esp_system): allow .bss to spill over into L2MEM above 0x4ff40000 on P4
See merge request espressif/esp-idf!28783
2024-02-29 16:28:13 +08:00
824c8e0593
feat(esp_system): allow .bss to spill over into L2MEM above 0x4ff40000
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This commit introduce SOC_MEM_NON_CONTIGUOUS_SRAM flag (that enebled for
esp32p4). If SOC_MEM_NON_CONTIGUOUS_SRAM is enabled:
- LDFLAGS+=--enable-non-contiguous-regions
- ldgen.py replaces "arrays[*]" from sections.ld.in with objects under
SURROUND keyword. (e.g. from linker.lf: data -> dram0_data SURROUND(foo))
- "mapping[*]" - refers to all other data
If SOC_MEM_NON_CONTIGUOUS_SRAM, sections.ld.in file should contain at
least one block of code like this (otherwise it does not make sense):
.dram0.bss (NOLOAD) :
{
arrays[dram0_bss]
mapping[dram0_bss]
} > sram_low
.dram1.bss (NOLOAD) :
{
/* do not place here arrays[dram0_bss] because it may be splited
* between segments */
mapping[dram0_bss]
} > sram_high
2024-02-28 19:41:25 +04:00
87e2d842ab
change(console): Add build test for no console output
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This commit adds a build test to test the scenario where both the primary and
secondary console outputs are disabled by Kconfig.
2024-02-28 20:39:52 +08:00
Alexey Lapshin