feat(esp32c5): support to run hello world on esp32c5 beta3

2023-12-18 20:43:06 +08:00 · 2023-12-18 20:43:06 +08:00 · 96a4ead083
commit 96a4ead083
--- a/1
+++ b/1
@ -118,7 +118,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
        default "y" if IDF_TARGET="esp32c5"
        select FREERTOS_UNICORE
        select IDF_TARGET_ARCH_RISCV
-        select IDF_ENV_BRINGUP

    config IDF_TARGET_ESP32P4
        bool
--- a/components/esp_driver_uart/src/uart.c
+++ b/components/esp_driver_uart/src/uart.c
@ -627,7 +627,7 @@ static bool uart_try_set_iomux_pin(uart_port_t uart_num, int io_num, uint32_t id
            gpio_iomux_in(io_num, upin->signal);
        }
    }
-#if (SOC_UART_LP_NUM >= 1)
+#if (SOC_UART_LP_NUM >= 1) && (SOC_RTCIO_PIN_COUNT >= 1)
    else {
        if (upin->input) {
            rtc_gpio_set_direction(io_num, RTC_GPIO_MODE_INPUT_ONLY);
--- a/components/esp_hw_support/Kconfig
+++ b/components/esp_hw_support/Kconfig
@ -245,6 +245,7 @@ menu "Hardware Settings"
    rsource "./dma/Kconfig.dma"

    menu "Main XTAL Config"
+        # TODO: IDF-8943
        choice XTAL_FREQ_SEL
            prompt "Main XTAL frequency"
            default XTAL_FREQ_48 if SOC_XTAL_SUPPORT_48M
--- a/components/esp_system/fpga_overrides_clk.c
+++ b/components/esp_system/fpga_overrides_clk.c
@ -29,8 +29,6 @@
 #include "esp32p4/rom/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32C5
 #include "esp32c5/rom/rtc.h"
-#include "hal/clk_tree_ll.h"
-#include "soc/clk_tree_defs.h"
 #endif
 #include "esp_log.h"
 #include "esp_rom_sys.h"
@ -59,12 +57,6 @@ void bootloader_clock_configure(void)
    REG_WRITE(RTC_APB_FREQ_REG, (apb_freq_hz >> 12) | ((apb_freq_hz >> 12) << 16));
 #endif
    REG_WRITE(RTC_XTAL_FREQ_REG, (xtal_freq_mhz) | ((xtal_freq_mhz) << 16));
-
-#if CONFIG_IDF_TARGET_ESP32C5
-    // The default slow clock source RC_SLOW is unusable on c5, switch to SOC_RTC_SLOW_CLK_SRC_RC32K instead
-    clk_ll_rtc_slow_set_src(SOC_RTC_SLOW_CLK_SRC_RC32K);
-    esp_rom_delay_us(SOC_DELAY_RTC_SLOW_CLK_SWITCH);
-#endif
 }

 void esp_clk_init(void)
--- a/components/esp_system/panic.c
+++ b/components/esp_system/panic.c
@ -79,7 +79,7 @@ static wdt_hal_context_t rtc_wdt_ctx = RWDT_HAL_CONTEXT_DEFAULT();

 #if !CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT

-#if CONFIG_ESP_CONSOLE_UART
+#if CONFIG_ESP_CONSOLE_UART && SOC_UART_SUPPORTED
 static uart_hal_context_t s_panic_uart = { .dev = CONFIG_ESP_CONSOLE_UART_NUM == 0 ? &UART0 :&UART1 };

 static void panic_print_char_uart(const char c)
@ -122,7 +122,7 @@ static void panic_print_char_usb_serial_jtag(const char c)

 void panic_print_char(const char c)
 {
-#if CONFIG_ESP_CONSOLE_UART
+#if CONFIG_ESP_CONSOLE_UART && SOC_UART_SUPPORTED
    panic_print_char_uart(c);
 #endif
 #if CONFIG_ESP_CONSOLE_USB_CDC
--- a/components/hal/esp32c5/include/hal/lp_aon_ll.h
+++ b/components/hal/esp32c5/include/hal/lp_aon_ll.h
@ -26,9 +26,7 @@ extern "C" {
 */
 static inline  uint32_t lp_aon_ll_ext1_get_wakeup_status(void)
 {
-    // TODO: [ESP32C5] IDF-8638, IDF-8640
-    // return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status);
-    return (uint32_t)0;
+    return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status);
 }

 /**
@ -36,8 +34,7 @@ static inline  uint32_t lp_aon_ll_ext1_get_wakeup_status(void)
 */
 static inline void lp_aon_ll_ext1_clear_wakeup_status(void)
 {
-    // TODO: [ESP32C5] IDF-8638, IDF-8640
-    // HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status_clr, 1);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status_clr, 1);
 }

 /**
@ -50,18 +47,23 @@ static inline void lp_aon_ll_ext1_clear_wakeup_status(void)
 */
 static inline void lp_aon_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t level_mask)
 {
-    // TODO: [ESP32C5] IDF-8638, IDF-8640
-    // HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, io_mask);
-    // HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, level_mask);
+    uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
+    wakeup_sel_mask |= io_mask;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, wakeup_sel_mask);
+
+    uint32_t wakeup_level_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv);
+    wakeup_level_mask |= io_mask & level_mask;
+    wakeup_level_mask &= ~(io_mask & ~level_mask);
+
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, wakeup_level_mask);
 }

 /**
 * @brief Clear all ext1 wakup-source setting
 */
-static inline void lp_aon_ll_ext1_clear_wakeup_pins(void)
+static inline  void lp_aon_ll_ext1_clear_wakeup_pins(void)
 {
-    // TODO: [ESP32C5] IDF-8638, IDF-8640
-    // HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, 0);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, 0);
 }

 /**
@ -71,9 +73,7 @@ static inline void lp_aon_ll_ext1_clear_wakeup_pins(void)
 */
 static inline  uint32_t lp_aon_ll_ext1_get_wakeup_pins(void)
 {
-    // TODO: [ESP32C5] IDF-8638, IDF-8640
-    // return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
-    return (uint32_t)0;
+    return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
 }


@ -84,12 +84,12 @@ static inline  uint32_t lp_aon_ll_ext1_get_wakeup_pins(void)
 */
 static inline  void lp_aon_ll_inform_wakeup_type(bool dslp)
 {
-    // TODO: [ESP32C5] IDF-8638, IDF-8640
-    // if (dslp) {
-    //     REG_SET_BIT(SLEEP_MODE_REG, BIT(0));    /* Tell rom to run deep sleep wake stub */
-    //     // } else {
-    //     REG_CLR_BIT(SLEEP_MODE_REG, BIT(0));    /* Tell rom to run light sleep wake stub */
-    // }
+    if (dslp) {
+        REG_SET_BIT(SLEEP_MODE_REG, BIT(0));    /* Tell rom to run deep sleep wake stub */
+
+    } else {
+        REG_CLR_BIT(SLEEP_MODE_REG, BIT(0));    /* Tell rom to run light sleep wake stub */
+    }
 }

 #ifdef __cplusplus
--- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
@ -83,6 +83,10 @@ config SOC_CPU_HAS_FLEXIBLE_INTC
    bool
    default y

+config SOC_INT_PLIC_SUPPORTED
+    bool
+    default n
+
 config SOC_INT_CLIC_SUPPORTED
    bool
    default y
--- a/components/soc/esp32c5/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/include/soc/soc_caps.h
@ -141,6 +141,7 @@
 #define SOC_CPU_CORES_NUM               (1U)
 #define SOC_CPU_INTR_NUM                32
 #define SOC_CPU_HAS_FLEXIBLE_INTC       1
+#define SOC_INT_PLIC_SUPPORTED          0       //riscv platform-level interrupt controller
 #define SOC_INT_CLIC_SUPPORTED          1
 #define SOC_INT_HW_NESTED_SUPPORTED     1       // Support for hardware interrupts nesting
 #define SOC_BRANCH_PREDICTOR_SUPPORTED  1