kopia lustrzana https://github.com/espressif/esp-idf
feat(esp32c5): support to build hello world on esp32c5 beta3
laokaiyao
rodzic
e0fdae294b
commit
11e19f40b9
2
Kconfig
2
Kconfig
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@ -145,7 +145,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
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default 0x000D if IDF_TARGET_ESP32C6
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default 0x0010 if IDF_TARGET_ESP32H2
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default 0x0012 if IDF_TARGET_ESP32P4
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default 0x0013 if IDF_TARGET_ESP32C5
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default 0x0011 if IDF_TARGET_ESP32C5
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default 0xFFFF
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@ -6,7 +6,7 @@ menu "Bootloader config"
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hex
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default 0x1000 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2
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# the first 2 sectors are reserved for the key manager with AES-XTS (flash encryption) purpose
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default 0x2000 if IDF_TARGET_ESP32P4
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default 0x2000 if IDF_TARGET_ESP32P4 || IDF_TARGET_ESP32C5
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default 0x0
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help
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Offset address that 2nd bootloader will be flashed to.
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@ -0,0 +1,255 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** Simplified memory map for the bootloader.
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* Make sure the bootloader can load into main memory without overwriting itself.
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*
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* ESP32-5 ROM static data usage is as follows:
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* - 0x4086ad08 - 0x4087c610: Shared buffers, used in UART/USB/SPI download mode only
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* - 0x4087c610 - 0x4087e610: PRO CPU stack, can be reclaimed as heap after RTOS startup
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* - 0x4087e610 - 0x40880000: ROM .bss and .data (not easily reclaimable)
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*
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* The 2nd stage bootloader can take space up to the end of ROM shared
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* buffers area (0x4087c610).
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*/
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/* We consider 0x4087c610 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
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* and work out iram_seg and iram_loader_seg addresses from there, backwards.
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*/
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/* These lengths can be adjusted, if necessary: */
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bootloader_usable_dram_end = 0x4087c610;
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bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
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bootloader_dram_seg_len = 0x5000;
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bootloader_iram_loader_seg_len = 0x7000;
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bootloader_iram_seg_len = 0x2200;
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/* Start of the lower region is determined by region size and the end of the higher region */
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bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
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bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
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bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len;
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bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
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MEMORY
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{
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iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
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iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
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dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
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}
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/* The app may use RAM for static allocations up to the start of iram_loader_seg.
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* If you have changed something above and this assert fails:
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* 1. Check what the new value of bootloader_iram_loader_seg start is.
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* 2. Update the value in this assert.
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* 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c5/memory.ld.in to the same value.
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*/
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ASSERT(bootloader_iram_loader_seg_start == 0x4086E610, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
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/* Default entry point: */
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ENTRY(call_start_cpu0);
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SECTIONS
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{
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.iram_loader.text :
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{
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. = ALIGN (16);
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_loader_text_start = ABSOLUTE(.);
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*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
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*liblog.a:(.literal .text .literal.* .text.*)
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/* we use either libgcc or compiler-rt, so put similar entries for them here */
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*libgcc.a:(.literal .text .literal.* .text.*)
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*libclang_rt.builtins.a:(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
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*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
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*libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
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*libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
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*libspi_flash.a:*.*(.literal .text .literal.* .text.*)
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*libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
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*libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
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*libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
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*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
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*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
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*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
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*libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
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*libefuse.a:*.*(.literal .text .literal.* .text.*)
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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_loader_text_end = ABSOLUTE(.);
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} > iram_loader_seg
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.iram.text :
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{
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. = ALIGN (16);
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*(.entry.text)
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*(.init.literal)
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*(.init)
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} > iram_seg
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/* Shared RAM */
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.dram0.bss (NOLOAD) :
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{
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. = ALIGN (8);
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_dram_start = ABSOLUTE(.);
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_bss_start = ABSOLUTE(.);
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*(.dynsbss)
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*(.sbss)
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*(.sbss.*)
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*(.gnu.linkonce.sb.*)
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*(.scommon)
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*(.sbss2)
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*(.sbss2.*)
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*(.gnu.linkonce.sb2.*)
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*(.dynbss)
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*(.bss)
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*(.bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN (8);
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_bss_end = ABSOLUTE(.);
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} > dram_seg
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.dram0.bootdesc : ALIGN(0x10)
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{
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_data_start = ABSOLUTE(.);
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*(.data_bootloader_desc .data_bootloader_desc.*) /* Should be the first. Bootloader version info. DO NOT PUT ANYTHING BEFORE IT! */
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} > dram_seg
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.dram0.data :
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{
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.d.*)
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*(.data1)
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(.gnu.linkonce.s2.*)
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*(.jcr)
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_data_end = ABSOLUTE(.);
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} > dram_seg
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.dram0.rodata :
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{
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_rodata_start = ABSOLUTE(.);
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*(.rodata)
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*(.rodata.*)
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*(.gnu.linkonce.r.*)
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*(.rodata1)
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*(.sdata2 .sdata2.* .srodata .srodata.*)
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__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
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*(.xt_except_table)
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*(.gcc_except_table)
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*(.gnu.linkonce.e.*)
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*(.gnu.version_r)
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*(.eh_frame)
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. = (. + 3) & ~ 3;
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/* C++ constructor and destructor tables, properly ordered: */
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__init_array_start = ABSOLUTE(.);
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KEEP (*crtbegin.*(.ctors))
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KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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__init_array_end = ABSOLUTE(.);
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KEEP (*crtbegin.*(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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/* C++ exception handlers table: */
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__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
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*(.xt_except_desc)
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*(.gnu.linkonce.h.*)
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__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
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*(.xt_except_desc_end)
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*(.dynamic)
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*(.gnu.version_d)
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_rodata_end = ABSOLUTE(.);
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/* Literals are also RO data. */
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_lit4_start = ABSOLUTE(.);
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*(*.lit4)
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*(.lit4.*)
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*(.gnu.linkonce.lit4.*)
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_lit4_end = ABSOLUTE(.);
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. = ALIGN(4);
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_dram_end = ABSOLUTE(.);
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} > dram_seg
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.iram.text :
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{
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_stext = .;
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_text_start = ABSOLUTE(.);
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*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.iram .iram.*) /* catch stray IRAM_ATTR */
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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/** CPU will try to prefetch up to 16 bytes of
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* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
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* safe access to up to 16 bytes after the last real instruction, add
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* dummy bytes to ensure this
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*/
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. += 16;
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_text_end = ABSOLUTE(.);
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_etext = .;
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} > iram_seg
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}
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/**
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* Appendix: Memory Usage of ROM bootloader
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*
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* 0x4086ad08 ------------------> _dram0_0_start
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* | |
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* | |
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* | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h
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* | |
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* | |
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* 0x4087c610 ------------------> __stack_sentry
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* | |
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* | | 2. Startup pro cpu stack (freed when IDF app is running)
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* | |
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* 0x4087e610 ------------------> __stack (pro cpu)
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* | |
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* | |
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* | | 3. Shared memory only used in startup code or nonos/early boot*
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* | | (can be freed when IDF runs)
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* | |
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* | |
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* 0x4087f564 ------------------> _dram0_rtos_reserved_start
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* | |
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* | |
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* | | 4. Shared memory used in startup code and when IDF runs
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* | |
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* | |
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* 0x4087fab0 ------------------> _dram0_rtos_reserved_end
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* | |
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* 0x4087fce8 ------------------> _data_start_interface
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* | |
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* | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
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* | |
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* 0x40880000 ------------------> _data_end_interface
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*/
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@ -0,0 +1,6 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* No definition for ESP32-C5 target */
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@ -0,0 +1,283 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdbool.h>
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#include <assert.h>
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#include "string.h"
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#include "sdkconfig.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "esp_rom_gpio.h"
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#include "esp_rom_efuse.h"
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#include "esp32c5/rom/spi_flash.h"
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#include "esp32c5/rom/efuse.h"
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#include "soc/gpio_periph.h"
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#include "soc/efuse_reg.h"
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#include "soc/spi_reg.h"
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#include "soc/spi_mem_reg.h"
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#include "soc/soc_caps.h"
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#include "flash_qio_mode.h"
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#include "bootloader_flash_config.h"
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#include "bootloader_common.h"
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#include "bootloader_flash_priv.h"
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#include "bootloader_init.h"
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#include "hal/mmu_hal.h"
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#include "hal/mmu_ll.h"
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#include "hal/cache_hal.h"
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#include "hal/cache_ll.h"
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void bootloader_flash_update_id()
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{
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esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
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chip->device_id = bootloader_read_flash_id();
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}
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void IRAM_ATTR bootloader_flash_cs_timing_config()
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{
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SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
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SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
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SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
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}
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void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
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{
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uint32_t spi_clk_div = 0;
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switch (pfhdr->spi_speed) {
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case ESP_IMAGE_SPI_SPEED_DIV_1:
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spi_clk_div = 1;
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break;
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case ESP_IMAGE_SPI_SPEED_DIV_2:
|
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spi_clk_div = 2;
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break;
|
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case ESP_IMAGE_SPI_SPEED_DIV_3:
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spi_clk_div = 3;
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break;
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case ESP_IMAGE_SPI_SPEED_DIV_4:
|
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spi_clk_div = 4;
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break;
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default:
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break;
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}
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esp_rom_spiflash_config_clk(spi_clk_div, 0);
|
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}
|
||||
|
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static const char *TAG = "boot.esp32c5";
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|
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void IRAM_ATTR bootloader_configure_spi_pins(int drv)
|
||||
{
|
||||
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
|
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uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
|
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uint8_t d_gpio_num = SPI_D_GPIO_NUM;
|
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uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
|
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uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
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uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
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esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
|
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esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
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esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
|
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esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
|
||||
}
|
||||
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static void update_flash_config(const esp_image_header_t *bootloader_hdr)
|
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{
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uint32_t size;
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switch (bootloader_hdr->spi_size) {
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||||
case ESP_IMAGE_FLASH_SIZE_1MB:
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size = 1;
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||||
break;
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||||
case ESP_IMAGE_FLASH_SIZE_2MB:
|
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size = 2;
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_4MB:
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size = 4;
|
||||
break;
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||||
case ESP_IMAGE_FLASH_SIZE_8MB:
|
||||
size = 8;
|
||||
break;
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||||
case ESP_IMAGE_FLASH_SIZE_16MB:
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size = 16;
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break;
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default:
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||||
size = 2;
|
||||
}
|
||||
// Set flash chip size
|
||||
esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode
|
||||
}
|
||||
|
||||
static void print_flash_info(const esp_image_header_t *bootloader_hdr)
|
||||
{
|
||||
ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
|
||||
ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
|
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ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
|
||||
ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
|
||||
ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
|
||||
|
||||
const char *str;
|
||||
switch (bootloader_hdr->spi_speed) {
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_2:
|
||||
str = "40MHz";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_3:
|
||||
str = "26.7MHz";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_4:
|
||||
str = "20MHz";
|
||||
break;
|
||||
case ESP_IMAGE_SPI_SPEED_DIV_1:
|
||||
str = "80MHz";
|
||||
break;
|
||||
default:
|
||||
str = "20MHz";
|
||||
break;
|
||||
}
|
||||
ESP_EARLY_LOGI(TAG, "SPI Speed : %s", str);
|
||||
|
||||
/* SPI mode could have been set to QIO during boot already,
|
||||
so test the SPI registers not the flash header */
|
||||
esp_rom_spiflash_read_mode_t spi_mode = bootloader_flash_get_spi_mode();
|
||||
switch (spi_mode) {
|
||||
case ESP_ROM_SPIFLASH_QIO_MODE:
|
||||
str = "QIO";
|
||||
break;
|
||||
case ESP_ROM_SPIFLASH_QOUT_MODE:
|
||||
str = "QOUT";
|
||||
break;
|
||||
case ESP_ROM_SPIFLASH_DIO_MODE:
|
||||
str = "DIO";
|
||||
break;
|
||||
case ESP_ROM_SPIFLASH_DOUT_MODE:
|
||||
str = "DOUT";
|
||||
break;
|
||||
case ESP_ROM_SPIFLASH_FASTRD_MODE:
|
||||
str = "FAST READ";
|
||||
break;
|
||||
default:
|
||||
str = "SLOW READ";
|
||||
break;
|
||||
}
|
||||
ESP_EARLY_LOGI(TAG, "SPI Mode : %s", str);
|
||||
|
||||
switch (bootloader_hdr->spi_size) {
|
||||
case ESP_IMAGE_FLASH_SIZE_1MB:
|
||||
str = "1MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_2MB:
|
||||
str = "2MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_4MB:
|
||||
str = "4MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_8MB:
|
||||
str = "8MB";
|
||||
break;
|
||||
case ESP_IMAGE_FLASH_SIZE_16MB:
|
||||
str = "16MB";
|
||||
break;
|
||||
default:
|
||||
str = "2MB";
|
||||
break;
|
||||
}
|
||||
ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str);
|
||||
}
|
||||
|
||||
static void IRAM_ATTR bootloader_init_flash_configure(void)
|
||||
{
|
||||
bootloader_configure_spi_pins(1);
|
||||
bootloader_flash_cs_timing_config();
|
||||
}
|
||||
|
||||
static void bootloader_spi_flash_resume(void)
|
||||
{
|
||||
bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
|
||||
esp_rom_spiflash_wait_idle(&g_rom_flashchip);
|
||||
}
|
||||
|
||||
esp_err_t bootloader_init_spi_flash(void)
|
||||
{
|
||||
bootloader_init_flash_configure();
|
||||
bootloader_spi_flash_resume();
|
||||
bootloader_flash_unlock();
|
||||
|
||||
#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
|
||||
bootloader_enable_qio_mode();
|
||||
#endif
|
||||
|
||||
print_flash_info(&bootloader_image_hdr);
|
||||
|
||||
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
|
||||
update_flash_config(&bootloader_image_hdr);
|
||||
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
|
||||
|
||||
//ensure the flash is write-protected
|
||||
bootloader_enable_wp();
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
#if CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
||||
static void bootloader_flash_set_spi_mode(const esp_image_header_t* pfhdr)
|
||||
{
|
||||
esp_rom_spiflash_read_mode_t mode;
|
||||
switch(pfhdr->spi_mode) {
|
||||
case ESP_IMAGE_SPI_MODE_QIO:
|
||||
mode = ESP_ROM_SPIFLASH_QIO_MODE;
|
||||
break;
|
||||
case ESP_IMAGE_SPI_MODE_QOUT:
|
||||
mode = ESP_ROM_SPIFLASH_QOUT_MODE;
|
||||
break;
|
||||
case ESP_IMAGE_SPI_MODE_DIO:
|
||||
mode = ESP_ROM_SPIFLASH_DIO_MODE;
|
||||
break;
|
||||
case ESP_IMAGE_SPI_MODE_FAST_READ:
|
||||
mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
|
||||
break;
|
||||
case ESP_IMAGE_SPI_MODE_SLOW_READ:
|
||||
mode = ESP_ROM_SPIFLASH_SLOWRD_MODE;
|
||||
break;
|
||||
default:
|
||||
mode = ESP_ROM_SPIFLASH_DIO_MODE;
|
||||
}
|
||||
esp_rom_spiflash_config_readmode(mode);
|
||||
}
|
||||
|
||||
void bootloader_flash_hardware_init(void)
|
||||
{
|
||||
esp_rom_spiflash_attach(0, false);
|
||||
|
||||
//init cache hal
|
||||
cache_hal_init();
|
||||
//init mmu
|
||||
mmu_hal_init();
|
||||
// update flash ID
|
||||
bootloader_flash_update_id();
|
||||
// Check and run XMC startup flow
|
||||
esp_err_t ret = bootloader_flash_xmc_startup();
|
||||
assert(ret == ESP_OK);
|
||||
|
||||
/* Alternative of bootloader_init_spi_flash */
|
||||
// RAM app doesn't have headers in the flash. Make a default one for it.
|
||||
esp_image_header_t WORD_ALIGNED_ATTR hdr = {
|
||||
.spi_mode = ESP_IMAGE_SPI_MODE_DIO,
|
||||
.spi_speed = ESP_IMAGE_SPI_SPEED_DIV_2,
|
||||
.spi_size = ESP_IMAGE_FLASH_SIZE_2MB,
|
||||
};
|
||||
|
||||
bootloader_configure_spi_pins(1);
|
||||
bootloader_flash_set_spi_mode(&hdr);
|
||||
bootloader_flash_clock_config(&hdr);
|
||||
// TODO: set proper dummy output
|
||||
bootloader_flash_cs_timing_config();
|
||||
|
||||
bootloader_spi_flash_resume();
|
||||
bootloader_flash_unlock();
|
||||
|
||||
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
|
||||
update_flash_config(&hdr);
|
||||
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
|
||||
|
||||
//ensure the flash is write-protected
|
||||
bootloader_enable_wp();
|
||||
}
|
||||
#endif //CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
||||
|
|
@ -21,7 +21,7 @@ typedef enum {
|
|||
ESP_CHIP_ID_ESP32C6 = 0x000D, /*!< chip ID: ESP32-C6 */
|
||||
ESP_CHIP_ID_ESP32H2 = 0x0010, /*!< chip ID: ESP32-H2 */
|
||||
ESP_CHIP_ID_ESP32P4 = 0x0012, /*!< chip ID: ESP32-P4 */
|
||||
ESP_CHIP_ID_ESP32C5 = 0x0013, /*!< chip ID: ESP32-C5 */
|
||||
ESP_CHIP_ID_ESP32C5 = 0x0011, /*!< chip ID: ESP32-C5 */
|
||||
ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
|
||||
} __attribute__((packed)) esp_chip_id_t;
|
||||
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
#include "soc/chip_revision.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
|
||||
#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4// TODO: IDF-5645
|
||||
#if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_IDF_TARGET_ESP32C5 // TODO: IDF-5645
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#else
|
||||
#include "soc/lp_wdt_reg.h"
|
||||
|
|
@ -18,7 +18,7 @@
|
|||
#include "soc/pmu_reg.h"
|
||||
#endif
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C5
|
||||
#include "hal/clk_tree_ll.h"
|
||||
#endif
|
||||
#include "esp_rom_sys.h"
|
||||
|
|
@ -57,9 +57,18 @@ __attribute__((weak)) void bootloader_clock_configure(void)
|
|||
// RTC_SLOW clock source will be switched according to Kconfig selection at application startup
|
||||
clk_cfg.slow_clk_src = rtc_clk_slow_src_get();
|
||||
if (clk_cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_INVALID) {
|
||||
#if CONFIG_IDF_TARGET_ESP32C5
|
||||
clk_cfg.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC32K;
|
||||
#else
|
||||
clk_cfg.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32C5
|
||||
// RC150K can't do calibrate on esp32c5MPW so not use it
|
||||
clk_cfg.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC32K;
|
||||
#endif
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32C6
|
||||
// TODO: IDF-5781 Some of esp32c6 SOC_RTC_FAST_CLK_SRC_XTAL_D2 rtc_fast clock has timing issue
|
||||
// Force to use SOC_RTC_FAST_CLK_SRC_RC_FAST since 2nd stage bootloader
|
||||
|
|
@ -75,6 +84,12 @@ __attribute__((weak)) void bootloader_clock_configure(void)
|
|||
rtc_clk_init(clk_cfg);
|
||||
}
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32C5
|
||||
/* Configure clk mspi fast to 80m*/
|
||||
clk_ll_mspi_fast_set_divider(6);
|
||||
clk_ll_mspi_fast_sel_clk(MSPI_CLK_SRC_SPLL);
|
||||
#endif
|
||||
|
||||
/* As a slight optimization, if 32k XTAL was enabled in sdkconfig, we enable
|
||||
* it here. Usually it needs some time to start up, so we amortize at least
|
||||
* part of the start up time by enabling 32k XTAL early.
|
||||
|
|
@ -87,7 +102,13 @@ __attribute__((weak)) void bootloader_clock_configure(void)
|
|||
#endif // CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
|
||||
|
||||
// TODO: IDF-8938 Need refactor! Does not belong to clock configuration.
|
||||
#if CONFIG_IDF_TARGET_ESP32C6
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5
|
||||
#if CONFIG_IDF_TARGET_ESP32C5
|
||||
#define LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG LP_ANA_LP_INT_ENA_REG
|
||||
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA LP_ANA_BOD_MODE0_LP_INT_ENA
|
||||
#define LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG LP_ANA_LP_INT_CLR_REG
|
||||
#define LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR LP_ANA_BOD_MODE0_LP_INT_CLR
|
||||
#endif
|
||||
// CLR ENA
|
||||
CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_SUPER_WDT_INT_ENA); /* SWD */
|
||||
CLEAR_PERI_REG_MASK(LP_TIMER_LP_INT_ENA_REG, LP_TIMER_MAIN_TIMER_LP_INT_ENA); /* MAIN_TIMER */
|
||||
|
|
|
|||
|
|
@ -30,6 +30,9 @@ int bootloader_clock_get_rated_freq_mhz(void)
|
|||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
return 160;
|
||||
|
||||
#elif CONFIG_IDF_TARGET_ESP32C5
|
||||
return 160;
|
||||
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
//IDF-6570
|
||||
return 96;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include "sdkconfig.h"
|
||||
#include "soc/soc.h"
|
||||
#include "soc/pcr_reg.h"
|
||||
#include "soc/pmu_reg.h"
|
||||
#include "hal/regi2c_ctrl.h"
|
||||
#include "esp_log.h"
|
||||
|
||||
void bootloader_random_enable(void)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8626
|
||||
ESP_EARLY_LOGW("bootloader_random", "bootloader_random_enable() has not been implemented on C5 yet");
|
||||
}
|
||||
|
||||
void bootloader_random_disable(void)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8626
|
||||
ESP_EARLY_LOGW("bootloader_random", "bootloader_random_disable() has not been implemented on C5 yet");
|
||||
}
|
||||
|
|
@ -33,6 +33,13 @@
|
|||
#include "esp32c6/rom/crc.h"
|
||||
#include "esp32c6/rom/rtc.h"
|
||||
#include "esp32c6/rom/uart.h"
|
||||
#include "esp32c6/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C5
|
||||
#include "esp32c5/rom/efuse.h"
|
||||
#include "esp32c5/rom/crc.h"
|
||||
#include "esp32c5/rom/rtc.h"
|
||||
#include "esp32c5/rom/uart.h"
|
||||
#include "esp32c5/rom/secure_boot.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "esp32h2/rom/efuse.h"
|
||||
#include "esp32h2/rom/crc.h"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <stdbool.h>
|
||||
#include <string.h>
|
||||
#include <sys/param.h>
|
||||
#include "rom/ecdsa.h"
|
||||
|
||||
// TODO: [ESP32C5] IDF-8618 remove esp_log.h
|
||||
#include "esp_log.h"
|
||||
|
||||
#define ROM_FUNC_TYPECAST int(*)(const uint8_t*, const uint8_t*, int, const uint8_t*, uint8_t*)
|
||||
|
||||
extern uint32_t _rom_eco_version;
|
||||
int (*_rom_ets_ecdsa_verify)(const uint8_t*, const uint8_t*, int, const uint8_t*, uint8_t*);
|
||||
|
||||
/* On ESP32-C5, the ROM interface hasn't exposed ets_ecdsa_verify symbol, so for that we have defined
|
||||
* the function here and then jump to the absolute address in ROM.
|
||||
*
|
||||
* There is a possibility of updating the ROM in the future chip revisions without any major upgrades,
|
||||
* in that case, the same binary should work as is on the new chip revision. For that, we check the _rom_eco_version
|
||||
* and if its a newer one, we jump to the new ROM interface. These addresses won't change in the future
|
||||
*
|
||||
* ets_ecdsa_verify symbol will be present in the upcoming ROM ECO versions so even though we have defined it here,
|
||||
* linker will pick the symbol address from rom.ld file
|
||||
*/
|
||||
int ets_ecdsa_verify(const uint8_t *key, const uint8_t *sig, ECDSA_CURVE curve_id, const uint8_t *image_digest, uint8_t *verified_digest)
|
||||
{
|
||||
// if (_rom_eco_version == 0) {
|
||||
// _rom_ets_ecdsa_verify = (ROM_FUNC_TYPECAST)0x4001a824;
|
||||
// return _rom_ets_ecdsa_verify(key, sig, curve_id, image_digest, verified_digest);
|
||||
// } else {
|
||||
// _rom_ets_ecdsa_verify = (ROM_FUNC_TYPECAST)0x40001490;
|
||||
// return _rom_ets_ecdsa_verify(key, sig, curve_id, image_digest, verified_digest);
|
||||
// }
|
||||
// TODO: [ESP32C5] IDF-8618
|
||||
ESP_EARLY_LOGW("bootloader_ecdsa", "ets_ecdsa_verify() has not been implemented on C5 yet");
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,171 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_image_format.h"
|
||||
#include "flash_qio_mode.h"
|
||||
#include "esp_rom_gpio.h"
|
||||
#include "esp_rom_efuse.h"
|
||||
#include "esp_rom_uart.h"
|
||||
#include "esp_rom_sys.h"
|
||||
#include "esp_rom_spiflash.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
#include "soc/assist_debug_reg.h"
|
||||
#include "esp_cpu.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/spi_periph.h"
|
||||
#include "soc/cache_reg.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
#include "soc/pcr_reg.h"
|
||||
#include "esp32c5/rom/efuse.h"
|
||||
#include "esp32c5/rom/ets_sys.h"
|
||||
#include "esp32c5/rom/spi_flash.h"
|
||||
#include "bootloader_common.h"
|
||||
#include "bootloader_init.h"
|
||||
#include "bootloader_clock.h"
|
||||
#include "bootloader_flash_config.h"
|
||||
#include "bootloader_mem.h"
|
||||
#include "esp_private/regi2c_ctrl.h"
|
||||
// #include "soc/regi2c_lp_bias.h"
|
||||
// #include "soc/regi2c_bias.h"
|
||||
#include "bootloader_console.h"
|
||||
#include "bootloader_flash_priv.h"
|
||||
#include "bootloader_soc.h"
|
||||
#include "esp_private/bootloader_flash_internal.h"
|
||||
#include "esp_efuse.h"
|
||||
#include "hal/mmu_hal.h"
|
||||
#include "hal/cache_hal.h"
|
||||
#include "hal/clk_tree_ll.h"
|
||||
#include "soc/lp_wdt_reg.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
#include "hal/lpwdt_ll.h"
|
||||
#include "modem/modem_lpcon_reg.h"
|
||||
|
||||
static const char *TAG = "boot.esp32c5";
|
||||
|
||||
static void wdt_reset_cpu0_info_enable(void)
|
||||
{
|
||||
REG_SET_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_CLK_EN);
|
||||
REG_CLR_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_RST_EN);
|
||||
REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
|
||||
}
|
||||
|
||||
static void wdt_reset_info_dump(int cpu)
|
||||
{
|
||||
(void) cpu;
|
||||
// saved PC was already printed by the ROM bootloader.
|
||||
// nothing to do here.
|
||||
}
|
||||
|
||||
static void bootloader_check_wdt_reset(void)
|
||||
{
|
||||
int wdt_rst = 0;
|
||||
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
|
||||
if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 ||
|
||||
rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
|
||||
ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
|
||||
wdt_rst = 1;
|
||||
}
|
||||
if (wdt_rst) {
|
||||
// if reset by WDT dump info from trace port
|
||||
wdt_reset_info_dump(0);
|
||||
}
|
||||
wdt_reset_cpu0_info_enable();
|
||||
}
|
||||
|
||||
static void bootloader_super_wdt_auto_feed(void)
|
||||
{
|
||||
REG_WRITE(LP_WDT_SWD_WPROTECT_REG, LP_WDT_SWD_WKEY_VALUE);
|
||||
REG_SET_BIT(LP_WDT_SWD_CONFIG_REG, LP_WDT_SWD_AUTO_FEED_EN);
|
||||
REG_WRITE(LP_WDT_SWD_WPROTECT_REG, 0);
|
||||
}
|
||||
|
||||
static inline void bootloader_hardware_init(void)
|
||||
{
|
||||
/* Enable analog i2c master clock */
|
||||
SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
|
||||
SET_PERI_REG_MASK(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M);
|
||||
}
|
||||
|
||||
static inline void bootloader_ana_reset_config(void)
|
||||
{
|
||||
//Enable super WDT reset.
|
||||
// bootloader_ana_super_wdt_reset_config(true);
|
||||
//Enable BOD reset
|
||||
// bootloader_ana_bod_reset_config(true);
|
||||
}
|
||||
|
||||
esp_err_t bootloader_init(void)
|
||||
{
|
||||
esp_err_t ret = ESP_OK;
|
||||
|
||||
bootloader_hardware_init();
|
||||
bootloader_ana_reset_config();
|
||||
bootloader_super_wdt_auto_feed();
|
||||
|
||||
// In RAM_APP, memory will be initialized in `call_start_cpu0`
|
||||
#if !CONFIG_APP_BUILD_TYPE_RAM
|
||||
// protect memory region
|
||||
bootloader_init_mem();
|
||||
/* check that static RAM is after the stack */
|
||||
assert(&_bss_start <= &_bss_end);
|
||||
assert(&_data_start <= &_data_end);
|
||||
// clear bss section
|
||||
bootloader_clear_bss_section();
|
||||
#endif // !CONFIG_APP_BUILD_TYPE_RAM
|
||||
|
||||
// init eFuse virtual mode (read eFuses to RAM)
|
||||
#ifdef CONFIG_EFUSE_VIRTUAL
|
||||
ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!");
|
||||
#ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
|
||||
esp_efuse_init_virtual_mode_in_ram();
|
||||
#endif
|
||||
#endif
|
||||
// config clock
|
||||
bootloader_clock_configure();
|
||||
// initialize console, from now on, we can use esp_log
|
||||
bootloader_console_init();
|
||||
/* print 2nd bootloader banner */
|
||||
bootloader_print_banner();
|
||||
|
||||
#if !CONFIG_APP_BUILD_TYPE_RAM
|
||||
//init cache hal
|
||||
cache_hal_init();
|
||||
//init mmu
|
||||
mmu_hal_init();
|
||||
// update flash ID
|
||||
bootloader_flash_update_id();
|
||||
// Check and run XMC startup flow
|
||||
if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
|
||||
ESP_LOGE(TAG, "failed when running XMC startup flow, reboot!");
|
||||
return ret;
|
||||
}
|
||||
// read bootloader header
|
||||
if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
|
||||
return ret;
|
||||
}
|
||||
// read chip revision and check if it's compatible to bootloader
|
||||
if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
|
||||
return ret;
|
||||
}
|
||||
// initialize spi flash
|
||||
if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
|
||||
return ret;
|
||||
}
|
||||
#endif // !CONFIG_APP_BUILD_TYPE_RAM
|
||||
|
||||
// check whether a WDT reset happend
|
||||
bootloader_check_wdt_reset();
|
||||
// config WDT
|
||||
bootloader_config_wdt();
|
||||
// enable RNG early entropy source
|
||||
bootloader_enable_random();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include "bootloader_sha.h"
|
||||
#include <stdbool.h>
|
||||
#include <string.h>
|
||||
#include <assert.h>
|
||||
#include <sys/param.h>
|
||||
|
||||
#include "esp32c5/rom/sha.h"
|
||||
|
||||
static SHA_CTX ctx;
|
||||
|
||||
bootloader_sha256_handle_t bootloader_sha256_start()
|
||||
{
|
||||
// Enable SHA hardware
|
||||
ets_sha_enable();
|
||||
ets_sha_init(&ctx, SHA2_256);
|
||||
return &ctx; // Meaningless non-NULL value
|
||||
}
|
||||
|
||||
void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data, size_t data_len)
|
||||
{
|
||||
assert(handle != NULL);
|
||||
/* C5 secure boot key field consists of 1 byte of curve identifier and 64 bytes of ECDSA public key.
|
||||
* While verifying the signature block, we need to calculate the SHA of this key field which is of 65 bytes.
|
||||
* ets_sha_update handles it cleanly so we can safely remove the check:
|
||||
* assert(data_len % 4) == 0
|
||||
*/
|
||||
ets_sha_update(&ctx, data, data_len, false);
|
||||
}
|
||||
|
||||
void bootloader_sha256_finish(bootloader_sha256_handle_t handle, uint8_t *digest)
|
||||
{
|
||||
assert(handle != NULL);
|
||||
|
||||
if (digest == NULL) {
|
||||
bzero(&ctx, sizeof(ctx));
|
||||
return;
|
||||
}
|
||||
ets_sha_finish(&ctx, digest);
|
||||
}
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <stdbool.h>
|
||||
#include <assert.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/lp_analog_peri_reg.h"
|
||||
// TODO: [ESP32C5] IDF-8667 remove esp_log.h
|
||||
#include "esp_log.h"
|
||||
|
||||
void bootloader_ana_super_wdt_reset_config(bool enable)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8667
|
||||
ESP_EARLY_LOGW("bootloader", "bootloader_ana_super_wdt_reset_config() has not been implemented on C5 yet");
|
||||
}
|
||||
|
||||
void bootloader_ana_bod_reset_config(bool enable)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8667
|
||||
ESP_EARLY_LOGW("bootloader", "bootloader_ana_bod_reset_config() has not been implemented on C5 yet");
|
||||
}
|
||||
|
||||
//Not supported but common bootloader calls the function. Do nothing
|
||||
void bootloader_ana_clock_glitch_reset_config(bool enable)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8667
|
||||
(void)enable;
|
||||
}
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <strings.h>
|
||||
#include "esp_flash_encrypt.h"
|
||||
#include "esp_secure_boot.h"
|
||||
#include "esp_efuse.h"
|
||||
#include "esp_efuse_table.h"
|
||||
#include "esp_log.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
static __attribute__((unused)) const char *TAG = "secure_boot";
|
||||
|
||||
esp_err_t esp_secure_boot_enable_secure_features(void)
|
||||
{
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
|
||||
|
||||
#ifdef CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE
|
||||
ESP_LOGI(TAG, "Enabling Security download mode...");
|
||||
esp_err_t err = esp_efuse_enable_rom_secure_download_mode();
|
||||
if (err != ESP_OK) {
|
||||
ESP_LOGE(TAG, "Could not enable Security download mode...");
|
||||
return err;
|
||||
}
|
||||
#elif CONFIG_SECURE_DISABLE_ROM_DL_MODE
|
||||
ESP_LOGI(TAG, "Disable ROM Download mode...");
|
||||
esp_err_t err = esp_efuse_disable_rom_download_mode();
|
||||
if (err != ESP_OK) {
|
||||
ESP_LOGE(TAG, "Could not disable ROM Download mode...");
|
||||
return err;
|
||||
}
|
||||
#else
|
||||
ESP_LOGW(TAG, "UART ROM Download mode kept enabled - SECURITY COMPROMISED");
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
|
||||
ESP_LOGI(TAG, "Disable hardware & software JTAG...");
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG);
|
||||
esp_efuse_write_field_cnt(ESP_EFUSE_SOFT_DIS_JTAG, ESP_EFUSE_SOFT_DIS_JTAG[0]->bit_count);
|
||||
#else
|
||||
ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE);
|
||||
#endif
|
||||
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_EN);
|
||||
|
||||
#ifndef CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS
|
||||
bool rd_dis_now = true;
|
||||
#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED
|
||||
/* If flash encryption is not enabled yet then don't read-disable efuses yet, do it later in the boot
|
||||
when Flash Encryption is being enabled */
|
||||
rd_dis_now = esp_flash_encryption_enabled();
|
||||
#endif
|
||||
if (rd_dis_now) {
|
||||
ESP_LOGI(TAG, "Prevent read disabling of additional efuses...");
|
||||
esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_RD_DIS);
|
||||
}
|
||||
#else
|
||||
ESP_LOGW(TAG, "Allowing read disabling of additional efuses - SECURITY COMPROMISED");
|
||||
#endif
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
components/bootloader_support/test_apps/rtc_custom_section:
|
||||
enable:
|
||||
- if: SOC_RTC_MEM_SUPPORTED == 1
|
||||
- if: SOC_RTC_MEM_SUPPORTED == 1 and IDF_TARGET != "esp32c5"
|
||||
reason: this feature is supported on chips that have RTC memory
|
||||
disable:
|
||||
# TODO: [ESP32C5] IDF-8653
|
||||
|
|
|
|||
|
|
@ -5,6 +5,10 @@ if(${target} STREQUAL "linux")
|
|||
# future (TODO: IDF-8103)
|
||||
endif()
|
||||
|
||||
if(${target} STREQUAL "esp32c5")
|
||||
return() # Not support yet
|
||||
endif()
|
||||
|
||||
set(argtable_srcs argtable3/arg_cmd.c
|
||||
argtable3/arg_date.c
|
||||
argtable3/arg_dbl.c
|
||||
|
|
|
|||
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <esp_bit_defs.h>
|
||||
#include "esp_efuse.h"
|
||||
#include "esp_efuse_table.h"
|
||||
#include "esp_efuse_rtc_calib.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
|
||||
/**
|
||||
* @brief Get the signed value by the raw data that read from eFuse
|
||||
* @param data The raw data that read from eFuse
|
||||
* @param sign_bit The index of the sign bit, start from 0
|
||||
*/
|
||||
#define RTC_CALIB_GET_SIGNED_VAL(data, sign_bit) ((data & BIT##sign_bit) ? -(int)(data & ~BIT##sign_bit) : (int)data)
|
||||
|
||||
int esp_efuse_rtc_calib_get_ver(void)
|
||||
{
|
||||
uint32_t cali_version = 0;
|
||||
// TODO: [ESP32C5] IDF-8702
|
||||
abort();
|
||||
|
||||
return cali_version;
|
||||
}
|
||||
|
||||
uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8702
|
||||
abort();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int esp_efuse_rtc_calib_get_chan_compens(int version, uint32_t adc_unit, uint32_t adc_channel, int atten)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8702
|
||||
abort();
|
||||
return 0;
|
||||
}
|
||||
|
||||
esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, uint32_t adc_unit, int atten, uint32_t* out_digi, uint32_t* out_vol_mv)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8702
|
||||
abort();
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8727
|
||||
abort();
|
||||
// Currently calibration is not supported on ESP32-C5, IDF-5236
|
||||
*tsens_cal = 0;
|
||||
return ESP_OK;
|
||||
}
|
||||
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,187 @@
|
|||
|
||||
# field_name, | efuse_block, | bit_start, | bit_count, |comment #
|
||||
# | (EFUSE_BLK0 | (0..255) | (1-256) | #
|
||||
# | EFUSE_BLK1 | | | #
|
||||
# | ...) | | | #
|
||||
##########################################################################
|
||||
# !!!!!!!!!!! # // TODO: [ESP32C5] IDF-8674
|
||||
# After editing this file, run the command manually "idf.py efuse-common-table"
|
||||
# this will generate new source files, next rebuild all the sources.
|
||||
# !!!!!!!!!!! #
|
||||
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: 709e8ea096e8a03a10006d40d5451a49
|
||||
|
||||
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
|
||||
WR_DIS.CRYPT_DPA_ENABLE, EFUSE_BLK0, 1, 1, [] wr_dis of CRYPT_DPA_ENABLE
|
||||
WR_DIS.SWAP_UART_SDIO_EN, EFUSE_BLK0, 2, 1, [] wr_dis of SWAP_UART_SDIO_EN
|
||||
WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE
|
||||
WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG
|
||||
WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE
|
||||
WR_DIS.DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_SERIAL_JTAG
|
||||
WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD
|
||||
WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI
|
||||
WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE
|
||||
WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG
|
||||
WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
|
||||
WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL
|
||||
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
|
||||
WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
|
||||
WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
|
||||
WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
|
||||
WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
|
||||
WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
|
||||
WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
|
||||
WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
|
||||
WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [WR_DIS.DPA_SEC_LEVEL] wr_dis of SEC_DPA_LEVEL
|
||||
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN
|
||||
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
|
||||
WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 17, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
|
||||
WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW
|
||||
WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE
|
||||
WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DIRECT_BOOT
|
||||
WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
|
||||
WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
|
||||
WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
|
||||
WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL
|
||||
WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME
|
||||
WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION
|
||||
WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 19, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
|
||||
WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
|
||||
WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
|
||||
WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1
|
||||
WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
|
||||
WR_DIS.MAC_EXT, EFUSE_BLK0, 20, 1, [] wr_dis of MAC_EXT
|
||||
WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR
|
||||
WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR
|
||||
WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
|
||||
WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR
|
||||
WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR
|
||||
WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP
|
||||
WR_DIS.FLASH_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_TEMP
|
||||
WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR
|
||||
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
|
||||
WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
|
||||
WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB
|
||||
WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN1
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN2
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN3
|
||||
WR_DIS.ADC1_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN0
|
||||
WR_DIS.ADC1_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN1
|
||||
WR_DIS.ADC1_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN2
|
||||
WR_DIS.ADC1_CAL_VOL_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN3
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN0_CH0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH0
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN0_CH1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH1
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN0_CH2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH2
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN0_CH3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH3
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN0_CH4, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH4
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN0_CH5, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH5
|
||||
WR_DIS.ADC1_INIT_CODE_ATTEN0_CH6, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH6
|
||||
WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
|
||||
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
|
||||
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
|
||||
WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
|
||||
WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
|
||||
WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
|
||||
WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
|
||||
WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
|
||||
WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
|
||||
WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS
|
||||
WR_DIS.VDD_SPI_AS_GPIO, EFUSE_BLK0, 30, 1, [] wr_dis of VDD_SPI_AS_GPIO
|
||||
WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG
|
||||
RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10
|
||||
RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
|
||||
RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
|
||||
RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
|
||||
RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
|
||||
RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
|
||||
RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
|
||||
RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
|
||||
SWAP_UART_SDIO_EN, EFUSE_BLK0, 39, 1, [] Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not swapped
|
||||
DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled
|
||||
DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled
|
||||
DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0: enabled
|
||||
DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 43, 1, [] Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled
|
||||
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled
|
||||
SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 45, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled
|
||||
DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled
|
||||
JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled
|
||||
SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled
|
||||
DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled
|
||||
USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged
|
||||
VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned
|
||||
WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected
|
||||
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
|
||||
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key
|
||||
KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Represents the purpose of Key0
|
||||
KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Represents the purpose of Key1
|
||||
KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Represents the purpose of Key2
|
||||
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Represents the purpose of Key3
|
||||
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Represents the purpose of Key4
|
||||
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Represents the purpose of Key5
|
||||
SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, [DPA_SEC_LEVEL] Represents the spa secure level by configuring the clock random divide mode
|
||||
CRYPT_DPA_ENABLE, EFUSE_BLK0, 114, 1, [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled
|
||||
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled
|
||||
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled
|
||||
FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
|
||||
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled
|
||||
DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled
|
||||
DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [DIS_USB_PRINT] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled
|
||||
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled
|
||||
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled
|
||||
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"}
|
||||
FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced
|
||||
SECURE_VERSION, EFUSE_BLK0, 142, 16, [] Represents the version used by ESP-IDF anti-rollback feature
|
||||
SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 158, 1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled
|
||||
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, [] Disables check of wafer version major
|
||||
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, [] Disables check of blk version major
|
||||
MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address
|
||||
MAC_EXT, EFUSE_BLK1, 56, 8, [] Stores the extended bits of MAC address
|
||||
, EFUSE_BLK1, 48, 8, [] Stores the extended bits of MAC address
|
||||
WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 4, []
|
||||
WAFER_VERSION_MAJOR, EFUSE_BLK1, 118, 2, []
|
||||
PKG_VERSION, EFUSE_BLK1, 120, 3, [] Package version
|
||||
BLK_VERSION_MINOR, EFUSE_BLK1, 123, 3, [] BLK_VERSION_MINOR of BLOCK2
|
||||
BLK_VERSION_MAJOR, EFUSE_BLK1, 126, 2, [] BLK_VERSION_MAJOR of BLOCK2
|
||||
FLASH_CAP, EFUSE_BLK1, 128, 3, []
|
||||
FLASH_TEMP, EFUSE_BLK1, 131, 2, []
|
||||
FLASH_VENDOR, EFUSE_BLK1, 133, 3, []
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
|
||||
TEMP_CALIB, EFUSE_BLK2, 128, 9, [] Temperature calibration data
|
||||
OCODE, EFUSE_BLK2, 137, 8, [] ADC OCode
|
||||
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 145, 10, [] ADC1 init code at atten0
|
||||
ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 155, 10, [] ADC1 init code at atten1
|
||||
ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 165, 10, [] ADC1 init code at atten2
|
||||
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 175, 10, [] ADC1 init code at atten3
|
||||
ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 185, 10, [] ADC1 calibration voltage at atten0
|
||||
ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 195, 10, [] ADC1 calibration voltage at atten1
|
||||
ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 205, 10, [] ADC1 calibration voltage at atten2
|
||||
ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 215, 10, [] ADC1 calibration voltage at atten3
|
||||
ADC1_INIT_CODE_ATTEN0_CH0, EFUSE_BLK2, 225, 4, [] ADC1 init code at atten0 ch0
|
||||
ADC1_INIT_CODE_ATTEN0_CH1, EFUSE_BLK2, 229, 4, [] ADC1 init code at atten0 ch1
|
||||
ADC1_INIT_CODE_ATTEN0_CH2, EFUSE_BLK2, 233, 4, [] ADC1 init code at atten0 ch2
|
||||
ADC1_INIT_CODE_ATTEN0_CH3, EFUSE_BLK2, 237, 4, [] ADC1 init code at atten0 ch3
|
||||
ADC1_INIT_CODE_ATTEN0_CH4, EFUSE_BLK2, 241, 4, [] ADC1 init code at atten0 ch4
|
||||
ADC1_INIT_CODE_ATTEN0_CH5, EFUSE_BLK2, 245, 4, [] ADC1 init code at atten0 ch5
|
||||
ADC1_INIT_CODE_ATTEN0_CH6, EFUSE_BLK2, 249, 4, [] ADC1 init code at atten0 ch6
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
|
||||
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
|
||||
KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data
|
||||
KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data
|
||||
KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data
|
||||
KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data
|
||||
KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data
|
||||
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)
|
||||
|
Nie można renderować tego pliku, ponieważ zawiera nieoczekiwany znak w wierszu 8 i kolumnie 53.
|
|
|
@ -0,0 +1,211 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_log.h"
|
||||
#include "assert.h"
|
||||
#include "esp_efuse_utility.h"
|
||||
#include "soc/efuse_periph.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
|
||||
// static const char *TAG = "efuse";
|
||||
|
||||
// TODO: [ESP32C5] IDF-8674
|
||||
|
||||
#ifdef CONFIG_EFUSE_VIRTUAL
|
||||
extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK];
|
||||
#endif // CONFIG_EFUSE_VIRTUAL
|
||||
|
||||
/*Range addresses to read blocks*/
|
||||
const esp_efuse_range_addr_t range_read_addr_blocks[] = {
|
||||
// {EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT
|
||||
// {EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_RD_MAC_SPI_SYS_5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M
|
||||
// {EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA
|
||||
// {EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA
|
||||
// {EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0
|
||||
// {EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1
|
||||
// {EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2
|
||||
// {EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3
|
||||
// {EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4
|
||||
// {EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5
|
||||
// {EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG} // range address of EFUSE_BLK10 KEY6
|
||||
};
|
||||
|
||||
static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 };
|
||||
|
||||
/*Range addresses to write blocks (it is not real regs, it is buffer) */
|
||||
const esp_efuse_range_addr_t range_write_addr_blocks[] = {
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK0][0], (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK1][0], (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK2][0], (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK3][0], (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK4][0], (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK5][0], (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK6][0], (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK7][0], (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK8][0], (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK9][0], (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]},
|
||||
{(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]},
|
||||
};
|
||||
|
||||
#ifndef CONFIG_EFUSE_VIRTUAL
|
||||
// Update Efuse timing configuration
|
||||
static esp_err_t esp_efuse_set_timing(void)
|
||||
{
|
||||
// efuse clock is fixed.
|
||||
// An argument (0) is for compatibility and will be ignored.
|
||||
// TODO: [ESP32C5] IDF-8674
|
||||
abort();
|
||||
// efuse_hal_set_timing(0);
|
||||
return ESP_OK;
|
||||
}
|
||||
#endif // ifndef CONFIG_EFUSE_VIRTUAL
|
||||
|
||||
// Efuse read operation: copies data from physical efuses to efuse read registers.
|
||||
void esp_efuse_utility_clear_program_registers(void)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8674
|
||||
abort();
|
||||
// efuse_hal_read();
|
||||
// efuse_hal_clear_program_registers();
|
||||
}
|
||||
|
||||
esp_err_t esp_efuse_utility_check_errors(void)
|
||||
{
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
// Burn values written to the efuse write registers
|
||||
esp_err_t esp_efuse_utility_burn_chip(void)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8674
|
||||
abort();
|
||||
esp_err_t error = ESP_OK;
|
||||
#ifdef CONFIG_EFUSE_VIRTUAL
|
||||
// ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses");
|
||||
// for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
|
||||
// int subblock = 0;
|
||||
// for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
|
||||
// virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block);
|
||||
// }
|
||||
// }
|
||||
// #ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
|
||||
// esp_efuse_utility_write_efuses_to_flash();
|
||||
// #endif
|
||||
#else // CONFIG_EFUSE_VIRTUAL
|
||||
if (esp_efuse_set_timing() != ESP_OK) {
|
||||
// ESP_LOGE(TAG, "Efuse fields are not burnt");
|
||||
} else {
|
||||
// // Permanently update values written to the efuse write registers
|
||||
// // It is necessary to process blocks in the order from MAX-> EFUSE_BLK0, because EFUSE_BLK0 has protection bits for other blocks.
|
||||
// for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
|
||||
// bool need_burn_block = false;
|
||||
// for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
|
||||
// if (REG_READ(addr_wr_block) != 0) {
|
||||
// need_burn_block = true;
|
||||
// break;
|
||||
// }
|
||||
// }
|
||||
// if (!need_burn_block) {
|
||||
// continue;
|
||||
// }
|
||||
// if (error) {
|
||||
// // It is done for a use case: BLOCK2 (Flash encryption key) could have an error (incorrect written data)
|
||||
// // in this case we can not burn any data into BLOCK0 because it might set read/write protections of BLOCK2.
|
||||
// ESP_LOGE(TAG, "BLOCK%d can not be burned because a previous block got an error, skipped.", num_block);
|
||||
// continue;
|
||||
// }
|
||||
// efuse_hal_clear_program_registers();
|
||||
// if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
|
||||
// uint8_t block_rs[12];
|
||||
// efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs);
|
||||
// hal_memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs));
|
||||
// }
|
||||
// unsigned r_data_len = (range_read_addr_blocks[num_block].end - range_read_addr_blocks[num_block].start) + sizeof(uint32_t);
|
||||
// unsigned data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t);
|
||||
// memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len);
|
||||
|
||||
// uint32_t backup_write_data[8 + 3]; // 8 words are data and 3 words are RS coding data
|
||||
// hal_memcpy(backup_write_data, (void *)EFUSE_PGM_DATA0_REG, sizeof(backup_write_data));
|
||||
// int repeat_burn_op = 1;
|
||||
// bool correct_written_data;
|
||||
// bool coding_error_before = efuse_hal_is_coding_error_in_block(num_block);
|
||||
// if (coding_error_before) {
|
||||
// ESP_LOGW(TAG, "BLOCK%d already has a coding error", num_block);
|
||||
// }
|
||||
// bool coding_error_occurred;
|
||||
|
||||
// do {
|
||||
// ESP_LOGI(TAG, "BURN BLOCK%d", num_block);
|
||||
// efuse_hal_program(num_block); // BURN a block
|
||||
|
||||
// bool coding_error_after;
|
||||
// for (unsigned i = 0; i < 5; i++) {
|
||||
// efuse_hal_read();
|
||||
// coding_error_after = efuse_hal_is_coding_error_in_block(num_block);
|
||||
// if (coding_error_after == true) {
|
||||
// break;
|
||||
// }
|
||||
// }
|
||||
// coding_error_occurred = (coding_error_before != coding_error_after) && coding_error_before == false;
|
||||
// if (coding_error_occurred) {
|
||||
// ESP_LOGW(TAG, "BLOCK%d got a coding error", num_block);
|
||||
// }
|
||||
|
||||
// correct_written_data = esp_efuse_utility_is_correct_written_data(num_block, r_data_len);
|
||||
// if (!correct_written_data || coding_error_occurred) {
|
||||
// ESP_LOGW(TAG, "BLOCK%d: next retry to fix an error [%d/3]...", num_block, repeat_burn_op);
|
||||
// hal_memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)backup_write_data, sizeof(backup_write_data));
|
||||
// }
|
||||
|
||||
// } while ((!correct_written_data || coding_error_occurred) && repeat_burn_op++ < 3);
|
||||
|
||||
// if (coding_error_occurred) {
|
||||
// ESP_LOGW(TAG, "Coding error was not fixed");
|
||||
// if (num_block == 0) {
|
||||
// ESP_LOGE(TAG, "BLOCK0 got a coding error, which might be critical for security");
|
||||
// error = ESP_FAIL;
|
||||
// }
|
||||
// }
|
||||
// if (!correct_written_data) {
|
||||
// ESP_LOGE(TAG, "Written data are incorrect");
|
||||
// error = ESP_FAIL;
|
||||
// }
|
||||
// }
|
||||
}
|
||||
#endif // CONFIG_EFUSE_VIRTUAL
|
||||
// esp_efuse_utility_reset();
|
||||
return error;
|
||||
}
|
||||
|
||||
// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values.
|
||||
// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme.
|
||||
// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this.
|
||||
// They will be filled during the burn operation.
|
||||
esp_err_t esp_efuse_utility_apply_new_coding_scheme()
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8674
|
||||
abort();
|
||||
// // start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE.
|
||||
// for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) {
|
||||
// if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
|
||||
// for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
|
||||
// if (REG_READ(addr_wr_block)) {
|
||||
// int num_reg = 0;
|
||||
// for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) {
|
||||
// if (esp_efuse_utility_read_reg(num_block, num_reg)) {
|
||||
// ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden.");
|
||||
// return ESP_ERR_CODING;
|
||||
// }
|
||||
// }
|
||||
// break;
|
||||
// }
|
||||
// }
|
||||
// }
|
||||
// }
|
||||
return ESP_OK;
|
||||
}
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// TODO: [ESP32C5] IDF-8674
|
||||
|
||||
/**
|
||||
* @brief Type of eFuse blocks ESP32C5
|
||||
*/
|
||||
typedef enum {
|
||||
EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */
|
||||
|
||||
EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */
|
||||
|
||||
EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
|
||||
EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA*/
|
||||
EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA*/
|
||||
|
||||
EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */
|
||||
EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */
|
||||
|
||||
EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */
|
||||
EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */
|
||||
|
||||
EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */
|
||||
EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */
|
||||
|
||||
EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */
|
||||
EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */
|
||||
|
||||
EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */
|
||||
EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */
|
||||
|
||||
EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK_KEY_MAX = 10,
|
||||
|
||||
EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
|
||||
EFUSE_BLK_MAX
|
||||
} esp_efuse_block_t;
|
||||
|
||||
/**
|
||||
* @brief Type of coding scheme
|
||||
*/
|
||||
typedef enum {
|
||||
EFUSE_CODING_SCHEME_NONE = 0, /**< None */
|
||||
EFUSE_CODING_SCHEME_RS = 3, /**< Reed-Solomon coding */
|
||||
} esp_efuse_coding_scheme_t;
|
||||
|
||||
/**
|
||||
* @brief Type of key purpose
|
||||
*/
|
||||
typedef enum {
|
||||
ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */
|
||||
ESP_EFUSE_KEY_PURPOSE_RESERVED = 1, /**< Reserved */
|
||||
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Digital Signature peripheral key (uses HMAC Downstream mode) */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8, /**< HMAC Upstream mode */
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_MAX, /**< MAX PURPOSE */
|
||||
} esp_efuse_purpose_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <esp_types.h>
|
||||
#include <esp_err.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// TODO: [ESP32C5] IDF-8674, IDF-8702
|
||||
|
||||
//This is the ADC calibration value version burnt in efuse
|
||||
#define ESP_EFUSE_ADC_CALIB_VER1 1
|
||||
#define ESP_EFUSE_ADC_CALIB_VER2 2
|
||||
#define ESP_EFUSE_ADC_CALIB_VER_MIN ESP_EFUSE_ADC_CALIB_VER1
|
||||
#define ESP_EFUSE_ADC_CALIB_VER_MAX ESP_EFUSE_ADC_CALIB_VER2
|
||||
#define VER2IDX(ver) ((ver) - 1) // Version number to index number of the array
|
||||
/**
|
||||
* @brief Get the RTC calibration efuse version
|
||||
*
|
||||
* @return Version of the stored efuse
|
||||
*/
|
||||
int esp_efuse_rtc_calib_get_ver(void);
|
||||
|
||||
/**
|
||||
* @brief Get the init code in the efuse, for the corresponding attenuation.
|
||||
*
|
||||
* @param version Version of the stored efuse
|
||||
* @param adc_unit ADC unit. Not used, for compatibility. On esp32c5, for calibration v1, both ADC units use the same init code (calibrated by ADC1)
|
||||
* @param atten Attenuation of the init code
|
||||
* @return The init code stored in efuse
|
||||
*/
|
||||
uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten);
|
||||
|
||||
/**
|
||||
* @brief Get the channel specific calibration compensation
|
||||
*
|
||||
* @param version Version of the stored efuse
|
||||
* @param adc_unit ADC unit. Not used, for compatibility. On esp32c5, for calibration v1, both ADC units use the same init code (calibrated by ADC1)
|
||||
* @param adc_channel ADC channel number
|
||||
* @param atten Attenuation of the init code
|
||||
* @return The channel calibration compensation value
|
||||
*/
|
||||
int esp_efuse_rtc_calib_get_chan_compens(int version, uint32_t adc_unit, uint32_t adc_channel, int atten);
|
||||
|
||||
/**
|
||||
* @brief Get the calibration digits stored in the efuse, and the corresponding voltage.
|
||||
*
|
||||
* @param version Version of the stored efuse
|
||||
* @param adc_unit ADC unit (not used on ESP32C5, for compatibility)
|
||||
* @param atten Attenuation to use
|
||||
* @param out_digi Output buffer of the digits
|
||||
* @param out_vol_mv Output of the voltage, in mV
|
||||
* @return
|
||||
* - ESP_ERR_INVALID_ARG: If efuse version or attenuation is invalid
|
||||
* - ESP_OK: if success
|
||||
*/
|
||||
esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, uint32_t adc_unit, int atten, uint32_t* out_digi, uint32_t* out_vol_mv);
|
||||
|
||||
/**
|
||||
* @brief Get the temperature sensor calibration number delta_T stored in the efuse.
|
||||
*
|
||||
* @param tsens_cal Pointer of the specification of temperature sensor calibration number in efuse.
|
||||
*
|
||||
* @return ESP_OK if get the calibration value successfully.
|
||||
* ESP_ERR_INVALID_ARG if can't get the calibration value.
|
||||
*/
|
||||
esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,240 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
// TODO: [ESP32C5] IDF-8674
|
||||
|
||||
// md5_digest_table fd5a35cea89bfad954e834bc92bed385
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
// To show efuse_table run the command 'show_efuse_table'.
|
||||
|
||||
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SWAP_UART_SDIO_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
|
||||
#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
|
||||
#define ESP_EFUSE_WR_DIS_DPA_SEC_LEVEL ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
|
||||
#define ESP_EFUSE_WR_DIS_DIS_USB_PRINT ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_AS_GPIO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SWAP_UART_SDIO_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
|
||||
#define ESP_EFUSE_DIS_CAN ESP_EFUSE_DIS_TWAI
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
|
||||
#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
|
||||
#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
|
||||
#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
|
||||
#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
|
||||
#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[];
|
||||
#define ESP_EFUSE_DPA_SEC_LEVEL ESP_EFUSE_SEC_DPA_LEVEL
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
|
||||
#define ESP_EFUSE_DIS_USB_PRINT ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
|
||||
#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH6[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||
#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||
#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
|
||||
#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
|
||||
#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
|
||||
#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
|
||||
#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
|
||||
#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
|
||||
#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
|
||||
#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define COUNT_EFUSE_REG_PER_BLOCK 8 /* The number of registers per block. */
|
||||
|
||||
#define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK0
|
||||
|
||||
#define ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(scheme, max_num_bit)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file adc_cali_schemes.h
|
||||
*
|
||||
* @brief Supported calibration schemes
|
||||
*/
|
||||
|
||||
// TODO: [ESP32C5] IDF-8702
|
||||
// #define ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED 1
|
||||
|
|
@ -162,6 +162,15 @@ if(NOT BOOTLOADER_BUILD)
|
|||
"port/esp_clk_tree_common.c" # TODO: [ESP32C5] IDF-8638, IDF-8640
|
||||
)
|
||||
endif()
|
||||
if(CONFIG_IDF_TARGET_ESP32C5)
|
||||
list(REMOVE_ITEM srcs
|
||||
"sleep_cpu.c" # TODO: [ESP32C5] IDF-8638, IDF-8640
|
||||
"sleep_modes.c" # TODO: [ESP32C5] IDF-8638, IDF-8640
|
||||
"sleep_wake_stub.c" # TODO: [ESP32C5] IDF-8638, IDF-8640
|
||||
"sleep_gpio.c" # TODO: [ESP32C5] IDF-8638, IDF-8640
|
||||
"port/esp_clk_tree_common.c" # TODO: [ESP32C5] IDF-8638, IDF-8640
|
||||
)
|
||||
endif()
|
||||
else()
|
||||
# Requires "_esp_error_check_failed()" function
|
||||
list(APPEND priv_requires "esp_system")
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ typedef enum {
|
|||
CHIP_ESP32C2 = 12, //!< ESP32-C2
|
||||
CHIP_ESP32C6 = 13, //!< ESP32-C6
|
||||
CHIP_ESP32H2 = 16, //!< ESP32-H2
|
||||
CHIP_ESP32C5 = 17, //!< ESP32-C5 beta3
|
||||
CHIP_ESP32C5 = 17, //!< ESP32-C5 beta3 TODO: [ESP32-C5] update when MP supported
|
||||
CHIP_ESP32P4 = 18, //!< ESP32-P4
|
||||
CHIP_POSIX_LINUX = 999, //!< The code is running on POSIX/Linux simulator
|
||||
} esp_chip_model_t;
|
||||
|
|
|
|||
|
|
@ -75,6 +75,7 @@ static void IRAM_ATTR modem_clock_wifi_bb_configure(modem_clock_context_t *ctx,
|
|||
#if SOC_BT_SUPPORTED
|
||||
static void IRAM_ATTR modem_clock_ble_mac_configure(modem_clock_context_t *ctx, bool enable)
|
||||
{
|
||||
modem_syscon_ll_enable_bt_mac_clock(ctx->hal->syscon_dev, enable);
|
||||
modem_syscon_ll_enable_modem_sec_clock(ctx->hal->syscon_dev, enable);
|
||||
modem_syscon_ll_enable_ble_timer_clock(ctx->hal->syscon_dev, enable);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
#include "hal/efuse_ll.h"
|
||||
#include "regi2c_ctrl.h"
|
||||
#include "esp_hw_log.h"
|
||||
|
||||
|
||||
// TODO: [ESP32C5] IDF-8702
|
||||
// static const char *TAG = "ocode_init";
|
||||
|
||||
static void set_ocode_by_efuse(int ocode_scheme_ver)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8702
|
||||
}
|
||||
|
||||
static void calibrate_ocode(void)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8702
|
||||
}
|
||||
|
||||
void esp_ocode_calib_init(void)
|
||||
{
|
||||
if (efuse_hal_blk_version() >= 1) {
|
||||
set_ocode_by_efuse(1);
|
||||
} else {
|
||||
calibrate_ocode();
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Initialize OCode
|
||||
*
|
||||
*/
|
||||
void esp_ocode_calib_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -21,7 +21,6 @@
|
|||
#include "esp_rom_uart.h"
|
||||
#include "esp_private/esp_pmu.h"
|
||||
#include "hal/clk_tree_ll.h"
|
||||
// #include "hal/pmu_ll.h"
|
||||
#include "hal/modem_syscon_ll.h"
|
||||
#include "hal/modem_lpcon_ll.h"
|
||||
#include "soc/pmu_reg.h"
|
||||
|
|
|
|||
|
|
@ -4,6 +4,10 @@ if(${target} STREQUAL "linux")
|
|||
return() # This component is not supported by the POSIX/Linux simulator
|
||||
endif()
|
||||
|
||||
if(${target} STREQUAL "esp32c5")
|
||||
return() # not support yet
|
||||
endif()
|
||||
|
||||
set(include_dirs include)
|
||||
set(priv_include_dirs proto-c src ../protocomm/proto-c)
|
||||
set(srcs "src/esp_local_ctrl.c"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "../ext_mem_layout.h"
|
||||
#include "hal/mmu_types.h"
|
||||
|
||||
/**
|
||||
* The start addresses in this list should always be sorted from low to high, as MMU driver will need to
|
||||
* coalesce adjacent regions
|
||||
*/
|
||||
// TODO: [ESP32C5] IDF-8658
|
||||
const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
|
||||
[0] = {
|
||||
.start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
|
||||
.end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
|
||||
.size = SOC_BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
|
||||
.bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
|
||||
.targets = MMU_TARGET_FLASH0,
|
||||
.caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,
|
||||
},
|
||||
};
|
||||
|
|
@ -4,8 +4,8 @@ if(${idf_target} STREQUAL "linux")
|
|||
return() # This component is not supported by the POSIX/Linux simulator
|
||||
endif()
|
||||
|
||||
if(IDF_TARGET STREQUAL "esp32p4")
|
||||
# TODO: IDF-7460
|
||||
if(IDF_TARGET STREQUAL "esp32p4" OR IDF_TARGET STREQUAL "esp32c5")
|
||||
# TODO: IDF-7460, IDF-8851
|
||||
return()
|
||||
endif()
|
||||
|
||||
|
|
|
|||
|
|
@ -90,6 +90,8 @@
|
|||
#define REF_CLK_DIV_MIN 2
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#define REF_CLK_DIV_MIN 2
|
||||
#elif CONFIG_IDF_TARGET_ESP32C5
|
||||
#define REF_CLK_DIV_MIN 2
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#define REF_CLK_DIV_MIN 2
|
||||
#elif CONFIG_IDF_TARGET_ESP32P4
|
||||
|
|
|
|||
|
|
@ -27,6 +27,10 @@
|
|||
#include "esp32h2/rom/rtc.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32P4
|
||||
#include "esp32p4/rom/rtc.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C5
|
||||
#include "esp32c5/rom/rtc.h"
|
||||
#include "hal/clk_tree_ll.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
#endif
|
||||
#include "esp_log.h"
|
||||
#include "esp_rom_sys.h"
|
||||
|
|
@ -55,6 +59,12 @@ void bootloader_clock_configure(void)
|
|||
REG_WRITE(RTC_APB_FREQ_REG, (apb_freq_hz >> 12) | ((apb_freq_hz >> 12) << 16));
|
||||
#endif
|
||||
REG_WRITE(RTC_XTAL_FREQ_REG, (xtal_freq_mhz) | ((xtal_freq_mhz) << 16));
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32C5
|
||||
// The default slow clock source RC_SLOW is unusable on c5, switch to SOC_RTC_SLOW_CLK_SRC_RC32K instead
|
||||
clk_ll_rtc_slow_set_src(SOC_RTC_SLOW_CLK_SRC_RC32K);
|
||||
esp_rom_delay_us(SOC_DELAY_RTC_SLOW_CLK_SWITCH);
|
||||
#endif
|
||||
}
|
||||
|
||||
void esp_clk_init(void)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,139 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* ESP32-C5 Linker Script Memory Layout
|
||||
* This file describes the memory layout (memory blocks) by virtual memory addresses.
|
||||
* This linker script is passed through the C preprocessor to include configuration options.
|
||||
* Please use preprocessor features sparingly!
|
||||
* Restrict to simple macros with numeric values, and/or #if/#endif blocks.
|
||||
*/
|
||||
|
||||
#include "sdkconfig.h"
|
||||
#include "ld.common"
|
||||
|
||||
/**
|
||||
* physical memory is mapped twice to the vritual address (IRAM and DRAM).
|
||||
* `I_D_SRAM_OFFSET` is the offset between the two locations of the same physical memory
|
||||
*/
|
||||
#define SRAM_IRAM_START 0x40800000
|
||||
#define SRAM_DRAM_START 0x40800000
|
||||
|
||||
#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START)
|
||||
#define SRAM_DRAM_END 0x4086E610 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */
|
||||
|
||||
#define SRAM_IRAM_ORG (SRAM_IRAM_START)
|
||||
#define SRAM_DRAM_ORG (SRAM_DRAM_START)
|
||||
|
||||
#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG
|
||||
|
||||
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
|
||||
/*
|
||||
* IDRAM0_2_SEG_SIZE_DEFAULT is used when page size is 64KB
|
||||
*/
|
||||
#define IDRAM0_2_SEG_SIZE (CONFIG_MMU_PAGE_SIZE << 8)
|
||||
#endif
|
||||
|
||||
#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/**
|
||||
* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
|
||||
* of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
|
||||
* are connected to the data port of the CPU and eg allow byte-wise access.
|
||||
*/
|
||||
|
||||
/* IRAM for PRO CPU. */
|
||||
iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE
|
||||
|
||||
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
|
||||
/* Flash mapped instruction data */
|
||||
irom_seg (RX) : org = 0x41000020, len = IDRAM0_2_SEG_SIZE - 0x20
|
||||
|
||||
/**
|
||||
* (0x20 offset above is a convenience for the app binary image generation.
|
||||
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
|
||||
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
|
||||
* header. Setting this offset makes it simple to meet the flash cache MMU's
|
||||
* constraint that (paddr % 64KB == vaddr % 64KB).)
|
||||
*/
|
||||
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
|
||||
|
||||
/**
|
||||
* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
|
||||
* Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
|
||||
*/
|
||||
dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN
|
||||
|
||||
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
|
||||
/* Flash mapped constant data */
|
||||
drom_seg (R) : org = 0x41000020, len = IDRAM0_2_SEG_SIZE - 0x20
|
||||
|
||||
/* (See irom_seg for meaning of 0x20 offset in the above.) */
|
||||
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
|
||||
|
||||
/**
|
||||
* lp ram memory (RWX). Persists over deep sleep. // TODO: IDF-5667
|
||||
*/
|
||||
#if CONFIG_ULP_COPROC_ENABLED
|
||||
lp_ram_seg(RW) : org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
|
||||
len = 0x4000 - CONFIG_ULP_COPROC_RESERVE_MEM - RESERVE_RTC_MEM
|
||||
#else
|
||||
lp_ram_seg(RW) : org = 0x50000000, len = 0x4000 - RESERVE_RTC_MEM
|
||||
#endif // CONFIG_ULP_COPROC_ENABLED
|
||||
|
||||
/* We reduced the size of lp_ram_seg by RESERVE_RTC_MEM value.
|
||||
It reserves the amount of LP memory that we use for this memory segment.
|
||||
This segment is intended for keeping:
|
||||
- (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
|
||||
- (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
|
||||
The aim of this is to keep data that will not be moved around and have a fixed address.
|
||||
*/
|
||||
lp_reserved_seg(RW) : org = 0x50000000 + 0x4000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM
|
||||
}
|
||||
|
||||
/* Heap ends at top of dram0_0_seg */
|
||||
_heap_end = 0x40000000;
|
||||
|
||||
_data_seg_org = ORIGIN(rtc_data_seg);
|
||||
|
||||
/**
|
||||
* The lines below define location alias for .rtc.data section
|
||||
* C5 has no distinguished LP(RTC) fast and slow memory sections, instead, there is a unified LP_RAM section
|
||||
* Thus, the following region segments are not configurable like on other targets
|
||||
*/
|
||||
REGION_ALIAS("rtc_iram_seg", lp_ram_seg );
|
||||
REGION_ALIAS("rtc_data_seg", rtc_iram_seg );
|
||||
REGION_ALIAS("rtc_slow_seg", rtc_iram_seg );
|
||||
REGION_ALIAS("rtc_data_location", rtc_iram_seg );
|
||||
REGION_ALIAS("rtc_reserved_seg", lp_reserved_seg );
|
||||
|
||||
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
|
||||
REGION_ALIAS("default_code_seg", irom_seg);
|
||||
#else
|
||||
REGION_ALIAS("default_code_seg", iram0_0_seg);
|
||||
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
|
||||
|
||||
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
|
||||
REGION_ALIAS("default_rodata_seg", drom_seg);
|
||||
#else
|
||||
REGION_ALIAS("default_rodata_seg", dram0_0_seg);
|
||||
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
|
||||
|
||||
/**
|
||||
* If rodata default segment is placed in `drom_seg`, then flash's first rodata section must
|
||||
* also be first in the segment.
|
||||
*/
|
||||
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
|
||||
ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg),
|
||||
".flash_rodata_dummy section must be placed at the beginning of the rodata segment.")
|
||||
#endif
|
||||
|
||||
#if CONFIG_ESP_SYSTEM_USE_EH_FRAME
|
||||
ASSERT ((__eh_frame_end > __eh_frame), "Error: eh_frame size is null!");
|
||||
ASSERT ((__eh_frame_hdr_end > __eh_frame_hdr), "Error: eh_frame_hdr size is null!");
|
||||
#endif
|
||||
|
|
@ -0,0 +1,442 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* Default entry point */
|
||||
ENTRY(call_start_cpu0);
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/**
|
||||
* RTC fast memory holds RTC wake stub code,
|
||||
* including from any source file named rtc_wake_stub*.c
|
||||
*/
|
||||
.rtc.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_rtc_fast_start = ABSOLUTE(.);
|
||||
_rtc_text_start = ABSOLUTE(.);
|
||||
*(.rtc.entry.text)
|
||||
|
||||
mapping[rtc_text]
|
||||
|
||||
*rtc_wake_stub*.*(.literal .text .literal.* .text.*)
|
||||
*(.rtc_text_end_test)
|
||||
|
||||
/* 16B padding for possible CPU prefetch and 4B alignment for PMS split lines */
|
||||
. += _esp_memprot_prefetch_pad_size;
|
||||
. = ALIGN(4);
|
||||
|
||||
_rtc_text_end = ABSOLUTE(.);
|
||||
} > lp_ram_seg
|
||||
|
||||
/**
|
||||
* This section located in RTC FAST Memory area.
|
||||
* It holds data marked with RTC_FAST_ATTR attribute.
|
||||
* See the file "esp_attr.h" for more information.
|
||||
*/
|
||||
.rtc.force_fast :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_rtc_force_fast_start = ABSOLUTE(.);
|
||||
|
||||
mapping[rtc_force_fast]
|
||||
|
||||
*(.rtc.force_fast .rtc.force_fast.*)
|
||||
. = ALIGN(4) ;
|
||||
_rtc_force_fast_end = ABSOLUTE(.);
|
||||
} > lp_ram_seg
|
||||
|
||||
/**
|
||||
* RTC data section holds RTC wake stub
|
||||
* data/rodata, including from any source file
|
||||
* named rtc_wake_stub*.c and the data marked with
|
||||
* RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
|
||||
*/
|
||||
.rtc.data :
|
||||
{
|
||||
_rtc_data_start = ABSOLUTE(.);
|
||||
|
||||
mapping[rtc_data]
|
||||
|
||||
*rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .srodata.*)
|
||||
_rtc_data_end = ABSOLUTE(.);
|
||||
} > lp_ram_seg
|
||||
|
||||
/* RTC bss, from any source file named rtc_wake_stub*.c */
|
||||
.rtc.bss (NOLOAD) :
|
||||
{
|
||||
_rtc_bss_start = ABSOLUTE(.);
|
||||
*rtc_wake_stub*.*(.bss .bss.* .sbss .sbss.*)
|
||||
*rtc_wake_stub*.*(COMMON)
|
||||
|
||||
mapping[rtc_bss]
|
||||
|
||||
_rtc_bss_end = ABSOLUTE(.);
|
||||
} > lp_ram_seg
|
||||
|
||||
/**
|
||||
* This section holds data that should not be initialized at power up
|
||||
* and will be retained during deep sleep.
|
||||
* User data marked with RTC_NOINIT_ATTR will be placed
|
||||
* into this section. See the file "esp_attr.h" for more information.
|
||||
*/
|
||||
.rtc_noinit (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_rtc_noinit_start = ABSOLUTE(.);
|
||||
*(.rtc_noinit .rtc_noinit.*)
|
||||
. = ALIGN(4) ;
|
||||
_rtc_noinit_end = ABSOLUTE(.);
|
||||
} > lp_ram_seg
|
||||
|
||||
/**
|
||||
* This section located in RTC SLOW Memory area.
|
||||
* It holds data marked with RTC_SLOW_ATTR attribute.
|
||||
* See the file "esp_attr.h" for more information.
|
||||
*/
|
||||
.rtc.force_slow :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_rtc_force_slow_start = ABSOLUTE(.);
|
||||
*(.rtc.force_slow .rtc.force_slow.*)
|
||||
. = ALIGN(4) ;
|
||||
_rtc_force_slow_end = ABSOLUTE(.);
|
||||
} > lp_ram_seg
|
||||
|
||||
/**
|
||||
* This section holds RTC data that should have fixed addresses.
|
||||
* The data are not initialized at power-up and are retained during deep sleep.
|
||||
*/
|
||||
.rtc_reserved (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_rtc_reserved_start = ABSOLUTE(.);
|
||||
/* New data can only be added here to ensure existing data are not moved.
|
||||
Because data have adhered to the end of the segment and code is relied on it.
|
||||
>> put new data here << */
|
||||
|
||||
*(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*)
|
||||
KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*))
|
||||
_rtc_reserved_end = ABSOLUTE(.);
|
||||
} > rtc_reserved_seg
|
||||
|
||||
_rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start;
|
||||
ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)),
|
||||
"RTC reserved segment data does not fit.")
|
||||
|
||||
/* Get size of rtc slow data based on rtc_data_location alias */
|
||||
_rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
|
||||
? (_rtc_force_slow_end - _rtc_data_start)
|
||||
: (_rtc_force_slow_end - _rtc_force_slow_start);
|
||||
|
||||
_rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
|
||||
? (_rtc_force_fast_end - _rtc_fast_start)
|
||||
: (_rtc_noinit_end - _rtc_fast_start);
|
||||
|
||||
ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)),
|
||||
"RTC_SLOW segment data does not fit.")
|
||||
|
||||
ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)),
|
||||
"RTC_FAST segment data does not fit.")
|
||||
|
||||
.iram0.text :
|
||||
{
|
||||
_iram_start = ABSOLUTE(.);
|
||||
/* Vectors go to start of IRAM */
|
||||
ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned");
|
||||
KEEP(*(.exception_vectors_table.text));
|
||||
KEEP(*(.exception_vectors.text));
|
||||
. = ALIGN(4);
|
||||
|
||||
_invalid_pc_placeholder = ABSOLUTE(.);
|
||||
|
||||
/* Code marked as running out of IRAM */
|
||||
_iram_text_start = ABSOLUTE(.);
|
||||
|
||||
mapping[iram0_text]
|
||||
|
||||
} > iram0_0_seg
|
||||
|
||||
/* Marks the end of IRAM code segment */
|
||||
.iram0.text_end (NOLOAD) :
|
||||
{
|
||||
/* ESP32-C5 memprot requires 16B padding for possible CPU prefetch and 512B alignment for PMS split lines */
|
||||
. += _esp_memprot_prefetch_pad_size;
|
||||
. = ALIGN(_esp_memprot_align_size);
|
||||
/* iram_end_test section exists for use by memprot unit tests only */
|
||||
*(.iram_end_test)
|
||||
_iram_text_end = ABSOLUTE(.);
|
||||
} > iram0_0_seg
|
||||
|
||||
.iram0.data :
|
||||
{
|
||||
. = ALIGN(16);
|
||||
_iram_data_start = ABSOLUTE(.);
|
||||
|
||||
mapping[iram0_data]
|
||||
|
||||
_iram_data_end = ABSOLUTE(.);
|
||||
} > iram0_0_seg
|
||||
|
||||
.iram0.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(16);
|
||||
_iram_bss_start = ABSOLUTE(.);
|
||||
|
||||
mapping[iram0_bss]
|
||||
|
||||
_iram_bss_end = ABSOLUTE(.);
|
||||
. = ALIGN(16);
|
||||
_iram_end = ABSOLUTE(.);
|
||||
} > iram0_0_seg
|
||||
|
||||
/**
|
||||
* This section is required to skip .iram0.text area because iram0_0_seg and
|
||||
* dram0_0_seg reflect the same address space on different buses.
|
||||
*/
|
||||
.dram0.dummy (NOLOAD):
|
||||
{
|
||||
. = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
|
||||
} > dram0_0_seg
|
||||
|
||||
.dram0.data :
|
||||
{
|
||||
_data_start = ABSOLUTE(.);
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.data1)
|
||||
__global_pointer$ = . + 0x800;
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
*(.jcr)
|
||||
|
||||
mapping[dram0_data]
|
||||
|
||||
_data_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
} > dram0_0_seg
|
||||
|
||||
/**
|
||||
* This section holds data that should not be initialized at power up.
|
||||
* The section located in Internal SRAM memory region. The macro _NOINIT
|
||||
* can be used as attribute to place data into this section.
|
||||
* See the "esp_attr.h" file for more information.
|
||||
*/
|
||||
.noinit (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_noinit_start = ABSOLUTE(.);
|
||||
*(.noinit .noinit.*)
|
||||
. = ALIGN(4) ;
|
||||
_noinit_end = ABSOLUTE(.);
|
||||
} > dram0_0_seg
|
||||
|
||||
/* Shared RAM */
|
||||
.dram0.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.);
|
||||
|
||||
mapping[dram0_bss]
|
||||
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.share.mem)
|
||||
*(.gnu.linkonce.b.*)
|
||||
|
||||
. = ALIGN (8);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
} > dram0_0_seg
|
||||
|
||||
ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.")
|
||||
|
||||
.flash.text :
|
||||
{
|
||||
_stext = .;
|
||||
_instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */
|
||||
_text_start = ABSOLUTE(.);
|
||||
|
||||
mapping[flash_text]
|
||||
|
||||
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.fini.literal)
|
||||
*(.fini)
|
||||
*(.gnu.version)
|
||||
|
||||
/** CPU will try to prefetch up to 16 bytes of
|
||||
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
|
||||
* safe access to up to 16 bytes after the last real instruction, add
|
||||
* dummy bytes to ensure this
|
||||
*/
|
||||
. += _esp_flash_mmap_prefetch_pad_size;
|
||||
|
||||
_text_end = ABSOLUTE(.);
|
||||
_instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */
|
||||
_etext = .;
|
||||
|
||||
/**
|
||||
* Similar to _iram_start, this symbol goes here so it is
|
||||
* resolved by addr2line in preference to the first symbol in
|
||||
* the flash.text segment.
|
||||
*/
|
||||
_flash_cache_start = ABSOLUTE(0);
|
||||
} > default_code_seg
|
||||
|
||||
/**
|
||||
* This dummy section represents the .flash.text section but in default_rodata_seg.
|
||||
* Thus, it must have its alignment and (at least) its size.
|
||||
*/
|
||||
.flash_rodata_dummy (NOLOAD):
|
||||
{
|
||||
_flash_rodata_dummy_start = .;
|
||||
/* Start at the same alignment constraint than .flash.text */
|
||||
. = ALIGN(ALIGNOF(.flash.text));
|
||||
/* Create an empty gap as big as .flash.text section */
|
||||
. = . + SIZEOF(.flash.text);
|
||||
/* Prepare the alignment of the section above. Few bytes (0x20) must be
|
||||
* added for the mapping header. */
|
||||
. = ALIGN(_esp_mmu_block_size) + 0x20;
|
||||
} > default_rodata_seg
|
||||
|
||||
.flash.appdesc : ALIGN(0x10)
|
||||
{
|
||||
_rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */
|
||||
_rodata_start = ABSOLUTE(.);
|
||||
|
||||
*(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */
|
||||
*(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */
|
||||
|
||||
/* Create an empty gap within this section. Thanks to this, the end of this
|
||||
* section will match .flash.rodata's begin address. Thus, both sections
|
||||
* will be merged when creating the final bin image. */
|
||||
. = ALIGN(ALIGNOF(.flash.rodata));
|
||||
} >default_rodata_seg
|
||||
|
||||
.flash.rodata : ALIGN(0x10)
|
||||
{
|
||||
_flash_rodata_start = ABSOLUTE(.);
|
||||
|
||||
mapping[flash_rodata]
|
||||
|
||||
*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
|
||||
*(.xt_except_table)
|
||||
*(.gcc_except_table .gcc_except_table.*)
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
. = (. + 7) & ~ 3;
|
||||
/*
|
||||
* C++ constructor and destructor tables
|
||||
* Don't include anything from crtbegin.o or crtend.o, as IDF doesn't use toolchain crt.
|
||||
*
|
||||
* RISC-V gcc is configured with --enable-initfini-array so it emits an .init_array section instead.
|
||||
* But the init_priority sections will be sorted for iteration in ascending order during startup.
|
||||
* The rest of the init_array sections is sorted for iteration in descending order during startup, however.
|
||||
* Hence a different section is generated for the init_priority functions which is iterated in
|
||||
* ascending order during startup. The corresponding code can be found in startup.c.
|
||||
*/
|
||||
__init_priority_array_start = ABSOLUTE(.);
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))
|
||||
__init_priority_array_end = ABSOLUTE(.);
|
||||
__init_array_start = ABSOLUTE(.);
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))
|
||||
__init_array_end = ABSOLUTE(.);
|
||||
KEEP (*crtbegin.*(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
/* C++ exception handlers table: */
|
||||
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
/* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */
|
||||
soc_reserved_memory_region_start = ABSOLUTE(.);
|
||||
KEEP (*(.reserved_memory_address))
|
||||
soc_reserved_memory_region_end = ABSOLUTE(.);
|
||||
/* System init functions registered via ESP_SYSTEM_INIT_FN */
|
||||
_esp_system_init_fn_array_start = ABSOLUTE(.);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*)))
|
||||
_esp_system_init_fn_array_end = ABSOLUTE(.);
|
||||
_rodata_end = ABSOLUTE(.);
|
||||
/* Literals are also RO data. */
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
. = ALIGN(4);
|
||||
_thread_local_start = ABSOLUTE(.);
|
||||
*(.tdata)
|
||||
*(.tdata.*)
|
||||
*(.tbss)
|
||||
*(.tbss.*)
|
||||
_thread_local_end = ABSOLUTE(.);
|
||||
. = ALIGN(ALIGNOF(.eh_frame));
|
||||
} > default_rodata_seg
|
||||
|
||||
/* Keep this section shall be at least aligned on 4 */
|
||||
.eh_frame : ALIGN(8)
|
||||
{
|
||||
__eh_frame = ABSOLUTE(.);
|
||||
KEEP (*(.eh_frame))
|
||||
__eh_frame_end = ABSOLUTE(.);
|
||||
/* Guarantee that this section and the next one will be merged by making
|
||||
* them adjacent. */
|
||||
. = ALIGN(ALIGNOF(.eh_frame_hdr));
|
||||
} > default_rodata_seg
|
||||
|
||||
/* To avoid any exception in C++ exception frame unwinding code, this section
|
||||
* shall be aligned on 8. */
|
||||
.eh_frame_hdr : ALIGN(8)
|
||||
{
|
||||
__eh_frame_hdr = ABSOLUTE(.);
|
||||
KEEP (*(.eh_frame_hdr))
|
||||
__eh_frame_hdr_end = ABSOLUTE(.);
|
||||
} > default_rodata_seg
|
||||
|
||||
/*
|
||||
This section is a place where we dump all the rodata which aren't used at runtime,
|
||||
so as to avoid binary size increase
|
||||
*/
|
||||
.flash.rodata_noload (NOLOAD) :
|
||||
{
|
||||
/*
|
||||
This is a symbol marking the flash.rodata end, this can be used for mmu driver to maintain virtual address
|
||||
We don't need to include the noload rodata in this section
|
||||
*/
|
||||
_rodata_reserved_end = ABSOLUTE(.);
|
||||
. = ALIGN (4);
|
||||
mapping[rodata_noload]
|
||||
} > default_rodata_seg
|
||||
|
||||
/* Marks the end of data, bss and possibly rodata */
|
||||
.dram0.heap_start (NOLOAD) :
|
||||
{
|
||||
. = ALIGN (16);
|
||||
_heap_start = ABSOLUTE(.);
|
||||
} > dram0_0_seg
|
||||
}
|
||||
|
||||
ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
|
||||
"IRAM0 segment data does not fit.")
|
||||
|
||||
ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
|
||||
"DRAM segment data does not fit.")
|
||||
|
|
@ -70,7 +70,6 @@
|
|||
#include "soc/hp_sys_clkrst_reg.h"
|
||||
#include "soc/interrupt_core0_reg.h"
|
||||
#include "soc/interrupt_core1_reg.h"
|
||||
#include "soc/keymng_reg.h"
|
||||
#endif
|
||||
|
||||
#include "esp_private/rtc_clk.h"
|
||||
|
|
@ -156,16 +155,18 @@ static volatile bool s_resume_cores;
|
|||
|
||||
static void core_intr_matrix_clear(void)
|
||||
{
|
||||
uint32_t core_id = esp_cpu_get_core_id();
|
||||
|
||||
for (int i = 0; i < ETS_MAX_INTR_SOURCE; i++) {
|
||||
#if CONFIG_IDF_TARGET_ESP32P4
|
||||
uint32_t core_id = esp_cpu_get_core_id();
|
||||
if (core_id == 0) {
|
||||
REG_WRITE(INTERRUPT_CORE0_LP_RTC_INT_MAP_REG + 4 * i, ETS_INVALID_INUM);
|
||||
} else {
|
||||
REG_WRITE(INTERRUPT_CORE1_LP_RTC_INT_MAP_REG + 4 * i, ETS_INVALID_INUM);
|
||||
}
|
||||
// #elif CONFIG_IDF_TARGET_ESP32C5
|
||||
// REG_WRITE(INTMTX_CORE0_WIFI_MAC_INT_MAP_REG + 4 * i, 0);
|
||||
#else
|
||||
uint32_t core_id = esp_cpu_get_core_id();
|
||||
esp_rom_route_intr_matrix(core_id, i, ETS_INVALID_INUM);
|
||||
#endif // CONFIG_IDF_TARGET_ESP32P4
|
||||
}
|
||||
|
|
@ -306,11 +307,6 @@ static void start_other_core(void)
|
|||
if(REG_GET_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL)){
|
||||
REG_CLR_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL);
|
||||
}
|
||||
// The following operation makes the Key Manager to use eFuse key for ECDSA and XTS-AES operation by default
|
||||
// This is to keep the default behavior same as the other chips
|
||||
// If the Key Manager configuration is already locked then following operation does not have any effect
|
||||
// TODO-IDF 7925 (Move this under SOC_KEY_MANAGER_SUPPORTED)
|
||||
REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY, 3);
|
||||
#endif
|
||||
ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
|
||||
|
||||
|
|
@ -704,7 +700,7 @@ void IRAM_ATTR call_start_cpu0(void)
|
|||
if (rst_reas[0] == RESET_REASON_CORE_DEEP_SLEEP) {
|
||||
esp_deep_sleep_wakeup_io_reset();
|
||||
}
|
||||
#endif //#if !CONFIG_IDF_TARGET_ESP32P4 & !CONFIG_IDF_TARGET_ESP32C5
|
||||
#endif //#if !CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_IDF_TARGET_ESP32C5
|
||||
|
||||
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
||||
esp_cache_err_int_init();
|
||||
|
|
|
|||
|
|
@ -147,7 +147,7 @@ ESP_SYSTEM_INIT_FN(init_psram_heap, CORE, BIT(0), 103)
|
|||
return ESP_OK;
|
||||
}
|
||||
|
||||
#if CONFIG_ESP_BROWNOUT_DET
|
||||
#if CONFIG_ESP_BROWNOUT_DET && SOC_BOD_SUPPORTED
|
||||
ESP_SYSTEM_INIT_FN(init_brownout, CORE, BIT(0), 104)
|
||||
{
|
||||
// [refactor-todo] leads to call chain rtc_is_register (driver) -> esp_intr_alloc (esp32/esp32s2) ->
|
||||
|
|
|
|||
|
|
@ -1,5 +1,10 @@
|
|||
idf_build_get_property(target IDF_TARGET)
|
||||
|
||||
|
||||
if(${target} STREQUAL "esp32c5")
|
||||
return() # not support yet
|
||||
endif()
|
||||
|
||||
set(srcs "diskio/diskio.c"
|
||||
"diskio/diskio_rawflash.c"
|
||||
"diskio/diskio_wl.c"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "hal/lp_aon_ll.h"
|
||||
|
||||
#define rtc_hal_ext1_get_wakeup_status() lp_aon_ll_ext1_get_wakeup_status()
|
||||
#define rtc_hal_ext1_clear_wakeup_status() lp_aon_ll_ext1_clear_wakeup_status()
|
||||
#define rtc_hal_ext1_set_wakeup_pins(io_mask, mode_mask) lp_aon_ll_ext1_set_wakeup_pins(io_mask, mode_mask)
|
||||
#define rtc_hal_ext1_clear_wakeup_pins() lp_aon_ll_ext1_clear_wakeup_pins()
|
||||
#define rtc_hal_ext1_get_wakeup_pins() lp_aon_ll_ext1_get_wakeup_pins()
|
||||
|
||||
#define lp_aon_hal_inform_wakeup_type(dslp) lp_aon_ll_inform_wakeup_type(dslp)
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for ESP32-C5 LP_AON register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/lp_aon_struct.h"
|
||||
#include "hal/misc.h"
|
||||
#include "esp32c5/rom/rtc.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Get ext1 wakeup source status
|
||||
* @return The lower 8 bits of the returned value are the bitmap of
|
||||
* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
|
||||
*/
|
||||
static inline uint32_t lp_aon_ll_ext1_get_wakeup_status(void)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8638, IDF-8640
|
||||
// return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status);
|
||||
return (uint32_t)0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the ext1 wakeup source status
|
||||
*/
|
||||
static inline void lp_aon_ll_ext1_clear_wakeup_status(void)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8638, IDF-8640
|
||||
// HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status_clr, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the wake-up LP_IO of the ext1 wake-up source
|
||||
* @param io_mask wakeup LP_IO bitmap, bit 0~7 corresponds to LP_IO 0~7
|
||||
* @param level_mask LP_IO wakeup level bitmap, bit 0~7 corresponds to LP_IO 0~7 wakeup level
|
||||
* each bit's corresponding position is set to 0, the wakeup level will be low
|
||||
* on the contrary, each bit's corresponding position is set to 1, the wakeup
|
||||
* level will be high
|
||||
*/
|
||||
static inline void lp_aon_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t level_mask)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8638, IDF-8640
|
||||
// HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, io_mask);
|
||||
// HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, level_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear all ext1 wakup-source setting
|
||||
*/
|
||||
static inline void lp_aon_ll_ext1_clear_wakeup_pins(void)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8638, IDF-8640
|
||||
// HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get ext1 wakeup source setting
|
||||
* @return The lower 8 bits of the returned value are the bitmap of
|
||||
* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
|
||||
*/
|
||||
static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8638, IDF-8640
|
||||
// return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
|
||||
return (uint32_t)0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0].
|
||||
* Set the flag to inform
|
||||
* @param true: deepsleep false: lightsleep
|
||||
*/
|
||||
static inline void lp_aon_ll_inform_wakeup_type(bool dslp)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8638, IDF-8640
|
||||
// if (dslp) {
|
||||
// REG_SET_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */
|
||||
// // } else {
|
||||
// REG_CLR_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */
|
||||
// }
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -66,7 +66,7 @@ typedef union {
|
|||
#define spi_flash_ll_set_dummy(dev, dummy) gpspi_flash_ll_set_dummy((spi_dev_t*)dev, dummy)
|
||||
#define spi_flash_ll_set_hold(dev, hold_n) gpspi_flash_ll_set_hold((spi_dev_t*)dev, hold_n)
|
||||
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) gpspi_flash_ll_set_cs_setup((spi_dev_t*)dev, cs_setup_time)
|
||||
#define spi_flash_ll_set_extra_address(dev, extra_addr) { /* Not supported on gpspi on ESP32-C*/ }
|
||||
#define spi_flash_ll_set_extra_address(dev, extra_addr) { /* Not supported on gpspi on ESP32-C5*/ }
|
||||
#else
|
||||
#define spi_flash_ll_reset(dev) spimem_flash_ll_reset((spi_mem_dev_t*)dev)
|
||||
#define spi_flash_ll_cmd_is_done(dev) spimem_flash_ll_cmd_is_done((spi_mem_dev_t*)dev)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include "esp_attr.h"
|
||||
#include "sdkconfig.h"
|
||||
#include "soc/soc.h"
|
||||
#include "heap_memory_layout.h"
|
||||
#include "esp_heap_caps.h"
|
||||
|
||||
/**
|
||||
* @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
|
||||
* Each type of memory map consists of one or more regions in the address space.
|
||||
* Each type contains an array of prioritized capabilities.
|
||||
* Types with later entries are only taken if earlier ones can't fulfill the memory request.
|
||||
*
|
||||
* - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory.
|
||||
* - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
|
||||
* - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
|
||||
* - Most other malloc caps only fit in one region anyway.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Index of memory in `soc_memory_types[]` */
|
||||
enum {
|
||||
SOC_MEMORY_TYPE_RAM = 0,
|
||||
SOC_MEMORY_TYPE_RTCRAM = 1,
|
||||
SOC_MEMORY_TYPE_NUM,
|
||||
};
|
||||
|
||||
/* COMMON_CAPS is the set of attributes common to all types of memory on this chip */
|
||||
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
|
||||
#define ESP32C5_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT)
|
||||
#else
|
||||
#define ESP32C5_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_EXEC)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Defined the attributes and allocation priority of each memory on the chip,
|
||||
* The heap allocator will traverse all types of memory types in column High Priority Matching and match the specified caps at first,
|
||||
* if no memory caps matched or the allocation is failed, it will go to columns Medium Priorty Matching and Low Priority Matching
|
||||
* in turn to continue matching.
|
||||
*/
|
||||
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
|
||||
/* Mem Type Name High Priority Matching Medium Priorty Matching Low Priority Matching */
|
||||
[SOC_MEMORY_TYPE_RAM] = { "RAM", { ESP32C5_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0, 0 }},
|
||||
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, ESP32C5_MEM_COMMON_CAPS, 0 }},
|
||||
};
|
||||
|
||||
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
|
||||
|
||||
/**
|
||||
* @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
|
||||
*
|
||||
* @note Because of requirements in the coalescing code which merges adjacent regions,
|
||||
* this list should always be sorted from low to high by start address.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* Register the shared buffer area of the last memory block into the heap during heap initialization
|
||||
*/
|
||||
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
|
||||
|
||||
const soc_memory_region_t soc_memory_regions[] = {
|
||||
{ 0x40800000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40800000, false}, //D/IRAM level0, can be used as trace memory
|
||||
{ 0x40820000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40820000, false}, //D/IRAM level1, can be used as trace memory
|
||||
{ 0x40840000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40840000, false}, //D/IRAM level2, can be used as trace memory
|
||||
{ 0x40860000, (APP_USABLE_DRAM_END-0x40860000), SOC_MEMORY_TYPE_RAM, 0x40860000, false}, //D/IRAM level3, can be used as trace memory
|
||||
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
|
||||
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||
{ 0x50000000, 0x4000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM
|
||||
#endif
|
||||
};
|
||||
|
||||
const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
|
||||
|
||||
|
||||
extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end;
|
||||
extern int _rtc_reserved_start, _rtc_reserved_end;
|
||||
|
||||
/**
|
||||
* Reserved memory regions.
|
||||
* These are removed from the soc_memory_regions array when heaps are created.
|
||||
*
|
||||
*/
|
||||
|
||||
// Static data region. DRAM used by data+bss and possibly rodata
|
||||
SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data);
|
||||
|
||||
// Target has a shared D/IRAM virtual address, no need to calculate I_D_OFFSET like previous chips
|
||||
SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code);
|
||||
|
||||
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||
// TODO: IDF-6019 check reserved lp mem region
|
||||
SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data);
|
||||
#endif
|
||||
|
||||
SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_start, (intptr_t)&_rtc_reserved_end, rtc_reserved_data);
|
||||
|
|
@ -19,6 +19,8 @@
|
|||
#include "esp32c2/rom/rom_layout.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "esp32c6/rom/rom_layout.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C5
|
||||
#include "esp32c5/rom/rom_layout.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "esp32h2/rom/rom_layout.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32P4
|
||||
|
|
|
|||
|
|
@ -34,6 +34,8 @@
|
|||
#include "esp32c2/rom/libc_stubs.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "esp32c6/rom/libc_stubs.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C5
|
||||
#include "esp32c5/rom/libc_stubs.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "esp32h2/rom/libc_stubs.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32P4
|
||||
|
|
|
|||
|
|
@ -39,6 +39,9 @@
|
|||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "esp32c6/rom/rtc.h"
|
||||
#include "esp32c6/rtc.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C5
|
||||
#include "esp32c5/rom/rtc.h"
|
||||
#include "esp32c5/rtc.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "esp32h2/rom/rtc.h"
|
||||
#include "esp32h2/rtc.h"
|
||||
|
|
|
|||
|
|
@ -4,6 +4,10 @@ if(${target} STREQUAL "linux")
|
|||
return() # This component is not supported by the POSIX/Linux simulator
|
||||
endif()
|
||||
|
||||
if(${target} STREQUAL "esp32c5")
|
||||
return() # not support yet
|
||||
endif()
|
||||
|
||||
set(include_dirs include/common
|
||||
include/security
|
||||
include/transports
|
||||
|
|
|
|||
|
|
@ -10,7 +10,6 @@
|
|||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
|
|
|
|||
|
|
@ -39,6 +39,10 @@ config SOC_SPI_FLASH_SUPPORTED
|
|||
bool
|
||||
default y
|
||||
|
||||
config SOC_SPI_FLASH_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_INT_HW_NESTED_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
|
@ -143,6 +147,18 @@ config SOC_MMU_PERIPH_NUM
|
|||
int
|
||||
default 1
|
||||
|
||||
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RTCIO_PIN_COUNT
|
||||
bool
|
||||
default n
|
||||
|
||||
config SOC_MMU_PERIPH_NUM
|
||||
int
|
||||
default 1
|
||||
|
||||
config SOC_MMU_LINEAR_ADDRESS_REGION_NUM
|
||||
int
|
||||
default 1
|
||||
|
|
|
|||
|
|
@ -26,6 +26,9 @@
|
|||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "esp32c6/rom/ets_sys.h"
|
||||
#include "esp32c6/rom/cache.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C5
|
||||
#include "esp32c5/rom/ets_sys.h"
|
||||
#include "esp32c5/rom/cache.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "esp32h2/rom/ets_sys.h"
|
||||
#include "esp32h2/rom/cache.h"
|
||||
|
|
@ -43,7 +46,7 @@ typedef struct {
|
|||
} spi_noos_arg_t;
|
||||
|
||||
static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 };
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5
|
||||
typedef struct {
|
||||
uint32_t icache_autoload;
|
||||
} spi_noos_arg_t;
|
||||
|
|
|
|||
|
|
@ -1,5 +1,10 @@
|
|||
idf_build_get_property(target IDF_TARGET)
|
||||
|
||||
|
||||
if(${target} STREQUAL "esp32c5")
|
||||
return() # not support yet
|
||||
endif()
|
||||
|
||||
set(original_srcs "spiffs/src/spiffs_cache.c"
|
||||
"spiffs/src/spiffs_check.c"
|
||||
"spiffs/src/spiffs_gc.c"
|
||||
|
|
|
|||
|
|
@ -4,6 +4,10 @@ if(${target} STREQUAL "linux")
|
|||
return() # This component is not supported by the POSIX/Linux simulator
|
||||
endif()
|
||||
|
||||
if(${target} STREQUAL "esp32c5")
|
||||
return() # not support yet
|
||||
endif()
|
||||
|
||||
list(APPEND sources "vfs.c"
|
||||
"vfs_eventfd.c"
|
||||
"vfs_semihost.c"
|
||||
|
|
|
|||
|
|
@ -4,6 +4,10 @@ if(${target} STREQUAL "linux")
|
|||
return() # This component is not supported by the POSIX/Linux simulator
|
||||
endif()
|
||||
|
||||
if(${target} STREQUAL "esp32c5")
|
||||
return() # not support yet
|
||||
endif()
|
||||
|
||||
set(srcs "src/wifi_config.c"
|
||||
"src/wifi_scan.c"
|
||||
"src/wifi_ctrl.c"
|
||||
|
|
|
|||
|
|
@ -71,6 +71,8 @@
|
|||
#include "esp32c2/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C6
|
||||
#include "esp32c6/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C5
|
||||
#include "esp32c5/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
#include "esp32h2/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32P4
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue