kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'feature/p4_memory_protection' into 'master'
feat: add memory protection support using PMA/PMP for P4 target Closes IDF-7542 See merge request espressif/esp-idf!29947pull/13517/merge
Mahavir Jain
commit
7a283b73f6
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@ -1,4 +1,4 @@
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[codespell]
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skip = build,*.yuv,components/fatfs/src/*,alice.txt,*.rgb
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ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling
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ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling,hart
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write-changes = true
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -9,22 +9,232 @@
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#include "soc/soc.h"
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#include "esp_cpu.h"
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#include "esp_fault.h"
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#include "hal/cache_ll.h"
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#include "riscv/csr.h"
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#ifdef BOOTLOADER_BUILD
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// Without L bit set
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#define CONDITIONAL_NONE 0x0
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#define CONDITIONAL_R PMP_R
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#define CONDITIONAL_RX PMP_R | PMP_X
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#define CONDITIONAL_RW PMP_R | PMP_W
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#define CONDITIONAL_RWX PMP_R | PMP_W | PMP_X
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#else
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// With L bit set
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#define CONDITIONAL_NONE NONE
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#define CONDITIONAL_R R
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#define CONDITIONAL_RX RX
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#define CONDITIONAL_RW RW
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#define CONDITIONAL_RWX RWX
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#endif
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#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) (((addr) + (SOC_MMU_PAGE_SIZE) - 1) & ~((SOC_MMU_PAGE_SIZE) - 1))
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#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ((addr) & ~((SOC_MMU_PAGE_SIZE) - 1))
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static void esp_cpu_configure_invalid_regions(void)
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{
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const unsigned PMA_NONE = PMA_L | PMA_EN;
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__attribute__((unused)) const unsigned PMA_RW = PMA_L | PMA_EN | PMA_R | PMA_W;
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__attribute__((unused)) const unsigned PMA_RX = PMA_L | PMA_EN | PMA_R | PMA_X;
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__attribute__((unused)) const unsigned PMA_RWX = PMA_L | PMA_EN | PMA_R | PMA_W | PMA_X;
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// 0. Special case - This whitelists the External flash/RAM, HP ROM and HP L2MEM regions and make them cacheable.
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// At the startup, this is done using PMA entry 15 by the ROM code.
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// We are reconfiguring and making it the highest priority entry here.
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PMA_ENTRY_SET_NAPOT(0, SOC_IROM_LOW, SOC_PERIPHERAL_LOW - SOC_IROM_LOW, PMA_NAPOT | PMA_RWX);
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// 1. Gap at bottom of address space
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PMA_ENTRY_SET_NAPOT(1, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE);
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// 2. Gap between CPU subsystem region & HP TCM
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PMA_ENTRY_SET_TOR(2, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE);
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PMA_ENTRY_SET_TOR(3, SOC_TCM_LOW, PMA_TOR | PMA_NONE);
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// 3. Gap between HP TCM and CPU Peripherals
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PMA_ENTRY_SET_TOR(4, SOC_TCM_HIGH, PMA_NONE);
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PMA_ENTRY_SET_TOR(5, CPU_PERIPH_LOW, PMA_TOR | PMA_NONE);
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// 4. Gap between CPU Peripherals and I_Cache
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PMA_ENTRY_SET_TOR(6, CPU_PERIPH_HIGH, PMA_NONE);
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PMA_ENTRY_SET_TOR(7, SOC_IROM_LOW, PMA_TOR | PMA_NONE);
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// 5. Gap between I_Cache and external memory range
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PMA_ENTRY_SET_NAPOT(8, SOC_DROM_HIGH, SOC_EXTRAM_LOW - SOC_DROM_HIGH, PMA_NAPOT | PMA_NONE);
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// 6. Gap between external memory and ROM
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PMA_ENTRY_SET_TOR(9, SOC_EXTRAM_HIGH, PMA_NONE);
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PMA_ENTRY_SET_TOR(10, SOC_IROM_MASK_LOW, PMA_TOR | PMA_NONE);
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// 7. Gap between ROM and internal memory
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PMA_ENTRY_SET_TOR(11, SOC_IROM_MASK_HIGH, PMA_NONE);
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PMA_ENTRY_SET_TOR(12, SOC_IRAM_LOW, PMA_TOR | PMA_NONE);
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// 8. Gap between internal memory and HP peripherals
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PMA_ENTRY_SET_NAPOT(13, SOC_DRAM_HIGH, SOC_PERIPHERAL_LOW - SOC_DRAM_HIGH, PMA_NAPOT | PMA_NONE);
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// 9. Gap between Uncacheable L2 Mem and end of address space
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PMA_ENTRY_SET_TOR(14, CACHE_LL_L2MEM_NON_CACHE_ADDR(SOC_DRAM_HIGH), PMA_NONE);
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PMA_ENTRY_SET_TOR(15, UINT32_MAX, PMA_TOR | PMA_NONE);
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}
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void esp_cpu_configure_region_protection(void)
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{
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//IDF-7542
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/* Notes on implementation:
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*
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* 1) Note: ESP32-P4 CPU support overlapping PMP regions, configuration is based on static priority
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* feature (lowest numbered entry has highest priority).
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*
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* 2) ESP32-P4 supports 16 PMA regions so we use this feature to block the invalid address ranges.
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* However the entries are not sufficient to block all reserved memory ranges and the excluded sections are:
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* a. Region between LP ROM and LP SRAM
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* b. Region between LP peripherals and External flash (direct access)
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* c. Region between External flash (direct access) and External RAM (direct access)
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* d. Region between External RAM (direct access) and HP ROM (direct access)
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* e. Region between HP ROM (direct access) and HP L2MEM (direct access)
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*
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* 3) We use combination of NAPOT (Naturally Aligned Power Of Two) and TOR (top of range)
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* entries to map all the valid address space, bottom to top. This leaves us with some extra PMP entries
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* which can be used to provide more granular access
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*
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* 4) Entries are grouped in order with some static asserts to try and verify everything is
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* correct.
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*
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* 5) No explicit permission specified in PMP (default all permissions) for following regions due to
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* limited entries:
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* a. External RAM
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* b. LP ROM, LP Peripherals, LP SRAM
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* c. External flash, External RAM, HP ROM, HP L2MEM (direct access)
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*/
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/* There are 4 configuration scenarios for SRAM
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*
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* 1. Bootloader build:
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* - We cannot set the lock bit as we need to reconfigure it again for the application.
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* We configure PMP to cover entire valid IRAM and DRAM range.
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*
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* 2. Application build with CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT enabled
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* - We split the SRAM into IRAM and DRAM such that IRAM region cannot be written to
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* and DRAM region cannot be executed. We use _iram_end and _data_start markers to set the boundaries.
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* We also lock these entries so the R/W/X permissions are enforced even for machine mode
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*
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* 3. Application build with CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT disabled
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* - The IRAM-DRAM split is not enabled so we just need to ensure that access to only valid address ranges are successful
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* so for that we set PMP to cover entire valid IRAM and DRAM region.
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* We also lock these entries so the R/W/X permissions are enforced even for machine mode
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*
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* 4. CPU is in OCD debug mode
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* - The IRAM-DRAM split is not enabled so that OpenOCD can write and execute from IRAM.
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* We set PMP to cover entire valid IRAM and DRAM region.
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* We also lock these entries so the R/W/X permissions are enforced even for machine mode
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*/
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const unsigned NONE = PMP_L;
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__attribute__((unused)) const unsigned R = PMP_L | PMP_R;
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const unsigned RW = PMP_L | PMP_R | PMP_W;
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const unsigned RX = PMP_L | PMP_R | PMP_X;
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const unsigned RWX = PMP_L | PMP_R | PMP_W | PMP_X;
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//
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// Configure all the invalid address regions using PMA
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//
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esp_cpu_configure_invalid_regions();
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//
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// Configure all the valid address regions using PMP
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//
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// 1. CPU Subsystem region - contains debug mode code and interrupt config registers
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const uint32_t pmpaddr0 = PMPADDR_NAPOT(SOC_CPU_SUBSYSTEM_LOW, SOC_CPU_SUBSYSTEM_HIGH);
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PMP_ENTRY_SET(0, pmpaddr0, PMP_NAPOT | RW);
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_Static_assert(SOC_CPU_SUBSYSTEM_LOW < SOC_CPU_SUBSYSTEM_HIGH, "Invalid CPU subsystem region");
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// 2. CPU Peripherals
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const uint32_t pmpaddr1 = PMPADDR_NAPOT(CPU_PERIPH_LOW, CPU_PERIPH_HIGH);
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PMP_ENTRY_SET(1, pmpaddr1, PMP_NAPOT | RW);
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_Static_assert(CPU_PERIPH_LOW < CPU_PERIPH_HIGH, "Invalid CPU peripheral region");
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// 3. I/D-ROM
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const uint32_t pmpaddr2 = PMPADDR_NAPOT(SOC_IROM_MASK_LOW, SOC_IROM_MASK_HIGH);
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PMP_ENTRY_SET(2, pmpaddr2, PMP_NAPOT | RX);
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_Static_assert(SOC_IROM_MASK_LOW < SOC_IROM_MASK_HIGH, "Invalid I/D-ROM region");
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if (esp_cpu_dbgr_is_attached()) {
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// Anti-FI check that cpu is really in ocd mode
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ESP_FAULT_ASSERT(esp_cpu_dbgr_is_attached());
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// 4. IRAM and DRAM
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PMP_ENTRY_SET(3, SOC_IRAM_LOW, NONE);
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PMP_ENTRY_SET(4, SOC_IRAM_HIGH, PMP_TOR | RWX);
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_Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid RAM region");
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} else {
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#if CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT && !BOOTLOADER_BUILD
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extern int _iram_end;
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// 4. IRAM and DRAM
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/* Reset the corresponding PMP config because PMP_ENTRY_SET only sets the given bits
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* Bootloader might have given extra permissions and those won't be cleared
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*/
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PMP_ENTRY_CFG_RESET(3);
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PMP_ENTRY_CFG_RESET(4);
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PMP_ENTRY_CFG_RESET(5);
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PMP_ENTRY_SET(3, SOC_IRAM_LOW, NONE);
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PMP_ENTRY_SET(4, (int)&_iram_end, PMP_TOR | RX);
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PMP_ENTRY_SET(5, SOC_DRAM_HIGH, PMP_TOR | RW);
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#else
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// 4. IRAM and DRAM
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PMP_ENTRY_SET(3, SOC_IRAM_LOW, CONDITIONAL_NONE);
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PMP_ENTRY_SET(4, SOC_IRAM_HIGH, PMP_TOR | CONDITIONAL_RWX);
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_Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid RAM region");
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#endif
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}
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#if CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT && !BOOTLOADER_BUILD
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extern int _instruction_reserved_end;
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extern int _rodata_reserved_end;
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const uint32_t irom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_instruction_reserved_end));
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const uint32_t drom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_rodata_reserved_end));
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// 5. I_Cache / D_Cache (flash)
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PMP_ENTRY_CFG_RESET(6);
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PMP_ENTRY_CFG_RESET(7);
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PMP_ENTRY_CFG_RESET(8);
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PMP_ENTRY_SET(6, SOC_IROM_LOW, NONE);
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PMP_ENTRY_SET(7, irom_resv_end, PMP_TOR | RX);
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PMP_ENTRY_SET(8, drom_resv_end, PMP_TOR | R);
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#else
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// 5. I_Cache / D_Cache (flash)
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const uint32_t pmpaddr6 = PMPADDR_NAPOT(SOC_IROM_LOW, SOC_IROM_HIGH);
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PMP_ENTRY_SET(6, pmpaddr6, PMP_NAPOT | CONDITIONAL_RX);
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_Static_assert(SOC_IROM_LOW < SOC_IROM_HIGH, "Invalid I/D_Cache region");
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#endif
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// 6. LP memory
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#if CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT && !BOOTLOADER_BUILD
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extern int _rtc_text_end;
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/* Reset the corresponding PMP config because PMP_ENTRY_SET only sets the given bits
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* Bootloader might have given extra permissions and those won't be cleared
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*/
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PMP_ENTRY_CFG_RESET(9);
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PMP_ENTRY_CFG_RESET(10);
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PMP_ENTRY_CFG_RESET(11);
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PMP_ENTRY_CFG_RESET(12);
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PMP_ENTRY_SET(9, SOC_RTC_IRAM_LOW, NONE);
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#if CONFIG_ULP_COPROC_RESERVE_MEM
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// First part of LP mem is reserved for coprocessor
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PMP_ENTRY_SET(10, SOC_RTC_IRAM_LOW + CONFIG_ULP_COPROC_RESERVE_MEM, PMP_TOR | RW);
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#else // CONFIG_ULP_COPROC_RESERVE_MEM
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// Repeat same previous entry, to ensure next entry has correct base address (TOR)
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PMP_ENTRY_SET(10, SOC_RTC_IRAM_LOW, NONE);
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#endif // !CONFIG_ULP_COPROC_RESERVE_MEM
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PMP_ENTRY_SET(11, (int)&_rtc_text_end, PMP_TOR | RX);
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PMP_ENTRY_SET(12, SOC_RTC_IRAM_HIGH, PMP_TOR | RW);
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#else
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const uint32_t pmpaddr9 = PMPADDR_NAPOT(SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH);
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PMP_ENTRY_SET(9, pmpaddr9, PMP_NAPOT | CONDITIONAL_RWX);
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_Static_assert(SOC_RTC_IRAM_LOW < SOC_RTC_IRAM_HIGH, "Invalid RTC IRAM region");
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#endif
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// 7. Peripheral addresses
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const uint32_t pmpaddr13 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH);
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PMP_ENTRY_SET(13, pmpaddr13, PMP_NAPOT | RW);
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_Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region");
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}
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@ -26,6 +26,9 @@ SECTIONS
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*rtc_wake_stub*.*(.text .text.*)
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*(.rtc_text_end_test)
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/* Align the end of RTC code region as per PMP granularity */
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. = ALIGN(_esp_pmp_align_size);
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ALIGNED_SYMBOL(4, _rtc_text_end)
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} > lp_ram_seg
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@ -190,6 +193,9 @@ SECTIONS
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/* Marks the end of IRAM code segment */
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.iram0.text_end (NOLOAD) :
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{
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/* Align the end of code region as per PMP region granularity */
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. = ALIGN(_esp_pmp_align_size);
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ALIGNED_SYMBOL(4, _iram_text_end)
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} > sram_low
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@ -9,6 +9,18 @@
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/* CPU instruction prefetch padding size for flash mmap scenario */
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#define _esp_flash_mmap_prefetch_pad_size 16
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/*
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* PMP region granularity size
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* Software may determine the PMP granularity by writing zero to pmp0cfg, then writing all ones
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* to pmpaddr0, then reading back pmpaddr0. If G is the index of the least-significant bit set,
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* the PMP granularity is 2^G+2 bytes.
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*/
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#ifdef CONFIG_SOC_CPU_PMP_REGION_GRANULARITY
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#define _esp_pmp_align_size CONFIG_SOC_CPU_PMP_REGION_GRANULARITY
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#else
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#define _esp_pmp_align_size 0
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#endif
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/* CPU instruction prefetch padding size for memory protection scenario */
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#ifdef CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE
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#define _esp_memprot_prefetch_pad_size CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE
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@ -23,13 +23,13 @@ extern "C" {
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* @brief Given a L2MEM cached address, get the corresponding non-cacheable address
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* @example 0x4FF0_0000 => 0x8FF0_0000
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*/
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#define CACHE_LL_L2MEM_NON_CACHE_ADDR(addr) ((intptr_t)(addr) + SOC_NON_CACHEABLE_OFFSET)
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#define CACHE_LL_L2MEM_NON_CACHE_ADDR(addr) ((uintptr_t)(addr) + SOC_NON_CACHEABLE_OFFSET)
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/**
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* @brief Given a non-cacheable address, get the corresponding L2MEM cached address
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* @example 0x8FF0_0000 => 0x4FF0_0000
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*/
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#define CACHE_LL_L2MEM_CACHE_ADDR(non_cache_addr) ((intptr_t)(non_cache_addr) - SOC_NON_CACHEABLE_OFFSET)
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#define CACHE_LL_L2MEM_CACHE_ADDR(non_cache_addr) ((uintptr_t)(non_cache_addr) - SOC_NON_CACHEABLE_OFFSET)
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/**
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* Cache capabilities
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@ -78,7 +78,7 @@ extern "C" {
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do { \
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ESP_STATIC_ASSERT(__builtin_popcount((SIZE)) == 1, "Size must be a power of 2"); \
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ESP_STATIC_ASSERT((ADDR) % ((SIZE)) == 0, "Addr must be aligned to size"); \
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RV_WRITE_CSR((CSR_PMAADDR0) + (ENTRY), ((ADDR) | ((SIZE >> 1) - 1)) >> 2); \
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RV_WRITE_CSR((CSR_PMAADDR0) + (ENTRY), ((ADDR) | (((SIZE) >> 1) - 1)) >> 2); \
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RV_WRITE_CSR((CSR_PMACFG0) + (ENTRY), CFG); \
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} while (0)
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@ -119,7 +119,7 @@ extern "C" {
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generate specific assembly instructions.
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- ADDR is the address to write to the PMPADDRx register. Note this is the unshifted address.
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- CFG is the configuration value to write to the correct CFG entry register. Note that
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the macro only sets bits in the CFG register, so it sould be zeroed already.
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the macro only sets bits in the CFG register, so it should be zeroed already.
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*/
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#define PMP_ENTRY_SET(ENTRY, ADDR, CFG) do { \
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RV_WRITE_CSR((CSR_PMPADDR0) + (ENTRY), (ADDR) >> (PMP_SHIFT)); \
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|
|
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@ -435,6 +435,10 @@ config SOC_CPU_IDRAM_SPLIT_USING_PMP
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bool
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default y
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config SOC_CPU_PMP_REGION_GRANULARITY
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int
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default 128
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config SOC_DS_SIGNATURE_MAX_BIT_LEN
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int
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default 4096
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@ -189,6 +189,9 @@
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#define SOC_DIRAM_DRAM_HIGH 0x4ffc0000
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#define SOC_DIRAM_ROM_RESERVE_HIGH 0x4ff40000
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|
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#define MAP_DRAM_TO_IRAM(addr) (addr)
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#define MAP_IRAM_TO_DRAM(addr) (addr)
|
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|
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// Region of memory accessible via DMA. See esp_ptr_dma_capable().
|
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#define SOC_DMA_LOW 0x4ff00000
|
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#define SOC_DMA_HIGH 0x4ffc0000
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|
|
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|||
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@ -169,6 +169,7 @@
|
|||
|
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#define SOC_CPU_HAS_PMA 1
|
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#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1
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#define SOC_CPU_PMP_REGION_GRANULARITY 128
|
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|
||||
/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
|
||||
/** The maximum length of a Digital Signature in bits. */
|
||||
|
|
|
|||
|
|
@ -552,7 +552,8 @@ CONFIGS_MEMPROT_IDRAM = [
|
|||
pytest.param('memprot_esp32c3', marks=[pytest.mark.esp32c3]),
|
||||
pytest.param('memprot_esp32c2', marks=[pytest.mark.esp32c2]),
|
||||
pytest.param('memprot_esp32c6', marks=[pytest.mark.esp32c6]),
|
||||
pytest.param('memprot_esp32h2', marks=[pytest.mark.esp32h2])
|
||||
pytest.param('memprot_esp32h2', marks=[pytest.mark.esp32h2]),
|
||||
pytest.param('memprot_esp32p4', marks=[pytest.mark.esp32p4])
|
||||
]
|
||||
|
||||
CONFIGS_MEMPROT_DCACHE = [
|
||||
|
|
@ -563,7 +564,8 @@ CONFIGS_MEMPROT_RTC_FAST_MEM = [
|
|||
pytest.param('memprot_esp32s2', marks=[pytest.mark.esp32s2]),
|
||||
pytest.param('memprot_esp32c3', marks=[pytest.mark.esp32c3]),
|
||||
pytest.param('memprot_esp32c6', marks=[pytest.mark.esp32c6]),
|
||||
pytest.param('memprot_esp32h2', marks=[pytest.mark.esp32h2])
|
||||
pytest.param('memprot_esp32h2', marks=[pytest.mark.esp32h2]),
|
||||
pytest.param('memprot_esp32p4', marks=[pytest.mark.esp32p4])
|
||||
]
|
||||
|
||||
CONFIGS_MEMPROT_RTC_SLOW_MEM = [
|
||||
|
|
@ -572,7 +574,8 @@ CONFIGS_MEMPROT_RTC_SLOW_MEM = [
|
|||
|
||||
CONFIGS_MEMPROT_FLASH_IDROM = [
|
||||
pytest.param('memprot_esp32c6', marks=[pytest.mark.esp32c6]),
|
||||
pytest.param('memprot_esp32h2', marks=[pytest.mark.esp32h2])
|
||||
pytest.param('memprot_esp32h2', marks=[pytest.mark.esp32h2]),
|
||||
pytest.param('memprot_esp32p4', marks=[pytest.mark.esp32p4])
|
||||
]
|
||||
|
||||
|
||||
|
|
@ -609,7 +612,7 @@ def test_iram_reg1_write_violation(dut: PanicTestDut, test_func_name: str) -> No
|
|||
dut.expect_backtrace()
|
||||
elif dut.target == 'esp32c3':
|
||||
dut.expect_exact(r'Test error: Test function has returned')
|
||||
elif dut.target in ['esp32c2', 'esp32c6', 'esp32h2']:
|
||||
elif dut.target in ['esp32c2', 'esp32c6', 'esp32h2', 'esp32p4']:
|
||||
dut.expect_gme('Store access fault')
|
||||
dut.expect_reg_dump(0)
|
||||
dut.expect_stack_dump()
|
||||
|
|
@ -634,7 +637,7 @@ def test_iram_reg2_write_violation(dut: PanicTestDut, test_func_name: str) -> No
|
|||
dut.expect(r' operation type: (\S+)')
|
||||
dut.expect_reg_dump(0)
|
||||
dut.expect_stack_dump()
|
||||
elif dut.target in ['esp32c2', 'esp32c6', 'esp32h2']:
|
||||
elif dut.target in ['esp32c2', 'esp32c6', 'esp32h2', 'esp32p4']:
|
||||
dut.expect_gme('Store access fault')
|
||||
dut.expect_reg_dump(0)
|
||||
dut.expect_stack_dump()
|
||||
|
|
@ -659,7 +662,7 @@ def test_iram_reg3_write_violation(dut: PanicTestDut, test_func_name: str) -> No
|
|||
dut.expect(r' operation type: (\S+)')
|
||||
dut.expect_reg_dump(0)
|
||||
dut.expect_stack_dump()
|
||||
elif dut.target in ['esp32c2', 'esp32c6', 'esp32h2']:
|
||||
elif dut.target in ['esp32c2', 'esp32c6', 'esp32h2', 'esp32p4']:
|
||||
dut.expect_gme('Store access fault')
|
||||
dut.expect_reg_dump(0)
|
||||
dut.expect_stack_dump()
|
||||
|
|
@ -706,7 +709,7 @@ def test_dram_reg1_execute_violation(dut: PanicTestDut, test_func_name: str) ->
|
|||
dut.expect(r'Unknown operation at address [0-9xa-f]+ not permitted \((\S+)\)')
|
||||
dut.expect_reg_dump(0)
|
||||
dut.expect_corrupted_backtrace()
|
||||
elif dut.target in ['esp32c3', 'esp32c2', 'esp32c6', 'esp32h2']:
|
||||
elif dut.target in ['esp32c3', 'esp32c2', 'esp32c6', 'esp32h2', 'esp32p4']:
|
||||
dut.expect_gme('Instruction access fault')
|
||||
dut.expect_reg_dump(0)
|
||||
dut.expect_stack_dump()
|
||||
|
|
@ -725,7 +728,7 @@ def test_dram_reg2_execute_violation(dut: PanicTestDut, test_func_name: str) ->
|
|||
dut.expect_gme('InstructionFetchError')
|
||||
dut.expect_reg_dump(0)
|
||||
dut.expect_corrupted_backtrace()
|
||||
elif dut.target in ['esp32c3', 'esp32c2', 'esp32c6', 'esp32h2']:
|
||||
elif dut.target in ['esp32c3', 'esp32c2', 'esp32c6', 'esp32h2', 'esp32p4']:
|
||||
dut.expect_gme('Instruction access fault')
|
||||
dut.expect_reg_dump(0)
|
||||
dut.expect_stack_dump()
|
||||
|
|
@ -743,7 +746,7 @@ def test_rtc_fast_reg1_execute_violation(dut: PanicTestDut, test_func_name: str)
|
|||
|
||||
@pytest.mark.parametrize('config', CONFIGS_MEMPROT_RTC_FAST_MEM, indirect=True)
|
||||
@pytest.mark.generic
|
||||
@pytest.mark.skipif('config.getvalue("target") in ["esp32c6", "esp32h2"]', reason='Not a violation condition because it does not have PMS peripheral')
|
||||
@pytest.mark.skipif('config.getvalue("target") in ["esp32c6", "esp32h2", "esp32p4"]', reason='Not a violation condition, no PMS peripheral case')
|
||||
def test_rtc_fast_reg2_execute_violation(dut: PanicTestDut, test_func_name: str) -> None:
|
||||
dut.run_test_func(test_func_name)
|
||||
dut.expect_gme('Memory protection fault')
|
||||
|
|
@ -781,7 +784,7 @@ def test_rtc_fast_reg3_execute_violation(dut: PanicTestDut, test_func_name: str)
|
|||
dut.expect(r' operation type: (\S+)')
|
||||
dut.expect_reg_dump(0)
|
||||
dut.expect_stack_dump()
|
||||
elif dut.target in ['esp32c6', 'esp32h2']:
|
||||
elif dut.target in ['esp32c6', 'esp32h2', 'esp32p4']:
|
||||
dut.expect_gme('Instruction access fault')
|
||||
dut.expect_reg_dump(0)
|
||||
dut.expect_stack_dump()
|
||||
|
|
|
|||
|
|
@ -0,0 +1,8 @@
|
|||
# Restricting to ESP32P4
|
||||
CONFIG_IDF_TARGET="esp32p4"
|
||||
|
||||
# Enabling memory protection
|
||||
CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT=y
|
||||
|
||||
# Enable memprot test
|
||||
CONFIG_TEST_MEMPROT=y
|
||||
Ładowanie…
Reference in New Issue