kopia lustrzana https://github.com/espressif/esp-idf
193 wiersze
8.3 KiB
C
193 wiersze
8.3 KiB
C
// Copyright (c) 2013, The Regents of the University of California (Regents).
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// Copyright (c) 2018-2019, The libfemto authors
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// Copyright (c) 2020 Espressif Systems (Shanghai) PTE LTD
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// All Rights Reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// 1. Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// 3. Neither the name of the Regents nor the
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// names of its contributors may be used to endorse or promote products
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// derived from this software without specific prior written permission.
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// IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
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// SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
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// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
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// BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
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// HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
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// MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <stddef.h>
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#include <stdbool.h>
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#include <sys/param.h>
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#include "encoding.h"
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#include "esp_assert.h"
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/********************************************************
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Physical Memory Attributes (PMA) register fields
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(privileged spec)
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********************************************************/
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/********************************************************
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PMA CSR and TOR & NAPOT macros
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********************************************************/
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#define CSR_PMACFG0 0xBC0
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#define CSR_PMAADDR0 0xBD0
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#define CSR_PMACFG(i) (CSR_PMACFG0 + (i))
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#define CSR_PMAADDR(i) (CSR_PMAADDR0 + (i))
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#define PMA_EN BIT(0)
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#define PMA_R BIT(4)
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#define PMA_W BIT(3)
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#define PMA_X BIT(2)
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#define PMA_L BIT(29)
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#define PMA_SHIFT 2
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#define PMA_TOR 0x40000000
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#define PMA_NA4 0x80000000
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#define PMA_NAPOT 0xC0000000
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#define PMA_NONCACHEABLE BIT(27)
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#define PMA_WRITETHROUGH BIT(26)
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#define PMA_WRITEMISSNOALLOC BIT(25)
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#define PMA_READMISSNOALLOC BIT(24)
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#define PMA_ENTRY_SET_TOR(ENTRY, ADDR, CFG) \
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do { \
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RV_WRITE_CSR((CSR_PMAADDR0) + (ENTRY), (ADDR) >> (PMA_SHIFT)); \
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RV_WRITE_CSR((CSR_PMACFG0) + (ENTRY), CFG); \
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} while (0)
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#define PMA_ENTRY_SET_NAPOT(ENTRY, ADDR, SIZE, CFG) \
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do { \
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ESP_STATIC_ASSERT(__builtin_popcount((SIZE)) == 1, "Size must be a power of 2"); \
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ESP_STATIC_ASSERT((ADDR) % ((SIZE)) == 0, "Addr must be aligned to size"); \
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RV_WRITE_CSR((CSR_PMAADDR0) + (ENTRY), ((ADDR) | (((SIZE) >> 1) - 1)) >> 2); \
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RV_WRITE_CSR((CSR_PMACFG0) + (ENTRY), CFG); \
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} while (0)
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/********************************************************
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Physical Memory Protection (PMP) register fields
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(privileged spec)
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********************************************************/
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/* Value of pmpcfg0 CSR. Note this macro is only needed for calculations like (CSR_PMPCFG0 + 1), which must
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still be constant at compile time. Use the assembler name pmpcfg0, pmpcfg1, pmpcfg2, etc. in other cases */
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#define CSR_PMPCFG0 0x3A0
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/* Value of pmpaddr0 CSR. Note, as above, this macro is only needed for calculations and the assembler names
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pmpaddr0, pmpaddr1, pmpaddr2, etc should be used otherwise. */
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#define CSR_PMPADDR0 0x3B0
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/* Generate the PMP address field value when PMPCFG.A == NAPOT
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START & END should be calculated at compile time. The size of the region
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(END-START) must be a power of 2 size, and START must be aligned to this
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size.
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Note: this value must be right-shifted PMP_SHIFT when written to the PMPADDR
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register. The PMP_ENTRY_SET macro will do this.
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*/
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#define PMPADDR_NAPOT(START, END) ({ \
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ESP_STATIC_ASSERT(__builtin_popcount((END)-(START)) == 1, "Size must be a power of 2"); \
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ESP_STATIC_ASSERT((START) % ((END)-(START)) == 0, "Start must be aligned to size"); \
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(((START)) | (((END)-(START)-1)>>1)); \
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})
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#define PMPADDR_ALL 0xFFFFFFFF
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/* Set a PMP entry.
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- ENTRY is number of the PMP entry to set. This must be a compile-time constant because it's used to
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generate specific assembly instructions.
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- ADDR is the address to write to the PMPADDRx register. Note this is the unshifted address.
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- CFG is the configuration value to write to the correct CFG entry register. Note that
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the macro only sets bits in the CFG register, so it should be zeroed already.
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*/
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#define PMP_ENTRY_SET(ENTRY, ADDR, CFG) do { \
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RV_WRITE_CSR((CSR_PMPADDR0) + (ENTRY), (ADDR) >> (PMP_SHIFT)); \
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RV_SET_CSR((CSR_PMPCFG0) + (ENTRY)/4, ((CFG)&0xFF) << (ENTRY%4)*8); \
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} while(0)
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/*Only set PMPCFG entries*/
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#define PMP_ENTRY_CFG_SET(ENTRY, CFG) do {\
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RV_SET_CSR((CSR_PMPCFG0) + (ENTRY)/4, ((CFG)&0xFF) << (ENTRY%4)*8); \
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} while(0)
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/*Reset all permissions of a particular PMPCFG entry*/
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#define PMP_ENTRY_CFG_RESET(ENTRY) do {\
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RV_CLEAR_CSR((CSR_PMPCFG0) + (ENTRY)/4, (0xFF) << (ENTRY%4)*8); \
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} while(0)
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/********************************************************
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Trigger Module register fields (Debug specification)
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********************************************************/
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#define TCONTROL_MTE (1<<3) /*R/W, Current M mode trigger enable bit*/
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#define TCONTROL_MPTE (1<<7) /*R/W, Previous M mode trigger enable bit*/
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#define TDATA1_LOAD (1<<0) /*R/W,Fire trigger on load address match*/
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#define TDATA1_STORE (1<<1) /*R/W,Fire trigger on store address mat*/
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#define TDATA1_EXECUTE (1<<2) /*R/W,Fire trigger on instruction fetch address match*/
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#define TDATA1_USER (1<<3) /*R/W,allow trigger to be fired in user mode*/
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#define TDATA1_MACHINE (1<<6) /*R/W,Allow trigger to be fired while hart is executing in machine mode*/
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#define TDATA1_MATCH_EXACT (0)
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#define TDATA1_MATCH_NAPOT (1<<7)
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#define TDATA1_MATCH_V (0xF) /*R/W,Address match type :0 : Exact byte match 1 : NAPOT range match */
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#define TDATA1_MATCH_S (7)
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#define TDATA1_HIT_S (20)
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/* RISC-V CSR macros
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* Adapted from https://github.com/michaeljclark/riscv-probe/blob/master/libfemto/include/arch/riscv/machine.h
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*/
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#define RV_READ_CONST_CSR(reg) ({ unsigned long __tmp; \
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asm ("csrr %0, " _CSR_STRINGIFY(reg) : "=r"(__tmp)); __tmp; })
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#define RV_READ_CSR(reg) ({ unsigned long __tmp; \
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asm volatile ("csrr %0, " _CSR_STRINGIFY(reg) : "=r"(__tmp)); __tmp; })
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#define RV_WRITE_CSR(reg, val) ({ \
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asm volatile ("csrw " _CSR_STRINGIFY(reg) ", %0" :: "rK"(val)); })
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#define RV_SWAP_CSR(reg, val) ({ unsigned long __tmp; \
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asm volatile ("csrrw %0, " _CSR_STRINGIFY(reg) ", %1" : "=r"(__tmp) : "rK"(val)); __tmp; })
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/* Note: this uses the atomic read-and-set instruction so possible to read the old CSR value as a result */
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#define RV_SET_CSR(reg, bit) ({ unsigned long __tmp; \
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asm volatile ("csrrs %0, " _CSR_STRINGIFY(reg) ", %1" : "=r"(__tmp) : "rK"(bit)); __tmp; })
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/* Note: this uses the atomic read-and-clear instruction so possible to read the old CSR value as a result */
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#define RV_CLEAR_CSR(reg, bit) ({ unsigned long __tmp; \
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asm volatile ("csrrc %0, " _CSR_STRINGIFY(reg) ", %1" : "=r"(__tmp) : "rK"(bit)); __tmp; })
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#define RV_SET_CSR_FIELD(_r, _f, _v) ({ (RV_WRITE_CSR((_r),((RV_READ_CSR(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))));})
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#define RV_CLEAR_CSR_FIELD(_r, _f) ({ (RV_WRITE_CSR((_r),(RV_READ_CSR(_r) & ~((_f##_V) << (_f##_S)))));})
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#define RV_READ_MSTATUS_AND_DISABLE_INTR() ({ unsigned long __tmp; \
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asm volatile ("csrrci %0, mstatus, 0x8" : "=r"(__tmp)); __tmp; })
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#define _CSR_STRINGIFY(REG) #REG /* needed so the 'reg' argument can be a macro or a register name */
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#ifdef __cplusplus
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}
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#endif
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