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feat(esp32c5): support esp32c5 beta3 48M xtal

pull/13090/head
laokaiyao 2023-12-19 13:49:26 +08:00
rodzic 96a4ead083
commit 3d459e423a
22 zmienionych plików z 49 dodań i 173 usunięć
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15
Kconfig
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@ -119,6 +119,21 @@ mainmenu "Espressif IoT Development Framework Configuration"
select FREERTOS_UNICORE
select IDF_TARGET_ARCH_RISCV
choice IDF_TARGET_ESP32C5_VERSION
prompt "ESP32-C5 version"
depends on IDF_TARGET_ESP32C5
default IDF_TARGET_ESP32C5_BETA3_VERSION
help
ESP32-C5 will support two versions in a period.
This option is for internal use only.
Select the one that matches your chip model.
config IDF_TARGET_ESP32C5_BETA3_VERSION
bool
prompt "ESP32-C5 beta3"
select ESPTOOLPY_NO_STUB
endchoice
config IDF_TARGET_ESP32P4
bool
default "y" if IDF_TARGET="esp32p4"

19
components/bootloader_support/src/bootloader_clock_init.c
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@ -53,20 +53,16 @@ __attribute__((weak)) void bootloader_clock_configure(void)
clk_cfg.cpu_freq_mhz = cpu_freq_mhz;
#if CONFIG_IDF_TARGET_ESP32C5
// RC150K can't do calibrate on esp32c5MPW so not use it
clk_cfg.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC32K;
#else
// Use RTC_SLOW clock source sel register field's default value, RC_SLOW, for 2nd stage bootloader
// RTC_SLOW clock source will be switched according to Kconfig selection at application startup
clk_cfg.slow_clk_src = rtc_clk_slow_src_get();
if (clk_cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_INVALID) {
#if CONFIG_IDF_TARGET_ESP32C5
clk_cfg.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC32K;
#else
clk_cfg.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
#endif
}
#if CONFIG_IDF_TARGET_ESP32C5
// RC150K can't do calibrate on esp32c5MPW so not use it
clk_cfg.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC32K;
#endif
#if CONFIG_IDF_TARGET_ESP32C6
@ -85,9 +81,10 @@ __attribute__((weak)) void bootloader_clock_configure(void)
}
#if CONFIG_IDF_TARGET_ESP32C5
/* Configure clk mspi fast to 80m*/
clk_ll_mspi_fast_set_divider(6);
clk_ll_mspi_fast_sel_clk(MSPI_CLK_SRC_SPLL);
/* TODO: [ESP32C5] IDF-8649 temporary use xtal clock source,
need to change back SPLL(480M) and set divider to 6 to use the 80M MSPI */
clk_ll_mspi_fast_set_divider(1);
clk_ll_mspi_fast_sel_clk(MSPI_CLK_SRC_XTAL);
#endif
/* As a slight optimization, if 32k XTAL was enabled in sdkconfig, we enable

4
components/console/CMakeLists.txt
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@ -5,10 +5,6 @@ if(${target} STREQUAL "linux")
# future (TODO: IDF-8103)
endif()
if(${target} STREQUAL "esp32c5")
return() # Not support yet
endif()
set(argtable_srcs argtable3/arg_cmd.c
argtable3/arg_date.c
argtable3/arg_dbl.c

1
components/esp_hw_support/modem_clock.c
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@ -75,7 +75,6 @@ static void IRAM_ATTR modem_clock_wifi_bb_configure(modem_clock_context_t *ctx,
#if SOC_BT_SUPPORTED
static void IRAM_ATTR modem_clock_ble_mac_configure(modem_clock_context_t *ctx, bool enable)
{
modem_syscon_ll_enable_bt_mac_clock(ctx->hal->syscon_dev, enable);
modem_syscon_ll_enable_modem_sec_clock(ctx->hal->syscon_dev, enable);
modem_syscon_ll_enable_ble_timer_clock(ctx->hal->syscon_dev, enable);
}

5
components/esp_hw_support/port/esp32c5/ocode_init.c
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@ -13,8 +13,7 @@
#include "esp_hw_log.h"
// TODO: [ESP32C5] IDF-8702
// static const char *TAG = "ocode_init";
static const char *TAG = "ocode_init";
static void set_ocode_by_efuse(int ocode_scheme_ver)
{
@ -28,6 +27,8 @@ static void calibrate_ocode(void)
void esp_ocode_calib_init(void)
{
// TODO: [ESP32C5] IDF-8702
ESP_HW_LOGW(TAG, "esp_ocode_calib_init() has not implemented yet");
if (efuse_hal_blk_version() >= 1) {
set_ocode_by_efuse(1);
} else {

3
components/esp_hw_support/port/esp32c5/rtc_time.c
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@ -20,8 +20,6 @@
static const char *TAG = "rtc_time";
// TODO: [ESP32C5] IDF-8667
/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* RTC_SLOW_CLK cycles.
@ -252,6 +250,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
// TODO: [ESP32C5] IDF-8667
// return lp_timer_hal_get_cycle_count();
ESP_EARLY_LOGW(TAG, "rtc_time_get has not been implemented yet");
return 0;

4
components/esp_local_ctrl/CMakeLists.txt
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@ -4,10 +4,6 @@ if(${target} STREQUAL "linux")
return() # This component is not supported by the POSIX/Linux simulator
endif()
if(${target} STREQUAL "esp32c5")
return() # not support yet
endif()
set(include_dirs include)
set(priv_include_dirs proto-c src ../protocomm/proto-c)
set(srcs "src/esp_local_ctrl.c"

2
components/esp_system/fpga_overrides_clk.c
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@ -27,8 +27,6 @@
#include "esp32h2/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32P4
#include "esp32p4/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C5
#include "esp32c5/rom/rtc.h"
#endif
#include "esp_log.h"
#include "esp_rom_sys.h"

4
components/esp_system/panic.c
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@ -79,7 +79,7 @@ static wdt_hal_context_t rtc_wdt_ctx = RWDT_HAL_CONTEXT_DEFAULT();
#if !CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT
#if CONFIG_ESP_CONSOLE_UART && SOC_UART_SUPPORTED
#if CONFIG_ESP_CONSOLE_UART
static uart_hal_context_t s_panic_uart = { .dev = CONFIG_ESP_CONSOLE_UART_NUM == 0 ? &UART0 :&UART1 };
static void panic_print_char_uart(const char c)
@ -122,7 +122,7 @@ static void panic_print_char_usb_serial_jtag(const char c)
void panic_print_char(const char c)
{
#if CONFIG_ESP_CONSOLE_UART && SOC_UART_SUPPORTED
#if CONFIG_ESP_CONSOLE_UART
panic_print_char_uart(c);
#endif
#if CONFIG_ESP_CONSOLE_USB_CDC

14
components/esp_system/port/cpu_start.c
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@ -70,6 +70,7 @@
#include "soc/hp_sys_clkrst_reg.h"
#include "soc/interrupt_core0_reg.h"
#include "soc/interrupt_core1_reg.h"
#include "soc/keymng_reg.h"
#endif
#include "esp_private/rtc_clk.h"
@ -155,18 +156,16 @@ static volatile bool s_resume_cores;
static void core_intr_matrix_clear(void)
{
uint32_t core_id = esp_cpu_get_core_id();
for (int i = 0; i < ETS_MAX_INTR_SOURCE; i++) {
#if CONFIG_IDF_TARGET_ESP32P4
uint32_t core_id = esp_cpu_get_core_id();
if (core_id == 0) {
REG_WRITE(INTERRUPT_CORE0_LP_RTC_INT_MAP_REG + 4 * i, ETS_INVALID_INUM);
} else {
REG_WRITE(INTERRUPT_CORE1_LP_RTC_INT_MAP_REG + 4 * i, ETS_INVALID_INUM);
}
// #elif CONFIG_IDF_TARGET_ESP32C5
// REG_WRITE(INTMTX_CORE0_WIFI_MAC_INT_MAP_REG + 4 * i, 0);
#else
uint32_t core_id = esp_cpu_get_core_id();
esp_rom_route_intr_matrix(core_id, i, ETS_INVALID_INUM);
#endif // CONFIG_IDF_TARGET_ESP32P4
}
@ -307,6 +306,11 @@ static void start_other_core(void)
if(REG_GET_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL)){
REG_CLR_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL);
}
// The following operation makes the Key Manager to use eFuse key for ECDSA and XTS-AES operation by default
// This is to keep the default behavior same as the other chips
// If the Key Manager configuration is already locked then following operation does not have any effect
// TODO-IDF 7925 (Move this under SOC_KEY_MANAGER_SUPPORTED)
REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY, 3);
#endif
ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
@ -700,7 +704,7 @@ void IRAM_ATTR call_start_cpu0(void)
if (rst_reas[0] == RESET_REASON_CORE_DEEP_SLEEP) {
esp_deep_sleep_wakeup_io_reset();
}
#endif //#if !CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_IDF_TARGET_ESP32C5
#endif //#if !CONFIG_IDF_TARGET_ESP32P4 & !CONFIG_IDF_TARGET_ESP32C5
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
esp_cache_err_int_init();

2
components/esp_system/startup_funcs.c
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@ -147,7 +147,7 @@ ESP_SYSTEM_INIT_FN(init_psram_heap, CORE, BIT(0), 103)
return ESP_OK;
}
#if CONFIG_ESP_BROWNOUT_DET && SOC_BOD_SUPPORTED
#if CONFIG_ESP_BROWNOUT_DET
ESP_SYSTEM_INIT_FN(init_brownout, CORE, BIT(0), 104)
{
// [refactor-todo] leads to call chain rtc_is_register (driver) -> esp_intr_alloc (esp32/esp32s2) ->

3
components/esptool_py/Kconfig.projbuild
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@ -90,7 +90,8 @@ menu "Serial flasher config"
choice ESPTOOLPY_FLASHFREQ
prompt "Flash SPI speed"
default ESPTOOLPY_FLASHFREQ_40M if IDF_TARGET_ESP32
# TODO: [ESP32C5] IDF-8649 switch back to 80M
default ESPTOOLPY_FLASHFREQ_40M if IDF_TARGET_ESP32 || IDF_TARGET_ESP32C5
default ESPTOOLPY_FLASHFREQ_80M if ESPTOOLPY_FLASHFREQ_80M_DEFAULT
default ESPTOOLPY_FLASHFREQ_60M if IDF_TARGET_ESP32C2
config ESPTOOLPY_FLASHFREQ_120M

7
components/esptool_py/project_include.cmake
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@ -7,6 +7,13 @@ idf_build_get_property(idf_path IDF_PATH)
set(chip_model ${target})
# TODO: [ESP32C5] remove this 'if' block when esp32C5 beta3 is no longer supported
if(target STREQUAL "esp32c5")
if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
set(chip_model esp32c5beta3)
endif()
endif()
set(ESPTOOLPY ${python} "$ENV{ESPTOOL_WRAPPER}" "${CMAKE_CURRENT_LIST_DIR}/esptool/esptool.py" --chip ${chip_model})
set(ESPSECUREPY ${python} "${CMAKE_CURRENT_LIST_DIR}/esptool/espsecure.py")
set(ESPEFUSEPY ${python} "${CMAKE_CURRENT_LIST_DIR}/esptool/espefuse.py")

5
components/fatfs/CMakeLists.txt
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@ -1,10 +1,5 @@
idf_build_get_property(target IDF_TARGET)
if(${target} STREQUAL "esp32c5")
return() # not support yet
endif()
set(srcs "diskio/diskio.c"
"diskio/diskio_rawflash.c"
"diskio/diskio_wl.c"

17
components/hal/esp32c5/include/hal/lp_aon_hal.h
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@ -1,17 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "hal/lp_aon_ll.h"
#define rtc_hal_ext1_get_wakeup_status() lp_aon_ll_ext1_get_wakeup_status()
#define rtc_hal_ext1_clear_wakeup_status() lp_aon_ll_ext1_clear_wakeup_status()
#define rtc_hal_ext1_set_wakeup_pins(io_mask, mode_mask) lp_aon_ll_ext1_set_wakeup_pins(io_mask, mode_mask)
#define rtc_hal_ext1_clear_wakeup_pins() lp_aon_ll_ext1_clear_wakeup_pins()
#define rtc_hal_ext1_get_wakeup_pins() lp_aon_ll_ext1_get_wakeup_pins()
#define lp_aon_hal_inform_wakeup_type(dslp) lp_aon_ll_inform_wakeup_type(dslp)

97
components/hal/esp32c5/include/hal/lp_aon_ll.h
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@ -1,97 +0,0 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-C5 LP_AON register operations
#pragma once
#include <stdlib.h>
#include "soc/soc.h"
#include "soc/lp_aon_struct.h"
#include "hal/misc.h"
#include "esp32c5/rom/rtc.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Get ext1 wakeup source status
* @return The lower 8 bits of the returned value are the bitmap of
* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
*/
static inline uint32_t lp_aon_ll_ext1_get_wakeup_status(void)
{
return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status);
}
/**
* @brief Clear the ext1 wakeup source status
*/
static inline void lp_aon_ll_ext1_clear_wakeup_status(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status_clr, 1);
}
/**
* @brief Set the wake-up LP_IO of the ext1 wake-up source
* @param io_mask wakeup LP_IO bitmap, bit 0~7 corresponds to LP_IO 0~7
* @param level_mask LP_IO wakeup level bitmap, bit 0~7 corresponds to LP_IO 0~7 wakeup level
* each bit's corresponding position is set to 0, the wakeup level will be low
* on the contrary, each bit's corresponding position is set to 1, the wakeup
* level will be high
*/
static inline void lp_aon_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t level_mask)
{
uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
wakeup_sel_mask |= io_mask;
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, wakeup_sel_mask);
uint32_t wakeup_level_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv);
wakeup_level_mask |= io_mask & level_mask;
wakeup_level_mask &= ~(io_mask & ~level_mask);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, wakeup_level_mask);
}
/**
* @brief Clear all ext1 wakup-source setting
*/
static inline void lp_aon_ll_ext1_clear_wakeup_pins(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, 0);
}
/**
* @brief Get ext1 wakeup source setting
* @return The lower 8 bits of the returned value are the bitmap of
* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
*/
static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void)
{
return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
}
/**
* @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0].
* Set the flag to inform
* @param true: deepsleep false: lightsleep
*/
static inline void lp_aon_ll_inform_wakeup_type(bool dslp)
{
if (dslp) {
REG_SET_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */
} else {
REG_CLR_BIT(SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */
}
}
#ifdef __cplusplus
}
#endif

2
components/hal/esp32c5/include/hal/lpwdt_ll.h
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@ -22,7 +22,7 @@ extern "C" {
#include "esp_attr.h"
#include "esp_assert.h"
#include "esp32c5/rom/ets_sys.h"
#include "esp32c6/rom/ets_sys.h"
/* The value that needs to be written to LP_WDT_WPROTECT_REG to write-enable the wdt registers */
#define LP_WDT_WKEY_VALUE 0x50D83AA1

4
components/protocomm/CMakeLists.txt
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@ -4,10 +4,6 @@ if(${target} STREQUAL "linux")
return() # This component is not supported by the POSIX/Linux simulator
endif()
if(${target} STREQUAL "esp32c5")
return() # not support yet
endif()
set(include_dirs include/common
include/security
include/transports

4
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
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@ -83,10 +83,6 @@ config SOC_CPU_HAS_FLEXIBLE_INTC
bool
default y
config SOC_INT_PLIC_SUPPORTED
bool
default n
config SOC_INT_CLIC_SUPPORTED
bool
default y

1
components/soc/esp32c5/include/soc/soc_caps.h
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@ -141,7 +141,6 @@
#define SOC_CPU_CORES_NUM (1U)
#define SOC_CPU_INTR_NUM 32
#define SOC_CPU_HAS_FLEXIBLE_INTC 1
#define SOC_INT_PLIC_SUPPORTED 0 //riscv platform-level interrupt controller
#define SOC_INT_CLIC_SUPPORTED 1
#define SOC_INT_HW_NESTED_SUPPORTED 1 // Support for hardware interrupts nesting
#define SOC_BRANCH_PREDICTOR_SUPPORTED 1

5
components/spiffs/CMakeLists.txt
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@ -1,10 +1,5 @@
idf_build_get_property(target IDF_TARGET)
if(${target} STREQUAL "esp32c5")
return() # not support yet
endif()
set(original_srcs "spiffs/src/spiffs_cache.c"
"spiffs/src/spiffs_check.c"
"spiffs/src/spiffs_gc.c"

4
components/vfs/CMakeLists.txt
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@ -4,10 +4,6 @@ if(${target} STREQUAL "linux")
return() # This component is not supported by the POSIX/Linux simulator
endif()
if(${target} STREQUAL "esp32c5")
return() # not support yet
endif()
list(APPEND sources "vfs.c"
"vfs_eventfd.c"
"vfs_semihost.c"