cariboulabs-cariboulite/firmware/top.asc

12838 wiersze
593 KiB
Plaintext

.comment from next-pnr
.device 1k
.io_tile 1 0
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 2 0
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 3 0
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 4 0
000000000000000010
000000000000000000
000000000000000000
000000000000000001
000010000001010001
000011110011010000
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000010000000001100
000011110000001100
000001111000000000
000000001000000000
000000000000000000
000000000000000000
.io_tile 5 0
000000000000000010
000100000000000000
000001111000000000
000011011001100001
000000110000110001
000000000011110000
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000001111001010110
000000001011011000
000000000000000000
000000000000010001
000001011000000001
000000001000000000
.io_tile 6 0
000000000000000010
000100000000000000
000010000000000000
000011110000000001
000001111001111101
000000000011110100
001101010000000000
000000000000000000
000000000000000000
000000000000000000
000010000000111110
010011110011111000
000000000000000000
000000000000000001
000011110000000001
000001110000000000
.io_tile 7 0
000000000000000010
000000000000000000
000011011000000000
000010110000000001
000000011000010101
000000001011110100
001100000000000000
000011110000100000
000000000000000000
000100000000000000
000000000000000100
000000000000001000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 8 0
000000000000000000
000000000000000000
000000000000000000
010000000000000001
000000000000000000
000000000000000000
001100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 9 0
000000000000000010
000100000000000000
000001010000000000
000000001000000001
000000000000100001
000000000011110000
001100000000100000
000000000000000000
000000000000000000
000100000000000000
000001111000111110
000000000000011100
000001111000000000
000011010000001001
000000000000000010
000000000000000000
.io_tile 10 0
000000000000000000
000100000000000000
000001111000000000
100000000000000001
000001010000000000
000000001000000000
001100000000001000
000000000000000000
000000000000000000
000000000000000000
000000000011001110
000000000011111000
000000000000000000
000000000000000001
000001010000000001
000000001000000000
.io_tile 11 0
000000000000000010
000100000000000000
000000000000000000
000000000000000001
000000000001100001
000000000001010000
001000000001000000
000000000000000000
000010111000000000
000100111000000001
100000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 12 0
000000000000001000
011100000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000001
001000000000000000
000000000000000000
100000000000000000
000000000000000000
100000000000000000
100000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 0 1
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 1
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 2 1
000000000000000000000000000011000001100000010000000000
000000000000001101000000000101001001110110110000000000
001000000000000000000111000000011101110000000100000000
100000000000000000000110110000001001110000000000000000
010001000000000001100000011111100000101001010100000000
100000000000000000000010000011100000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000011000000000111101100110001010000000000
000000000000000000100000000000101000110001010000000000
000000000000001000000000000000000000000000000000000000
000000000000001011000000000000000000000000000000000000
000000000000000000000000001000000000100000010100000000
000000000000000000000000000011001010010000100000000000
110000000000000000000000010011100000100000010100000001
000000000000000000000010000000001011100000010000000001
.ramb_tile 3 1
000000000000001000000000001000000000000000
000000000110000101000000000101001010000000
001000000000001000000000001001000001000000
100000000000000101000010010101001111000000
010000000001000011100011101000000000000000
110000000000100000000000001001000000000000
000000000000000011100011111000000000000000
000000000000001001000111100111000000000000
000000000100000001000000001000000000000000
000000000000000000100000001101000000000000
000000000000000000000000001001100000000000
000000000000001001000000001101000000000000
000000000000000000000000001000000000000000
000000000000000000000000000011000000000000
110000000000000111000000000000000000000000
110000000000000111000010010011000000000000
.logic_tile 4 1
000000000000000000000000001000000000000000000100000000
000000000000000000000000001011000000000010000000000000
101000000000000000000000000000011100000100000100000000
000000000000000000000000000000000000000000000010000000
000000000000001000000110000000000000000000000100000000
000000000000000001000000001101000000000010000010000001
000000000000000000000000000011000000000000000100000000
000000000000000000000000000000000000000001000000000000
000000000000001000000000000111100000000000000100000001
000000000000001011000000000000100000000001000010000000
000000000000001000000000010000000000000000100100000000
000000000000000101000010100000001010000000000010000100
000000000000000000000000000000000001000000100100000000
000000000000000000000000000000001111000000000000000000
000000000000000000000010010000000000000000000000000000
000000000000000000000110000000000000000000000000000000
.logic_tile 5 1
100000000000000000000000000000000000010110100100000000
000000000000000000000000000011000000101001010010000000
001000000000000000000000000000000000000000000100000000
100000000000000000000000001111000000000010000000000101
010000000000000000000010100000000000000000000110000000
110000000000000000000100000111000000000010000000000100
000000000000000000000000001000000000000000000100000100
000000000000001101000000000111000000000010000000000000
000000000000001000000000000000001110001100110100000000
000000000010000001000000000000011111001100110000000000
000000000000000000000110100111000000000000000100000100
000000000000000000000000000000100000000001000000000000
000000000000000101100110110101100000000000000100000000
000000000000000000000010100000000000000001000000000000
010000000000001000000000001000000000000000000100000001
000000000000000101000000001011000000000010000000000100
.logic_tile 6 1
000000000000000000000000010101000000000000001000000000
000000000000000000000010100000000000000000000000001000
000000000000000101100000000001011010001100111000000000
000000000000000000000000000000100000110011000000000100
000000000000001101100110100000001000001100111000000000
000000000000000101000000000000001010110011000000000000
000000000000000111100110100000001001001100111000000000
000000000000000000000000000000001000110011000000000000
000000000000000000000000000000001000001100111000000000
000000000000000000000000000000001011110011000000000000
000000000000000000000000000011101000001100111000000000
000000000000000000000010100000100000110011000000000000
000000000000000000000000000000001001001100111000000000
000000000000000000000000000000001110110011000000000000
000000000000000101000000000101101000001100111000000000
000000000000000000000000000000100000110011000000000000
.logic_tile 7 1
100000000000000001100111101001000000000000000000000000
000000000000000000000000000011100000111111110000000101
001010100000000000000000000000000000000000100100000000
100001000000000000000000000000001111000000000000000000
000000000000000000000000000001000000000000000100000000
000000000000000000000000000000000000000001000000000100
000010000000000000000000000111100001011001100000000000
000001000000000000000000000000001111011001100000100100
000000000000000000000010110000001100000100000100000000
000000000000000000000010100000010000000000000010000000
000000000000011000000000000000000000001111000010000000
000000000000100101000010110000001110001111000000000000
000000000000000101100010100000000000011001100000000010
000000000100001011000110101011001110100110010000000001
000000000000000101100000010111011100101111000000000000
000000000000000000000010100000111110101111000000000000
.logic_tile 8 1
000000000000000000000000000000000000000000001000000000
000000000000000000000000000000001110000000000000001000
000000000000000000000010100000001111001100111000000000
000000000010101101000100000000001101110011000001000000
000000000000000000000000000000001000001100111000000000
000000000000000000000000000000001101110011000000000000
000010000000000101000000000101101000001100111010000000
000001001000000000100000000000000000110011000000000000
000000000000000000000000010000001001001100111000000101
000000000000000000000010100000001100110011000000000000
000000000000010000000110100001101000001100111000000101
000000000000101001000000000000000000110011000000000000
000000000000000101100110100000001000001100111000000100
000000000000000000000000000000001111110011000000000000
000000000000000000000000000000001001001100111000000100
000001001000000000000000000000001001110011000010000001
.logic_tile 9 1
000000000000000101100000010000000000000000000000000000
000000000000000000000010100000000000000000000000000000
101000000000000000000000010111000000010110100100000000
000000000000000000000010100000000000010110100000000000
010000000000000000000111100000000000000000100100000000
110000000000000000000000000000001001000000000000000001
000000000000000000000000000000011000000100000100000000
000000000000000000000000000000010000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000001100000000000000000000000000000000000
000000000000010000000000000000000000000000000000000000
010000000000000000000000000000000000000000100110000000
000000000000000000000000000000001000000000000010000000
.ramb_tile 10 1
000000000000000000000000000000000000000000
000000010000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000001000000000000000000000000000000000
.logic_tile 11 1
000010000000000000000000000000011000101000000000000000
000000000000000000000000000101000000010100000000000000
000000000000000111000000000000000000000000000000000000
000000000000000000100000000000000000000000000000000000
000000000000100001000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000010000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 12 1
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000110000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000100000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.io_tile 13 1
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 0 2
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 2
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000001000000000100000010100000000
100000000000000000000000000011001011010000100000000001
010000000000000000000000010011111110101000000100000000
100000000000000000000010000000010000101000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000101100000000000000000000000000000000000
000000000000000000100000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
110000000000000000000000010000000000000000000000000000
000000000000000000000011010000000000000000000000000000
.logic_tile 2 2
000000000001011000000000011111100000101001010100000000
000000000000000001000010101001100000000000000000000000
001000000000000000000000010101011100101001010000000000
100000000000000000000011011101110000101010100000000000
110000000000000101100110000101100001101001010000000000
110000000000001101000010100101001101100110010010000000
000000000000001000000000000001011000101000000100000000
000000000000000001000010110000010000101000000000000000
000000000000000000000000001000011010101000000100000000
000000000000000000000000001001010000010100000000000000
000000000000000000000000000001100001100000010100000100
000000000000000000000011000000101010100000010000000000
000000000000000000000010001000001010101000000100000000
000000000000000000000000001001000000010100000000000000
110000000000000000000000010011101001110100010000000000
100000000000000000000010000000111011110100010000000010
.ramt_tile 3 2
000000010000000000000000001000000000000000
000000000000000111000000000101001000000000
101000010000000000000000001111100000000000
000000000000001111000000001111001010000000
010000000100000000000111101000000000000000
110000000000000001000100001101000000000000
000000000000000011100011101000000000000000
000000000000000111100010001101000000000000
000010000000000000000000000000000000000000
000000000000000001000000000011000000000000
000000000000000001000000001011100000000000
000000000000000001000000000101000000000000
000000000000000000000000001000000000000000
000000000000000000000000001111000000000000
010000000000000011100010011000000000000000
010000000000000000000011010011000000000000
.logic_tile 4 2
100010000000000101100111101101101010101000000000000000
000000000000000111000100000001111000010000100000000001
111000000000000000000000001000000000000000000100000000
100000000000001111000000000101000000000010000000000100
110000000000000000000000011000000000000000000100000000
000000000000000000000010000111000000000010000000000000
000000000000001101100000010000000000000000100100000000
000000001100000111000011100000001001000000000000000000
000010100000010000000000001000000000000000000100000000
000000000000000000000000000101000000000010000000000000
000000000000000001100000000000000000000000100100000000
000000000000000000100000000000001000000000000000000001
000000000000000001100000000000000000000000100100000000
000000000000000000100000000000001110000000000000000010
010000000000000101000000001000000000000000000100000000
000000000000000000100000000011000000000010000000000001
.logic_tile 5 2
000000000000000001100110000001001001010010000000000000
000000000000000000000111100111011000010110100000000000
001000000000001000000110010101001110100100000000000000
100000000000001001000110010000111011100100000000000000
010000000000000000000110010000011001001100110000000000
010000000000000000000110010000011001001100110000000000
000000000001010000000000000111100000101111010001000000
000000000000100000000000000000001111101111010001100000
000000000000000000000010100000000001011001100000000000
000000000000000000000000001101001000100110010000000000
000000000001010000000110000000000000000000100100000000
000000001110100000000000000000001101000000000000000000
000000000000000001000010000111111100000011010000000000
000000000000000000100111100000011110000011010000000000
010000000000001001100000000111001010000100100000000000
000000000000000001000000000000111011000100100000000000
.logic_tile 6 2
100000000000001000000010100111001000001100111000000000
000000000000000001000100000000000000110011000000010001
111000000000000000000000000111101000001100110000000000
100000000000000000000000000000000000110011000000000000
000000000000000000000110011001001011010110000000000000
000010000000000000000010010101111110000000000000000000
000000000000000101100010100101000000010110100110000001
000001000000000000000000000000100000010110100001000101
000000000110000001100011100000000001011001100000000000
000000000000000000100000000001001011100110010000000000
000001000000000001100000010111001110000100010000000000
000010000000000000100010001011101100010001000000000000
000000000000001111000110000000000001011001100110000101
000000001010001011000100001101001101100110010010000010
010000000000000101000000001111001110101000000000000000
000000000000000000000000000011100000000010100000000000
.logic_tile 7 2
100000000000000000000000000101011010100100000000000000
000000000000000000000011010000101011100100000000000000
001000001010000000000000001000000001011001100000000000
100000001110000000000000000111001100100110010000000100
010000000000000000000110010000001110010101010000000000
010000000000000000000110010111010000101010100000000000
000000000000000000000110011000011100010101010000000000
000000000000001001000110010011010000101010100000100000
000000000000000000000000000000001010001100110000000100
000000000000000000000000000000011011001100110000000000
000001000000000001100000010000011100000100000110000000
000010000000001001100010010000010000000000000000000001
000000000000000001100000010011100000000000000100000100
000000000000000000100010010000000000000001000000000000
010000000000011000000000001011111010111100000000000000
000000000000001001000000001101010000000011110000000000
.logic_tile 8 2
000000000000001001100010110111101000001100111000000000
000000000000000001000010000000100000110011000010010000
101000000000010101000000000001001000001100110010000000
000000000000100000000000000000100000110011000010000000
010000000000000000000010000001000000000000000100000000
110000000000000000000100000000000000000001000000000000
000000000000000000000010100000000000000000100100000000
000000000000000000000000000000001110000000000000000000
000000000000000000000000000000011000000100000100000000
000000000000000000000000000000000000000000000000000000
000010100000000000000000000000000000000000000100000000
000001000000000000000000001001000000000010000000000000
000000000000001000000000000000000000000000000100000000
000000000000001001000000000001000000000010000000000000
010010000000000000000000010101100000000000000100000000
000001000000000000000010000000100000000001000000000000
.logic_tile 9 2
000000000000000000000010100000000001000000001000000000
000000000000000000000010100000001011000000000000001000
000010000000000101100110100001011010001100111000000000
000001000000000000000010110000110000110011000000000000
000000000000000000000000000001101000001100111000000000
000000000000000000000000000000000000110011000000000000
000000000000001000000010110001101000001100111000000000
000000000000000101000010100000100000110011000000000000
000000000000000000000000000101101000001100111000000000
000000000000000000000000000000000000110011000000000000
000000000000000000000000000000001000001100111000000000
000000000000000000000000000000001001110011000000000000
000000000000000000000000000001101000001100111000000000
000000000000000000000000000000100000110011000000000000
000000000000000000000000000000001001001100111000000100
000000000000000000000000000000001011110011000000000100
.ramt_tile 10 2
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000100000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000001000000000000000000000000000000000000
000010100000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 11 2
100000000000000001100111100001001000111000000000000000
000000000000000101000111100000011101111000000000000000
001000000000000000000000000011001000000000000100000000
001000000000000000000000001001110000101000000000000000
000000000000000000000000001001000000100000010100000000
000000000000000000000000000111101001000000000000000000
000001000000101000000000000001011111001001000000000000
000000100001010001000000001001101010000001000000000000
000000000000000000000000010001001000000001010100000000
000000000000000111000010001001010000000000000000000000
000000000000000000000000000111000000110110110100000000
000000000000000000000000000000101110110110110000000000
000000000000001000000110000101100001010110100000000000
000000000000000001000000000011001110101111010000000010
000000000000000001100000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 12 2
100000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
101000100000000000000000000000000000000000000000000000
001001000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000011100000000000000000000000000000000000
000000000000000000100000000000000000000000000000000000
000000000000001000000000000000000000000000000000000000
000000000000001001000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010001000000000000000000001000000000010110100100000000
110000000000000000000011111111000000101001010000000000
.io_tile 13 2
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000100000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 0 3
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 3
000000000000000001100000000101100000100000010100000000
000000000000000000000000000000001011100000010000000000
001000000000000000000000000000001010110000000100000000
100000000000000000000000000000011110110000000000000000
010000000000000000000111100000000000000000000000000000
100000000000000000000000000000000000000000000000000000
000000000000000001100000000011000000111001110000000001
000000000000001101000000001111101000100000010000000000
000000000000000000000000010111011101111000100010000000
000000000000000000000010100000101010111000100000000000
000000000000000101100000000101000000100000010100000000
000000000000000000000000000000101000100000010000000000
000000000000101000000000000111001111110001010000000000
000000000000000001000010000000011110110001010010000000
110000000000000001000000000000000000000000000000000000
000000000000000000100000000000000000000000000000000000
.logic_tile 2 3
000000000000100000000010101001100000101001010100000000
000000000000000000000011110101000000000000000000000000
001000000000000101000000000111111010101000000100100000
100000000000000000000000000000000000101000000000000100
010000100000000000000000000000011101110000000100000000
010001000000010000000000000000001010110000000000000000
000000000000000111000000000000011010110000000100000000
000000000000000000110000000000001001110000000010000000
000000000000000000000000011000000001100000010100000000
000000000000000000000010000011001010010000100000000000
000000000000000111000000000011011010101000000100000000
000000000000001001000000000000100000101000000000000000
000000000000000000000110001000011110101000000100000000
000000000000000000000000000101000000010100000000000000
110000000000001001100000000101101110101000000100000000
100000000110000001000000000000010000101000000000000011
.ramb_tile 3 3
010000101110100000000000000000000001000000
001000000001000000000000001101001001000000
001000000000000000000000000111000001000000
100001000000000000000011111011001111000000
110000000001010000000111001000000000000000
111000000000000000000100000111000000000000
000000000000000111000000001000000000000000
001000000000000111000000000101000000000000
000000100000000001000011110000000000000000
001011000000000000000111011011000000000000
000000000000000011100000001111100000000000
001000000000000001100000000011100000000000
000000000010010001100011101000000000000000
001001000100000000100000000011000000000000
010000000000000111100110100000000000000000
111000000000000000000010000011000000000000
.logic_tile 4 3
100000100000000000000010110000000000000000000000000000
000001001100000000000010010000000000000000000000000000
001001000000000000000000010000000000000000000000000000
100010100000000000000011100000000000000000000000000000
010000000001000111100110000000000000000000000000000000
110000000110100000100100000000000000000000000000000000
000000000000001111100000010001000000000000000100000001
000000000000000111000011110000100000000001000000000000
000010000000100000000000000000000000000000100100000000
000010000001010000000010000000001010000000000000100000
000000000000000000000110100011101101011010010000000000
000000000000000001000011110000011101011010010000000000
000010100000000000000000001001011111000100000000000000
000000001010000000000000000101111001101000010000000000
010000000000000000000000011011100001101001010000000000
000000001100000000000011000101101011100110010000000000
.logic_tile 5 3
100001001100001111100110000011011110010100000000000000
000000100000000001000111101001110000000001010000000000
001000000000000101100110011001001100000100100000000000
100000000000000000000110011001011110000000000010000000
000000000000000000000110001111001001000000100000000000
000000100000000101000110101001111111101000010010000000
000001000000000001100010011101111011110000000000000000
000010100000000000000011001011101100000000000000000000
000000000000000001000010011001011110101000010000000000
000000000000000000000010111001001011000100000000000000
000000000000000101000010101111101111001000010000000000
000000000000000000000000000001001011010010000000000000
000000000000100001000000010101001010101000000000000000
000000000001000101100011100111010000000001010000000000
000000000000011111000010000000000000000000000100000000
000000000000001001000010010011000000000010000010000000
.logic_tile 6 3
100000000000000101000000001011011010100000000000000000
000000000000000000000010101101111011000000000000000000
001000000000001001100110011000001010010101010000000000
100000000000000001000010101011000000101010100000000000
000000000000000001100110111001000001101001010000000000
000000000000000101100011010111001100000110000000000000
000000000000000101000111111111001101000011100100000000
000000000000000101000010001001101000000011110000000000
000000000000001000000010100001001010010101010000000000
000000000000000001000000000000000000010101010000000000
000000000000000001000010001111011000000100000000000000
000000000000000001100100000101011111010000000000000000
000010100000000001100110111101011110000000100000000000
000000000000010000000011010101101001100000000000000000
010000000000000001100000011001100001100000010000000000
000000000000001001100010011111001100000110000000000000
.logic_tile 7 3
100000000000001001000000010101011101100010000000000000
000000000000011011100010101101111101000100010000000000
001001000000000000000000001111011100001100110000000000
100000000000000101000000000101001100000100100000000000
110000000000001001100010100101000000000000000100000000
110000000000000001000010100000100000000001000000000000
000000000010001000000111100101001000101000000000000000
000010000000001011000100000101010000000000000000000000
000000100010000001000110000111100000000000000100000000
000010000000001111100100000000000000000001000000000000
000000001100000000000011110000001110000100000100000000
000000000000000111000011100000000000000000000000000000
000000001010000001100111100001001111111111000000000000
000000000000000000100010100001011000010110000000000000
010001000000101000000000011101101100101000010000000000
000010100000011001000010011111101101000100000000000000
.logic_tile 8 3
100000000000000011100110010101101000001100000000000000
000000000000001101100011110001111111110000000000000000
111000000000001001100110011011111000000000000000000000
100000000000001001100010100011011011100000000000000000
010000000000000001000010010001011100000010100000000000
010000000000000101000010000011011101000000010000000000
000000000000001000000110111001100001001111000000000000
000000000000001011000010010001001110110000110000000000
000001000000001101000000010101011001000011000000000000
000000000000001001100011010001011111000000110000000000
000000000000001101100110000101100001111001110100000000
000000000000000001000100000000101010111001110000000010
000001000000100111100010000011000000101001010100000000
000010000000011001100000000111000000111111110010000000
000000001010001000000010000101001010111100000000000000
000000000000000011000000000111010000000011110000000000
.logic_tile 9 3
000000000000000101000000010111001000001100110000000000
000000000000000000000011110000100000110011000000010000
101000000000000101000111000011000000001111000000000000
000000000000001101000010101101101000110000110000000000
010000000000000011100010100111111010000000110000000000
010000000000000000000010101101101110110000000000000000
000000000000000000000000011001111101001100000000000000
000000000000000101000011110001101001110000000000000000
000000000000001001100000000101011010011010010000000000
000000001110001001100010110000111011011010010000000000
000000000000001000000000000011011100100101100000000000
000000000000000001000010000000011100100101100000000000
000000000000000001100000010000000000000000100100000000
000000000001010000000010010000001010000000000000100000
010001000000000000000011100111111000111110100000000001
000010100000000000000110110000100000111110100010100110
.ramb_tile 10 3
010000000000000000000000000000000000000000
001000000000001001000000000001001110000000
001000000000001000000000001111100001000010
100000000000001011000000001101101101000000
110000000000000000000000001000000000000000
011000000000000000000000001011000000000000
000000000000000000000000010000000000000000
001000000000000000000011111111000000000000
000000000100001111100000000000000000000000
001000000000001011000011100011000000000000
000000000000000000000111101111100000000000
001000000000000000000011110111000000010000
000000000000010001000111100000000000000000
001000000000100000000110001111000000000000
010000001110000011100111100000000000000000
011000000000000011100100000011000000000000
.logic_tile 11 3
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
101000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000001000000100100000001
000000000000000000000000000000001011000000000000000000
000000000000000000000110000000000000000000000000000000
000000000000000000010100000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000001100000000000000000000000000000000000000000000
000000000000100000000000000000000000000000000000000000
000000000001010000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 12 3
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000110000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000001010010000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000001010000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.io_tile 13 3
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000101110001000000
000000001000000000
000000000000000000
000000000000000000
000000000000010010
000000000000110000
000000000000000000
000000000000000001
000000000000000010
000000000000000000
.io_tile 0 4
000000000100000000
000000000100000000
000000000100000000
000000000100000000
000000000100000000
000000000100000000
000100000100000000
000000000100000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 4
010000000000000000000000000011011010101000000100000000
001000000000000000000000000000010000101000000000000000
001000000000000101000000000011100000100000010100000001
100000000000000000100000000000101100100000010000000000
010000000000000001100000001000011011110100010000000000
101000000000000000000000001101011100111000100010000000
000000000000000101000010000000000000000000000000000000
001000000000000000000010110000000000000000000000000000
000100000000000101100000000000001100101000000100000000
001000000000000000100000000101000000010100000000000000
000000000000001000000000010101100000100000010100000000
001000000000001011000010000000001100100000010000000000
000100000000001000000000000111001100101000000100000000
001000000000000001000000000000000000101000000000000000
110000000000000000000000000000000001100000010100000000
001000000000000000000000000011001000010000100000100000
.logic_tile 2 4
010000000000000000000000010000000000100000010100000000
001000000110000101000010111001001011010000100000000000
001000000001010000000110100000001110110001010000000001
100000000000100101000000000111001011110010100000000000
010000000100001000000111000101101110101000000000000000
101000000000000101000111100111010000111101010000000010
000000000000001000000000000111101110101000110000000000
001000000000000101000000000000001010101000110010000000
000000000000000000000000000000000000100000010100000100
001000000000000000000010001011001001010000100010000000
000000000000000000000110000001101111101000110000000000
001000000000000000000000000000001001101000110000000001
000000001100001001000000010000011100101100010000000000
001000000000000001000011000001011110011100100000000010
110000000000000111000000000001000000100000010100000000
001000000000000000000000000000101110100000010000000100
.ramt_tile 3 4
000000010000001001000000000000000001000000
000000000000001111100000000001001100000000
101000010000000000000000001101100000000000
000000000000000000000000001101101110000000
110000000000000000000000001000000000000000
110000000000001111000000001111000000000000
000000000000000111000111110000000000000000
000000000000000000100111110001000000000000
000000000000000000000000000000000000000000
000000000000101001000011100011000000000000
000000000000000000000000000111100000000000
000000000000000111000000000101000000000000
000000100000000000000011100000000000000000
000001000000001001000100001011000000000000
010000000000000011100011101000000000000000
110000000110001001100000000111000000000000
.logic_tile 4 4
110001000000000101100000010000001100000100000100000000
001000000100000000000011010000000000000000000000000000
111000000000000101100111100000000000000000100100000000
100000000000000000000100000000001000000000000000000001
110100000000000000000000000000011000000100000100000000
001000000000000000000000000000000000000000000010000000
000000000000000001000111100101100000000000000100000000
001000000000000000100000000000100000000001000000000000
000000000011000001100000000000000001000000100100000000
001000001010000000100000000000001110000000000000000000
000000000000001001100011100000000001000000100100000000
001000000000000001000000000000001101000000000000000000
000000000001010000000000000111111001000001010000000000
001001000000000000000000001001111010000001100000000000
010000000000000101000000001011111011001001000000000000
001000000000000000100010000011001001000101000000000000
.logic_tile 5 4
110000000000000000000000001000000000111001110100000100
001000000000010000000011100111001010110110110000000000
111000000000001000000110111000000001111001110100000000
100000000000000001000010101111001010110110110000000010
010000000000000011100110100000011001111100110110000000
011000000000001111100000000000011000111100110000000000
000001000000000000000011100011100001001001000100000000
001000100000000101000010110000101110001001000000000000
000011000110000000000000001111101011101001000000000000
001010100000000000000000001101001101100000000000000000
000000000000000000000010101001100000101001010100000000
001000000000000000000110001101100000111111110000000001
000000000000000000000000001011111110000000010000000000
001000000000000000000000001011101011000001110010000000
000000000000000101000000010000000000000000000000000000
001000000000000001100010010000000000000000000000000000
.logic_tile 6 4
110010000000000000000000000111111000101010100000000000
001000000001010000000000000000010000101010100000000000
001000000000001001100010100000000000000000000000000000
100000000000000001100100000000000000000000000000000000
110000000000000001000000000000011010000100000100000000
111000000000000000000000000000000000000000000010000000
000000000000100101000000000000000000000000000000000000
001000000001010101100010110000000000000000000000000000
000000000000000001000000000011000000000000000100000000
001000000100000000000010000000000000000001000000100000
000000000000000000000000001101011001011010010000000000
001000000000000000000000000001001011010110100000000000
000000000000000000000111000000000000000000100100000000
001000001110000000000000000000001101000000000010000000
010000000000100000000000000101111000010101010000000000
001000000001010001000000000000000000010101010000000000
.logic_tile 7 4
010000000000100000000000010111111100110011000000000000
001000000000000000000011111101111100000000000000000000
101001000000100011100111001111011111110000010000000000
000010100000010000000100001001011000100000000000000000
010000000100000000000111000011001100010101010100000000
011010000000010000000000000000010000010101010000000000
000000000000100001000010001111000000001111000000000000
001000000000010111000000000101101111110000110000000000
000001000000000001000010000000000000000000000000000000
001000000000000001000000000000000000000000000000000000
000000000001110000000110100101111010010101010100000000
001000000001010000000000000000100000010101010000000000
000000000000000111100010010000000000000000000000000000
001000000000000000100011010000000000000000000000000000
010000000010000000000010100000000000000000000000000000
001000000000000000000011110000000000000000000000000000
.logic_tile 8 4
010000000000000000000000000000000000000000000100000000
001000001100000000000000001101000000000010000000000000
101000000000001000000111000000011110000100000100000000
000000000000000001000100000000000000000000000000000100
000001000000000000000110000000011000000100000100100000
001010000000000000000000000000010000000000000000000000
000001000000000000000000000000000001000000100100000000
001000100000000000000000000000001110000000000000000000
000000000000000000000000001000000000000000000100000000
001000000000000000000000000011000000000010000000000000
000000000001011001100000000000000000000000000100000000
001000000000100111000000001111000000000010000000000000
000000000110000000000000010000000001000000100100000001
001000000000000000000010010000001000000000000000000000
000010000000001001100000000000000001000000100100000000
001001000000001001100000000000001100000000000000000000
.logic_tile 9 4
010010100000000001100110010011011101001100110000000000
001000000000000101000010000001101111001000010000000000
101001000000000111100110101000000000000000000100000000
000000100000000000100011110001000000000010000000000000
000000000000100000000010100011111111101000010110000000
001000000000010001000010100111111110111000100000000000
000000000000000001100000000011100001001001000000000000
001000000000000000000011100101001001100000010000000000
000000001000001000000111000001011000010100000000000000
001000000000001001000100001001000000000000000000000000
000000000000001011100110001001011000110100100000000000
001000000000000001100000001101011101010010110000000000
000000000000001001100000001001001110000000000000000000
001010000000000001100000000101101100100000000000000000
010000000000000101000010010000001010101000000000000000
001000000000000000100010001101010000010100000000000000
.ramt_tile 10 4
000000010000000000000000011000000000000000
000000000100000000000011111011001100000000
101000010000001000000000001001000000000001
000000000000001111000000000011101010000000
010000001000101000000011101000000000000000
110001000000011111000000000011000000000000
000000000000000111000000000000000000000000
000000000000000011100000001111000000000000
000000000100001000000111100000000000000000
000000000000001111000100001111000000000000
000000000011000011100000010101100000000010
000000000000100001100011101011000000000000
000000000000000000000011111000000000000000
000000000000000000000111101111000000000000
010000000000000000000011101000000000000000
010000000000000000000000000101000000000000
.logic_tile 11 4
010000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
101000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000111100000000000000000000000000100000000
001000001100000000100000000101000000000010000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000010000000000000000000000000000
001000000000000000000010000000000000000000000000000000
000000000000000000000000000000000000000000100110000000
001000000000010000000000000000001111000000000010000000
.logic_tile 12 4
010000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000010000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000100000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
.io_tile 13 4
000000000100000000
000000000100000000
000000000100000000
000000000100010001
000000000100000000
000000000100000000
001100000100000000
000000000100000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 0 5
000000000100000010
000100000100000000
000000000100000000
000001110100000001
000000000100100010
000000000100110000
001100000100000000
000000000100000000
000000000000000000
000100000000000000
000001011000110110
000000000000011000
000010000000000000
000001010000000001
000000000000000010
000000000000000000
.logic_tile 1 5
010000000000001000000000010111100000101001010100000000
001000000000000001000010000111100000000000000000000000
001000000000000000000000001000011100101000000100000000
100000000000000000000000001111000000010100000000000000
010000000000000001100000000111100000100000010100000000
101000000000000000000000000000101010100000010000000000
000000000000000101000000001101100000101001010100000000
001000000000000000000000001111000000000000000000000000
000000000000001111000000000111111100101000000100000000
001000000000000011100000000000100000101000000000000000
000000000000001011100000000001000001100000010100000000
001000000000000001100000000000001111100000010000000000
000000000000000111000000000111100000100000010100000000
001000000000000000000000000000101001100000010000000000
110000000000000000000000000011011100101100010000000000
001000000000000000000011010000001100101100010000100000
.logic_tile 2 5
110000000100000000000000000011000000000000000110000000
001000000000001101000000000000000000000001000000000000
111000000000000101100010100000000000000000000000000000
100000000000000000000100000000000000000000000000000000
110000100000001000000010110000000000000000000000000000
001001000000010101010111010000000000000000000000000000
000000000000000000000000011001000001111001110000000000
001000000000000001000011000101001000100000010000000001
000000000000000101000000000101011100101100010000000000
001000000000000000000000000000101110101100010010000000
000000000000000001100000011000011101110100010000000000
001000000000000000100010010101011001111000100010000000
000000000000000011000000000101011011110001010000000000
001000000000010000000000000000001110110001010000000000
010000000000000101000000001101000001101001010000000000
001000000000000000100000001101101010100110010000000010
.ramb_tile 3 5
010001000101000001000010000000000000000000
001010100000110000000111111111001001000000
001000000110000000000000010101100000000000
100000000000000111000010101001001100000000
010000000001011000000011101000000000000000
111001001000001111000000001111000000000000
000000000000000111000111000000000000000000
001000000000000000000000001011000000000000
000001000000000111000011101000000000000000
001010100100000000100000001101000000000000
000000001000000000000000000001100000000000
001000000000001001000000000101100000000000
000000000000100000000111001000000000000000
001000001010000000000100000011000000000000
010000000000000000000010100000000000000000
011000000000000000000000000001000000000000
.logic_tile 4 5
110000000000000111000000010000001100000100000100000000
001000000000000101000011100000010000000000000000000000
111000000000001000000000000000000000000000000000000000
100000000000000111000000000000000000000000000000000000
110000000000000101100000000000000000000000100100000000
001000000000000000000000000000001001000000000000000000
000000000000000000000000001000000000000000000100100000
001000000000000000000000000011000000000010000000000000
000000000000000000000111010001001110101000010000000000
001000000000000000000010000001001101000000010000000000
000000000000000101000000000111011000001000000000000000
001000000000000000100000000111001000001101000000000000
000000000000000111000000000000000000000000000000000000
001010000000000001100000000000000000000000000000000000
010000000000000000000000000101000000000000000100000000
001000000000000000000000000000000000000001000000000000
.logic_tile 5 5
010000000100000000000010100001000000000000000100000000
001010000000000000000000000000100000000001000000000000
101000001110000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000010000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000110011101101100000000000000000001
001000000000000000000011000011100000010100000001000101
000000000000001001000000000000000000000000000000000000
001000001010010001000000000000000000000000000000000000
000000000000000001000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000001010000000000001011011010101000010000000000
001000000000110000000000000111011011001000000000000000
010000000000000001000000000000001100000100000100000000
001000000000000000000000000000000000000000000000000000
.logic_tile 6 5
110000000000100000000000010000000000000000100100000000
001000000000010000000010010000001001000000000000000000
001000000000001000000000000011000000000000000100000000
100000000000000001000000000000100000000001000000000000
000000000000000000000000000000000000000000100100100000
001000000000000000000000000000001100000000000000000000
000000000000000001100000000000011110000100000100100000
001000000000000000100000000000010000000000000000100000
000001000000000001100000011000000000000000000100000000
001010000001000001000010100101000000000010000000000000
000000000000000000000000001000000000000000000100000000
001000000000000000000000001111000000000010000000100000
000000001000000000000000000000001100000100000100000000
001000000000000000000000000000000000000000000000000010
000000000000000000000010100000011000000100000100000000
001000000000000000000010100000000000000000000000000010
.logic_tile 7 5
010000000100000000000111010000000001000000100100000000
001000100001000000000011110000001100000000000000000000
101000000000001011100000000000000000010110100100000000
000000000000001011000011100101000000101001010000000000
010000000000001000000000000000000001011001100100000000
011000000000000011000000001111001000100110010000000000
000001001000000000000000000000000001000000100100000000
001010100000000000000000000000001000000000000000000000
000000000000000000000000001000000000000000000100000000
001000100000000000000000001001000000000010000000000000
000000001100001000000000000000000000000000000000000000
001000000000001101000000000000000000000000000000000000
000000000000000000000010000000000000000000000000000000
001000001011000000000000000000000000000000000000000000
010000001000000000000000000000001110010101010100000000
001000000000000000000000001001010000101010100000000000
.logic_tile 8 5
010000000000001000000110000011011010111100010000000000
001000000000001011000010011111001101111101000000000001
001000000000000000000111010000000000000000000000000000
001000000000000111000110000000000000000000000000000000
010000000000000000000111010000000001000000100100000000
011000000000000000000010010000001001000000000000000000
000000000001010101000000000000011011100001010000000000
001000000000000111100010111101001001010010100000000000
000000000000001101100000011101111000001001100000000000
001000000000001001000010100101111011010001100000000000
000000000000001101000000000011011100101000000000000000
001000000000000001000000001001000000000000000000000000
000000000000000000000110100000001100100000000000000000
001000100000000000000000001111001101010000000000000000
010000001000000000000000000000000001000000100000000000
011000000000000000000000000000001100000000000000000000
.logic_tile 9 5
010000000000000000000000000000000000000000001000000000
001000000000000000000010100000001011000000000000001000
001000000000000000000000000111001010001100111100000000
101000000000000000000000000000010000110011000000000000
000000001010000111100110010101001000001100110100000000
001000000000000000100010000000100000110011000000000000
000000000000000011100000000000001010000011110100000000
001000000000000000100000000000010000000011110000000000
000000001010000000000011100000000000000000000000000000
001000000001010000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000001100000000000000000000000000000000000
001010100000000001000000000000000000000000000000000000
010000000000000000000000000000001000100011010000000001
111000000000000000000000000111011101010011100000000000
.ramb_tile 10 5
010000000000000111100000001000000001000000
001000000000001001100011101011001111000000
001000000000000111100000001111100001100000
100000000010000000100000000101001000000000
010000000000100000000000010000000000000000
011000000000010000000011110001000000000000
000000000000001111000000000000000000000000
001000000000001111100000000001000000000000
000010000001010000000000001000000000000000
001001000000100000000000000101000000000000
000000000100001000000000010111000000001000
001000000000001011000011110111100000000000
000000000000000111100111100000000000000000
001000000000000011000100000111000000000000
110000000000000111100111100000000000000000
011000001000000000000000001101000000000000
.logic_tile 11 5
010000000000000000000000000011100000010110100000100000
001000001100000000000000000000000000010110100000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000010000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000101110000000000000000000000000000000000000000000
001001000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000001000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000010100000010000000000000000000000000000000000000000
001000000000100000000000000000000000000000000000000000
000000001100000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
.logic_tile 12 5
010000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000100000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
.io_tile 13 5
000000000100000000
000000000100000000
000000000100000000
000000000100000000
000000000100000000
000000000100000000
000000000100000000
000000000100000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 0 6
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 6
000000000000000000000110001000011111110100010000000000
000000000000000000000011100101001011111000100001000000
001000000000000000000000000101011011110001010000000000
100000000000000000000000000000001101110001010000000001
010001000000000101000000000000011101110000000100000001
010000100000001101000010100000001101110000000000000000
000000000000000001000010101000000001100000010100000000
000000000000000000000100001011001100010000100000000000
000000000000000000000000001101001000101000000000000001
000000000000000000000000000101110000111101010000000000
000000000000000001000110010101100001100000010100000000
000000000000000000010010000000101100100000010000000000
000000000000000000000000000001011100101000000100000000
000000000000000000000000000000100000101000000000100000
110000000000001000000000001000000000100000010100000000
100000000000000011000000000011001010010000100000000000
.logic_tile 2 6
000000000000000000000110000000011001110000000100000000
000000000000000000000011100000001010110000000000000010
001000000000000011100110001000000000100000010100100000
100000000000000000100000000001001001010000100000000000
010000000000000001100000010001100000100000010100000000
010000000000000000000010100000001101100000010000000000
000000000000000101100011111000000001100000010100000000
000000000000000000000010000001001001010000100000000000
000001000000000000000000000000011000101000000100000000
000000000000000000000010000101000000010100000000100000
000000000000000000000000001000001111110100010000000000
000000000000000000000000001111011011111000100010000000
000000000000000000000110001001100000101001010100000000
000000000000000000000100001101000000000000000000000000
110000000000000000000000011000000000100000010100000000
100000000000000000000010110001001011010000100000000000
.ramt_tile 3 6
000010110000000000000000000000000000000000
000000000000000000000011111001001110000000
101000010000000111000000001101000000000000
000000000000001111000011111111101110000000
110000000000000000000111101000000000000000
010000001000000000000100001101000000000000
000000000000000000000011101000000000000000
000000000000000000000000000011000000000000
000000100000110000000000011000000000000000
000001000001110000000010100011000000000000
000000000000001101100000001111000000000000
000000000000000101000000000001100000000000
000001100000001001000011101000000000000000
000000000000000101000100001001000000000000
010000000001010000000000001000000000000000
010000000000100001000010000111000000000000
.logic_tile 4 6
000000000000001000000010100000000000001111000110100000
000000000000000001000100000000001000001111000010100001
101000000000001000000000000000000000000000000000000000
000000000000000011000000000000000000000000000000000000
110000000000000000000110000000000000000000100000000000
010000000000000101000100000000001011000000000000000000
000010100000001001000000000001111011000000100000000000
000001001110001111000000000101001010010100100000000000
000000000000000000000000010111100000000000000100000010
000000000000000000000010100000100000000001000010100110
000000000000010000000000000111100000000000000100000010
000000000000100000000000000000000000000001000010100100
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000000000000101000000000000000000000000100000000000
000000000000000000000010100000001001000000000000000000
.logic_tile 5 6
100000000000000000000110101001111011001101000000000000
000000000000000000000000000001001011000100000000000000
111000100000001011100000000000011100111101010100000100
100001001100001011000000000111010000111110100000000000
110000000000000000000111010011000000111111110010000010
110000000000000000000110111011100000010110100000000001
000000000000000000000111000000000001111001110100000000
000000000000001001000000001001001110110110110000000010
000000000000000000000111100000000000000000000000000000
000000000000000000000010000000000000000000000000000000
000000000000000000000000010000000000000000000000000000
000000000000000000000010000000000000000000000000000000
000000000000001000000111101101011000100001010000000000
000000000000000001000000001101101011010000000000000000
000000000000001000000000000000000000000000000000000000
000000000000001001000000000000000000000000000000000000
.logic_tile 6 6
100010000000000000000000000000000000000000000000000000
000000000000000101000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
100000001010000000000000000000000000000000000000000000
000000001110001000000000000000000000000000100100100000
000000000000011001000000000000001000000000000000000000
000100000000000000000000000000000000000000000000000000
000100000000000000000000000000000000000000000000000000
000000000001001000000000000000000000000000000100000000
000000000000000101000000000011000000000010000000000010
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000001000000000000000000101000000000000000100000000
000000000000000000000000000000000000000001000000100000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 7 6
100000000010000000000010100000000000000000000100000000
000010000000000000000000000101000000000010000000000000
001000000000100000000010100000000000000000000000000000
100000000001000101000000000000000000000000000000000000
000000000000000101000000011000000000000000000100000000
000000000000000000000010000001000000000010000000000000
000000001110000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000010000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000001000000000000000000000000000000000000000100000000
000000100000000000000000001101000000000010000000100000
000000000000100000000000000000011000000100000100000000
000000000000010000000000000000010000000000000000000000
000000000000100000000000000000000000000000100100000000
000000000001010000000000000000001001000000000000000000
.logic_tile 8 6
000000000000001000000000000011100000000000000100000000
000000100000000001000010100000100000000001000000000000
101000000000000000000000000000000000000000000000000000
000000000000001111000000000000000000000000000000000000
000000001110000011100000000000011100001100000000000000
000000000001000000100010110000011000001100000001000001
000000000000100000000000000000000000000000000000000000
000000000001010000000010100000000000000000000000000000
000000000000000000000000000101100000000000000000000000
000000000000000000000000000101100000101001010000000000
000000000000000000000110000000011000000100000100000000
000000000000000000000000000000000000000000000000000010
000000001000100000000000000101000000000000000100000000
000000000000010000000000000000100000000001000000000010
000000000000000000000000000000001000000100000100000000
000000000000000000000000000000010000000000000000000000
.logic_tile 9 6
100000000000000001000000000000001100000100000100000001
000000000000000000100000000000000000000000000000000000
111000000000000000000000000111000000000000000101000000
100000000000000000000000000000000000000001000000000000
110000000000000000000000000000000000000000000000000000
000000000000000000000010010000000000000000000000000000
000000000000000000000000000000000000000000000100000000
000000000000000000000000001101000000000010000001000000
000000000000000101000000001000000000000000000100000000
000000000000000000000000000111000000000010000000000100
000000000000000101100000001000000000000000000100000000
000000000000000000000000000011000000000010000000000000
000000000000000101100000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000000000000101000000000000000000000000100100000000
000000000000000000000000000000001000000000000000100000
.ramt_tile 10 6
000000010000000000000011110000000001000000
000000000000000000000011011011001100000000
101000010000000000000000000111100000000000
000000000000000000000000001001101110000000
010000000000010000000000001000000000000000
010000000000100000000000000101000000000000
000000000000000111000011110000000000000000
000000000000000000000011011111000000000000
000000000000000000000000010000000000000000
000000001010000000000011111111000000000000
000000000000001111100000011011100000000000
000000000000000111000011111101100000000000
000000000000000000000111111000000000000000
000000001110001111000011101101000000000000
110000000000000111000011101000000000000000
110000001000000000100000000011000000000000
.logic_tile 11 6
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 12 6
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.io_tile 13 6
000000000000000000
000100000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
001000000000000000
000000000000000000
000000000000000000
000100000000000001
000000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 0 7
000000000000001000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000010000
000000000000000000
000000000000000000
.logic_tile 1 7
000000000000000000000000000111111010101000000100100000
000000000000000000000000000000100000101000000000000000
001000000000001000000000001000000000100000010100000000
100000000000000111000000001111001110010000100000000000
110000000000000001100000000000000000000000000000000000
010000000000001101000000000000000000000000000000000000
000010000000001000000000010000011000000011110000000000
000001000000000001000010000000000000000011110010000001
000000000000000000000000000111111010101000000100000000
000000001000000000000010010000110000101000000000000000
000000000000000000000000001011100000111001110000000000
000000100000001111000000000101001010010000100000000001
000000000000000000000000000111100001100000010100000000
000000000000001001000000000000101111100000010000000000
110000000000000000000111010101000001100000010100000000
100000000000000000000111100000001111100000010000000000
.logic_tile 2 7
100000100000000000000000000000000000000000000000000000
000001000000000000000000000000000000000000000000000000
111000000000000000000000000011001010101001010010100000
100000000000000000000000000111100000101000000010100110
110000000000000111100011101000000000000000000100000000
000000000000000000000110100111000000000010000000000010
000001000000000011100000000101111111111001000000000000
000010100000000001000000000000011010111001000010000000
000000000000000101000000000011100000000000000100000001
000000000010000000000010010000000000000001000000000000
000000000000000101100000000101000000000000000110000000
000000000000000000000000000000100000000001000000000000
000001000000101101000000000011000000000000000100000000
000000000000001011100000000000000000000001000010000000
010000000000000101000010001000001110110100010001000000
000000000000000000000000000101001011111000100000000000
.ramb_tile 3 7
000000000001010001000000010000000000000000
000010000100000000100011001111001110000000
001000000001010000000000011101100001000000
100000000000100000000011000111101101000001
010000000000000000000111100000000000000000
010000001000001111000000001101000000000000
000000001000000000000111000000000000000000
000000000000000000000100000101000000000000
000001000000000111000000001000000000000000
000000001000100000000000001111000000000000
000000000000000000000110110001100000000000
000000000000000000000010100011100000000000
000000000001010011100111001000000000000000
000001000010000000100100001011000000000000
110010000001011001000111000000000000000000
110001000000100101000000000001000000000000
.logic_tile 4 7
000000000000010000000111101000001001100100000000100000
000000001010100000000000001001011011011000000000000000
001010000001010101000110000000000000000000000000000000
100000000000100101000010110000000000000000000000000000
110000000000000000000010100101011001000001100000000000
110000001000000000000111100000101000000001100000000000
000000000000000000000010100000000001000000100110100000
000000000000001101000100000000001010000000000011000000
000000000000001000000000000000000000000000100101000101
000000000010000011000000000000001011000000000000100010
000010100001010000000000000000000000000000000000000000
000001000000100000000000000000000000000000000000000000
000010100100110000000111100000000000000000100101000000
000000000000100000000000000000001100000000000010100100
010000100000100000000000001000000000010110100100000001
000001000000010000000000001001000000101001010010100100
.logic_tile 5 7
000000000000000000000000000000000000000000001000000000
000000001100000000000000000000001100000000000000001000
000000000000000000000000000011101100001100111000000000
000000001110000000000000000000100000110011000000000100
000000000000000000000000000000001000001100111000000000
000000000000000000000000000000001111110011000000000000
000000000000000000000000000000001000001100111000000000
000000000000000000000000000000001110110011000000000000
000000000000001101100000000000001001001100111000000000
000000000000001001000000000000001100110011000000000000
000000000000001000000000010111101000001100111000000100
000000000000000101000010100000000000110011000000000000
000000000000101000000110100111101000001100111000000100
000000000001000101000000000000000000110011000000000000
000000000000001001100000000000001000001100111000000000
000000000000001001100000000000001100110011000000000000
.logic_tile 6 7
000000000000000000000000000000000000000000100100000000
000000000000000000000000000000001011000000000011100101
101000000000001000000000000000011010000100000110000001
000000000000000101000000000000010000000000000010000110
110000000000000101100110110000000000000000000000000000
010000000000000000000010100000000000000000000000000000
000100000000000000000110100000000000000000000100000001
000110100000000000000000001101000000000010000010100111
000000000000000000000000010000000001000000100110000001
000000000000000000000010010000001000000000000011000000
000000000000000000000000000000000000000000000110000000
000000000000000000000000000111000000000010000011000101
000001000000000000000000000000000000000000100110000100
000010000000001101000000000000001010000000000001100011
010000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 7 7
100000000001010000000000000000000000000000000000000000
000000101100000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
110000000000000000000000000000000001001111000100000000
110000100000000000000000000000001010001111000000000000
000000001010000001000000000000000000000000000000000000
000000000000000000100000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000100000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000010000000000000000000000000000000000000000
000010100000000000000111100000000000000000000000000000
000001000001000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 8 7
000000000000000000000000000000000000000000000000000000
000000000001010000000000000000000000000000000000000000
101000000000000000000000000000000000000000000000000000
000000000000000101000000000000000000000000000000000000
000000000000000000000000010000001010000100000100000000
000000000000000000000010100000010000000000000000000000
000000000000000000000000000000011000000100000000000000
000000000000000000000000000000000000000000000000000000
000010000000000000000000000000000000000000000000000000
000001000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000001000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 9 7
000000000000000000000000010000000000000000100100000000
000000000000001111000011100000001000000000000000000000
001000000000001000000000010000000000000000000100000000
101000000000000111000011101101000000000010000000000000
010000000000001111100110110101100000000000000100000000
110000000000000111100011110000100000000001000000000000
000000000000001000000000010001100000000000000100000000
000000000000001111000011110000000000000001000000000000
000000000000000000000000000000000000000000100100000000
000000000000000000000000000000001001000000000000000000
000000000000000000000000000000000000000000100100000000
000000000000000000000000000000001010000000000000000000
000000000000000000000000000101100000000000000100000000
000000000000000000000000000000000000000001000000000000
000000000000000000000000000001100000000000000100000000
000000000000000000000000000000100000000001000000000000
.ramb_tile 10 7
000010000000000000000000001000000001000000
000001000000001011000000001011001100000000
001000000000001000000000001101000001000000
100000000010101011000011010101001111000000
110000100000000111100000000000000000000000
110000000000000000000000001011000000000000
000000000001000000000000001000000000000000
000000000000000011000000000011000000000000
000010100000011000000000000000000000000000
000001000000101011000011110011000000000000
000000000010000111100000001001100000000000
000000000000000001000010000111100000000000
000000001010000000000111110000000000000000
000000101100000000000111100001000000000000
010000000001001000000000010000000000000000
010000001000001101000011101111000000000000
.logic_tile 11 7
000000000000011000000000011000000000000000000100000000
000000000000000001000010001101000000000010000001000000
101000000000000000000000010001000000000000000100000000
001000000000000000000010000000100000000001000001000000
110000000000000000000110000000000000000000100100000000
110000000000000000000000000000001000000000000001000000
000000000000000000000110000111000000000000000100000000
000000000000000000000000000000000000000001000001000000
000000000000000000000000000000000000000000000000000000
000000000000000001000000000000000000000000000000000000
000000000000100000000000000000001010000100000100000000
000000000001010000000000000000010000000000000001000000
000000000000011001100111000111000000000000000100000000
000000000000101101000000000000000000000001000001000000
000000000000000000000000000000011000000100000100000000
000000000000000000000000000000010000000000000001000000
.logic_tile 12 7
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000100000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000100000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.io_tile 13 7
000000000000000010
000100000000000000
000000000000000000
000000000000000001
000000000000100010
000000000000110000
001000000000000000
000000000000100000
000000000000000000
000100000000000001
000000111000000000
000000001000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 0 8
000000000000000000
000000000000001000
000000000000100000
000000000000000000
000000000000001100
000000000000000100
000100011000000000
000000001000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 8
000000000000000000000000000101100000100000010100100000
000000000000000000000000000000101110100000010000000000
001000000000000000000000000111000000101001010100000000
100000000000000000000010101101000000000000000000000000
010000000000000101000000000000011010101000000100100000
100000000000000000000010000111000000010100000000000000
000000000000001000000011111001111010101001010010000000
000000000000000001000010001101110000101010100000000000
000000000000000000000111100011000000100000010100000000
000000000000000000000100000000101110100000010000000000
000000000000000011100000000101101011111000100010000000
000000001110000000100000000000101010111000100000000000
000000000000000011000000000011100000100000010100000000
000000000000000000100000000000001110100000010000000000
110000000000000000000000000000000001001111000000000000
000000000000001001000000000000001110001111000000000000
.logic_tile 2 8
100000001100000000000000000000000000000000100100000000
000000000000000000000010000000001110000000000000000001
111000000000000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
110000000001010000000000000000000000000000100100100000
000000000000000000000000000000001101000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000010010000000000000000000000000000
000001001001010101000000000000001000000100000100000000
000000100000100000000000000000010000000000000010000000
000000000000100101000000000000011100000100000100000000
000000000001000000000000000000000000000000000000100000
010000000000000000000000000000000000000000000000000000
000000001010000000000000000000000000000000000000000000
.ramt_tile 3 8
000000010000000000000111100000000000000000
000000000000000000000000000101001011000000
101000010000001000000000010001100000000000
000000000000000111000011110101101101000000
110000000100001111100111101000000000000000
110000000000001111100110001011000000000000
000010100000000011100000000000000000000000
000001000000000000100000001101000000000000
000011100000000011100111000000000000000000
000000000000001001000100000011000000000000
000000000001010000000000000001100000000000
000000000010100000000011101001000000000000
000000000000000000000011101000000000000000
000000000000000000000100000111000000000000
010010000000000001000000000000000000000000
110001000000000000100000000011000000000000
.logic_tile 4 8
000000000000000111100010100001100000000000001000000000
000000000000000000100000000000100000000000000000001000
000000000000000000000010100000000000000000001000000000
000000000000000000000000000000001000000000000000000000
000000000000000000000111100000001000001100111010000011
000000000010000000000100000000001011110011000000000000
000000000000000000000000000000001001001100111000000000
000000000000000101000000000000001010110011000000100101
000001000001100000000000000001001000001100111000000000
000010101011010000000000000000100000110011000000000100
000000000000000000000000000011101000001100111010000000
000000000000000000000010000000100000110011000000000000
000000000000000000000000000111101000001100111000000000
000000000000000001000000000000100000110011000000000010
000000000000000000000000000000001000001100111000000000
000000000000100000000010000000001110110011000000000010
.logic_tile 5 8
000000000000000011100110110000001001001100111000100000
000000000110000000000011110000001010110011000000010100
101010000110010101000010100000001001001100110000000000
000000001110101111000010100000001100110011000010000100
010000000000001000000010110000011000010101010000000000
010000000000001001000110100011010000101010100000000001
000001000000001001100000000000011000000100000110100000
000000000000001001100000000000000000000000000110000010
000000000000001000000000010101001001000101000000000100
000000000000000001000010010000111110000101000000000000
000000100000000011100000000001100001011001100000000100
000001000000000000100000000000101001011001100000000001
000001000000000000000000000101101010000011000000000001
000000100000000000000000001101001101001111000000000000
010000000000000001000000001001100000110000110000000000
000000000000000000100000000001101000001111000000000000
.logic_tile 6 8
000000100000000000000000000000000000000000000000000000
000000000000000000000010110000000000000000000000000000
101000000000000000000000000000001110001100110010000000
000000000000000000000000000000001111001100110000100000
010000000000000000000010111000000000111001110000000000
110000001110000000000110000101001100110110110010000010
000000000010100001100000001000000001011001100000000000
000000000000000000000000000111001100100110010000100100
000000000000100000000000000111000000000000000000000100
000000000001010001000000001111100000111111110000000000
000000001000000001100010100001000000000000000100000000
000010000000001101100100000000100000000001000000000000
000000000000000001100110011011101010111100000010000000
000000000000000000100110010111110000111110100010000000
110010100000001101000000000000001111001100110000000000
010000000000001001100000000000011110001100110000000100
.logic_tile 7 8
000000000000000000000000000000000001000000001000000000
000000000000000000000000000000001000000000000000001000
101000000000111101100000000111000000000010101010100000
000000000000100001000000000000101100000001010001100111
110001000000000001100000000111001000001100110100000000
010000001100000000000000000000101010110011001000000000
000000000000000011100000000001101110001100110100000001
000000000000000000000000000000011100110011001000000000
000001000110100001100000001000000000010110100110000000
000010100001010001000010000001000000101001010000000000
000000000000000000000000000111011000000010000000000000
000000000000000000000000000000101111000010000000000000
000001000000000000000110010000000000000000000000000000
000010000000000000000010000000000000000000000000000000
010000000000000000000000001011000000010110100000000000
110000000000010000000000000001000000000000000000100010
.logic_tile 8 8
000000000000000000000110100000000000000000100100000000
000000000000001101000010110000001010000000000000000100
101000000000000101100110000111000000010110100100000010
000000000000000000000000000000000000010110101000000000
110000000000000011100010110000001110000100000100000000
010000000000000000100110100000010000000000000000100000
000001000000001101000000001101100000101001010000000000
000000000000000101100000001001001001011001100000000000
000000000110000000000000010011101010101011000000000000
000000000000000000000011010001011111111111000010000000
000000001100000101000000001011100001100000010000000000
000000000000001111000000000001001110110000110000000010
000001000000100101000110000000000000000000000000000000
000010001110010000100010000000000000000000000000000000
110000000000001111000000001101001000111101010000000000
110000000000000111100000000101110000101000000000000000
.logic_tile 9 8
000000000000000000000010100000001010000100000100000000
000000000000000101000000000000010000000000000000000101
101000000000000000000000000000011010000100000100100000
000000001100000101000010100000010000000000000000000101
010000000000000101000011100000000000000000000100000000
110000001110000000000010100001000000000010000000000100
000000001101000101000010100000000000000000000100000000
000000000000000000000000001001000000000010000000000100
000010000000000000000000000000000001000000100100000100
000001000000000000000000000000001000000000000000000000
000000000000000000000000000101000000000000000110000001
000000000110000000000000000000000000000001000000000000
000000000000000000000000001000000000000000000100000001
000000100000000000000000001001000000000010000000000000
000000000000000000000000000000011010000100000100000001
000000000110000000000000000000000000000000000000000100
.ramt_tile 10 8
000000010000100000000000001000000000000000
000000001111010000000000001011001111000000
101000010000001000000000000001100001000000
000000000000001011000000000111001010001000
010000001000000000000111101000000000000000
110000000000000000000000000011000000000000
000000000000101000000000000000000000000000
000000000001011111000000001011000000000000
000000000000000011100111110000000000000000
000000001100000000000011010111000000000000
000000000000001000000111001011000000000000
000000000000001011000111101011100000000100
000000000000100111100111101000000000000000
000000000000010111000100001111000000000000
110000000000000111100011100000000000000000
110000000000000000100000000011000000000000
.logic_tile 11 8
000000000000000111100000000000000000000000000000000000
000000001110000000100000000000000000000000000000000000
101000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
110010100000000000000111100000000000000000000000000000
010001000000000111000000000000000000000000000000000000
000000000000000000000111100000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000011101000000101001010000000000
000000000000000000000011111101000000000000000010000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000001000001101111010100000000
000000000001010000000000001101001110000110000000100000
000000000000000111100000000000000000000000000000000000
000000000000000000100000000000000000000000000000000000
.logic_tile 12 8
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000001100000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.io_tile 13 8
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000001110000000100
000000000000000100
000000000000000000
000000000000000000
000000000000000000
101100000000000000
010000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 0 9
000000000000000000
000000000000000000
000001011000000000
000000000000000000
000000000000001100
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 9
000000000000000000000000000000000001000000001000000000
000000000000000000000000000000001100000000000000001000
000000000000001000000000000111111100001100111000000000
000000000000001111000000000000000000110011000000000000
000000000000000111000000000000001000001100111000000000
000000000000000000100000000000001010110011000000000000
000000000000000000000000000111001000001100111000000000
000000000000000000000000000000100000110011000000000000
000000000000001000000110100000001001001100111000000000
000000000000000101000000000000001111110011000000000001
000000000000001000000000000000001000001100111000000000
000000000000000101000000000000001101110011000000000000
000000000000000000000111000000001000001100111000000000
000000001000000000000000000000001100110011000000000000
000000000000000101100110100001101000001100111000000000
000000000000000000000000000000000000110011000000000000
.logic_tile 2 9
000000000000000000000000000001100000000000000111100001
000000000000000111000000000000100000000001000000000000
001000000001010111100111100001001010101001010000000000
100000000000100000100000001111000000101010100000000000
010000000000000101100010110101000001001100110000000000
110000000000000000100111110000101100110011000000000000
000000000000000111100000000101100000000000000110100000
000000001110000000000000000000000000000001000010000010
000100000001000101000000010000000000000000000100000001
000100000000100000100010001011000000000010000000000011
000010100000001000000000001000000000000000000100000001
000001000000000001000000000001000000000010000000000011
000000000000000011100000010011000000101001010000000000
000000000000000000000010110111001010100110010000000000
010000000000000111000000000000011110000100000101000001
000000000100000000000000000000000000000000000010000001
.ramb_tile 3 9
000000100000000001000000001000000001000000
000000000000000000100010010101001000000000
001000000000001000000110100101000001000000
100000000000000101000000000111001011000000
110000000010001101100110100000000000000000
110000000000000101000000001001000000000000
000000000001010101100000001000000000000000
000000000000100000000010001001000000000000
000000000000000000000000000000000000000000
000000000000000000000011101101000000000000
000000000000001000000000000011000000000000
000000000000001111000000000101100000000000
000000000000000000000010001000000000000000
000000000010000001000000000011000000000000
110000000000000111000000000000000000000000
110000000000000000000000000001000000000000
.logic_tile 4 9
000000000000000000000000000101101000001100111000100000
000000000000000000000000000000000000110011000001010001
101000000000000101000000000011001000001100110000000000
000000000000000101000010100000100000110011000001000001
110000000000000111100010101000000001011001100000000010
110000000000000000100000001001001011100110010000000000
000000000000001000000010101011101011000011000010000000
000000000000000011000010011011101100000000000000000000
000000000000000000000000010111101110010101010110000000
000000000000000000000011010000010000010101010000000000
000000000000000001100111001101011000010100000000000000
000000000110000000000010001101100000000001010000000000
000000000000000000000010000000011001001100110000000000
000000000110000000000010000000001001001100110000000100
010000000000000000000000000000011001001100110000000010
000010000000000001000000000000001000001100110000000010
.logic_tile 5 9
000000000000001101000011000011100000000000000000000000
000000000000000101100010100001100000111111110010000100
101011000100101000000010100011001011011110110000000000
000001000000001011000000000001011111000100100000000000
000010000000010000000110000000001000000100000100000000
000001001010100000000000000000010000000000000000000000
000000000000000001110000000000011110000100000100000000
000000000000000000000000000000010000000000000000000000
000000100000000000000000000000000001000000100110000000
000001000000000001000000000000001000000000000010000000
000000000100100000000110000000000000000000100100000000
000000000000000000000100000000001111000000000000000000
000000000000010000000000010001111110000010100000000000
000000000000100000000010001001100000010100000000000000
000000001010000000000011100000011010000100000100000000
000000000100000011000011110000000000000000000000000000
.logic_tile 6 9
000000000000000000000110110000001100000100000100000000
000000000001010000000011100000010000000000000000000000
101000000000010000000010100000000001011001100000000000
000000000000001101000010111001001001100110010000100000
010000000000001000000000001000001011000001000000000000
010000000000000001000010110011001011000010000000000000
000000100000001101000110001101111001010000100000000000
000001000000000101100000000101101111100000110000000000
000000000000001000000010100011101101101000110100000000
000000000000001111000000000000111010101000110000000000
000010100000001000000010000011011000010111110000000000
000000000000000001000100001111011011010111100010000000
000000000000000000000000011111000000000000000000000000
000000000000000001000010000101000000101001010000000000
010000000000010000000000010000000000000000000100000000
000000001010000000000010001101000000000010000000000000
.logic_tile 7 9
000100000000100000000000000000000000010110100000000000
000000000001010000000011110011000000101001010010000000
101000000000000000000110000000000000000000100000000000
000000000000000000000000000000001110000000000000000000
010000000001000000000111100000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000001100011100110100101111100111110100000000000
000000000001010000000000000000100000111110100000000000
000000000010001000000000000001111100101000010000000000
000000000000000111000000001101101100000100000000100000
000000000100000101000111000000000000000000000000000000
000010000000001101100100000000000000000000000000000000
000001000000100000000110000000000000000000100100000011
000010100000001101000000000000001111000000000010000011
010000000000000000000000000101111101000011010000000000
110000000000000000000000000000101101000011010000000000
.logic_tile 8 9
000000000000000000000000000101101101000110000000000000
000000000000000000000000000111011100000101000000000000
101000000000001000000000001000000000000000000100000000
000000000000001111000000000111000000000010000000000000
110000000000000000000000000000011100000100000100000000
110000000000000000000000000000000000000000000000000000
000000000001011000000000000000011100000100000100000000
000000000000000001000000000000010000000000000000000000
000000000000101000000110000011100000000000000100000000
000000000001011011000100000000100000000001000000000000
000000000000001011100010011111111100101001010000000000
000000000000001001100111001111100000010101010000000000
000000001100001001100110100000000000000000100100000000
000000000000000011000000000000001100000000000000000000
010000000001010000000110010000000000000000000100000000
010000000000100111000010000111000000000010000000000000
.logic_tile 9 9
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
101000000000000000000000000000000000000000000000000000
000000000001000000000000000000000000000000000000000000
110000000000000000000000000000000001000000100100000000
010000000000000000000000000000001111000000000000000000
000000000000000111100111100000000001000000100000000000
000000000000000000100100000000001100000000000000000000
000001000000000000000011100000001100000100000100000000
000011100010000000000011100000010000000000000000000000
000000000000001001100000000101111100000000100000000000
000000000000000001100000001111101110100000110000000000
000000000000000000000000010000000000000000000000000000
000000000000000111000010000000000000000000000000000000
010000000000000000000011100000000000000000000000000000
110000000000000000000100000000000000000000000000000000
.ramb_tile 10 9
000000000000000000000000000000000000000000
000100010000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000001010000000000000000000000000000
000000000000100000000000000000000000000000
000000100000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 11 9
000000000000000000000000000000000000000000000000000000
000000000000000000000011100000000000000000000000000000
101000000000000000000000000000000000000000000000000000
000001000000000000000000000000000000000000000000000000
010000000001010000000000000000000000000000000000000000
010000000000100000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000100000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000110100000
000000000000000000000000001111000000000010000100100100
000000000000000000000000000000000000000000000000000000
000000000000000000000010000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 12 9
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
101000000000000000000000000000000000001111000100000000
101100000000000000000000000000001100001111000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000100000000000000000000000000000000000000000
000000000001000000000000000000000000000000000000000000
000000000000000001100000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000111000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.io_tile 13 9
000000011000000000
000000001000000000
000000000000000000
000000000000000001
000000000000000100
000000000000000000
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 0 10
000001010000000000
000100001001000000
000010000001100000
000000110000010000
000010000000010010
000000010000010000
001100000000000000
000000000000000000
000010000011000000
000100110001000000
000000000000100100
000000000000011000
000010000000000000
000000010000000000
000000000000010010
000000000011000100
.logic_tile 1 10
000000000000000101000010100111001000001100110000000000
000000000000001111000010100000100000110011000000010000
001000000000000111000000000000000001001111000100100000
100000000000000000000011100000001110001111000000000000
110000000000000000000000001101101011010101100000000000
010000000000000000000010110101111001101001100000000000
000000000000000101000010100011101101100000000000000000
000000000000000000000010100000101101100000000000000000
000000000000001000000000001000011011100000100000000000
000000000000000101000010011001011010010000010000000000
000000000000000000000110010001001110000011110000000000
000000000000000000000010000001100000111100000000000000
000000000000000001000000001101100000001111000000000000
000000000000000000000010001101101000110000110000000000
000000000000001001100000001001011110001100000000000000
000000000000000111000000000001101001110000000000000000
.logic_tile 2 10
000000000000000000000110110000011110011010010000000000
000000000000000000000010101111001010100101100000000000
000000000000001000000010101000011001101100010000000001
000000000000001101000100001011001100011100100011000010
000000000001011111100010100101001100010101010010000001
000000000000000101100110100000100000010101010000000000
000000000000011001000111100000001110111111000000000000
000000000000100101100000000000001111111111000000100010
000100000000000001000000001101101011000110000000000000
000000000000000000100000000111001010010100000000000000
000000000010001001000110100101111110010101010000000000
000000000000000001000100000000110000010101010000000000
000000000000000001100110000001011001000000000000000000
000000000000000000000110011001111100100000000010000000
000000000000001001100110000101101010001100110000000000
000000001110001001000100000101011011001000010000000000
.ramt_tile 3 10
000000010000000000000111001000000001000000
000000001000001001000100000101001000000000
101000010000000000000111001011100000000000
000000000000000111000111111011101001001000
010001000000000000000111100000000000000000
110000000000010000000100001111000000000000
000000000000000111100000001000000000000000
000000000000000001100000000101000000000000
000000000000000000000000000000000000000000
000000000000000001000000000011000000000000
000000000000000000000010011001000000000000
000000000100000000000010011001000000000100
000000000000000000000010001000000000000000
000000000000000000000000001001000000000000
110000000000000111100000011000000000000000
110000000000000000000010101111000000000000
.logic_tile 4 10
000000000000001101000011100000011000000011110100000001
000000000000001111000010100000000000000011110000000000
101010000000100111100010100001011010000000010000000000
000010100000010000100010101101011101000000000000000000
010000000000000000000111011001001011001011000000000000
110000000000000101000010001111001010001110000000000000
000000000000000011100110011001011101101110000000000000
000000000000000001100011101001111010011110100000000000
000000000000000000000110000000000000000000000000000000
000011100000000000000010000000000000000000000000000000
000000001010001000000000000111011100000000000000000000
000000000000000011000010001001101110110011000000000000
000000000000001000000010000000000000000000000110000010
000000000000001101000100001011000000000010000010100010
010000000000010000000111101000011000010101010000000000
000000000000100000000000001101010000101010100000000000
.logic_tile 5 10
000000000000001101100000011111101010000011000000000000
000000000000001011000011010001001010001100000000000000
001001000000101101100000001000001010101010100000000000
100010100001001011000010101111010000010101010000000000
000010100110001101000010001001101101000000000000000000
000001000100000011000011100111011010000000100000000000
000000001100000001000010000111011101100010000000000000
000000000000001111000000001101111110001000100000000000
000000000000000001000010100001011011111100010110000000
000000000000000000000100000111001111111100000001000001
000000000000000001000111000101000001001111000000000000
000000000000000000100010000011101100110000110000000000
000000000000000111000111000000011100011010010000000000
000000000000000001000000000001011001100101100000000000
010000000000001001100010000001111011000000010000000000
000000000110000011000011100111111111000001000000000000
.logic_tile 6 10
000000000000000000000000000111011000000111000100100000
000000000000000101000010101101011110001111000000000100
101000000000001000000110100101100001000000000000000000
000000000000000001000010100101101010010000100000000000
000000000000000000000110101000000001000110000000000000
000000000000000101000000000011001010001001000000000000
000000000000000001100010110011100000000000000000000000
000000000000000101000010000000000000000001000000000000
000000000110000001100000000000011010111101010000000000
000000000000000000000000000001000000111110100010000000
000010000000001000000000001001011010000000000000000000
000010000000011001000000000101010000000001010000000000
000000001010000101000000001011000001000000000000000000
000000000000001101100000000001001100010000100000000000
010000000000000000000000001001011000010100000000000000
000000000000000000000000001101110000000000000010000000
.logic_tile 7 10
000000000000000101100010110101001111100000000000000001
000000000000000000000011100000111111100000000000100000
101000000000001000000000010001100000000000000100000000
000000000000001111000011110000000000000001000000100101
010000000000010111000110111011111010000000000000000000
010000000000000000000010101111101100000000100010100000
000000000000001111100000000000001010010000000000000000
000000000000000101000010100001011001100000000000000000
000000000000000000000000000000000000000000000000000000
000000001111010111000000000000000000000000000000000000
000011100000100000000110000111101010100000000000000000
000001000000000000000100000000111000100000000010000000
000000000000000000000000010000000001000000100100000001
000000000000000000000010010000001001000000000010000000
000000000000000000000011001101011011000000010000000000
000000000000000000000111101101001111000000000000000000
.logic_tile 8 10
000001000000001000000000010000000000000000100100000000
000000100000000001000010100000001100000000000000000000
101000000000010000000110110001011111000010000000000000
000000001110100000000010000000011010000010000010000101
010000000000000001100000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000010001000000000000000011000101000000000000001
000000000000000001000010001011010000010100000010000100
000000000000000000000010000000000001000000100100000000
000000000000000001000000000000001101000000000000000000
000000000001010000000000000101000001100000010000000000
000000000000000001000010000000001001100000010000100000
000000000000000000000000000000000001000000100100000100
000000000000000000000000000000001100000000000010000001
000000000001100000000110000000000001000000100100000000
000000000000100000000000000000001011000000000000000000
.logic_tile 9 10
000000000000000111100000000000000001000000100110000000
000000000000000111000000000000001010000000000000000100
101010100000001000000000010101011000111111110010000001
000001000000001011000010100001010000010111110000100001
110000000000000101100010010000011010000100000100000010
010000100000000000000011010000010000000000000000100100
000000000000000001000010010101000000000000000110000000
000000001100000000000011010000100000000001000010000001
000000000000000000000000010000001010000011000010000000
000000000000000000000011100000011000000011000000000000
000000000000000000000000000000011010000100000100000111
000000000000000000000000000000010000000000000000000000
000000000001010000000000001000000000000000000100000111
000000000000000000000000000001000000000010000010000110
000010000000000000000000000001000000000000000100000110
000001001110000000000000000000000000000001000000000000
.ramt_tile 10 10
000000000000000000000000000000000000000000
000000001110000000000000000000000000000000
000000000000000000000000000000000000000000
000010101000000000000000000000000000000000
000000000000100000000000000000000000000000
000000001111000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000001000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000001000000100000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 11 10
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
101000000000000111100011111001111101000000000000000000
000000000000000000100010000011111001100000000010000000
110000000000000000000000000000000000000000000000000000
110000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000110000000000000000000000000000000000000000000
000000000010000000000000000000000000000000000000000000
000000100000000111100000000000000000000000000000000000
000000000000100000000010000000000000000000000000000000
000000000000000000000011100001100000000000000110000000
000000000000000000000100000000000000000001000000100100
110000000000000011100000000000000000000000000000000000
110000000000000000100000000000000000000000000000000000
.logic_tile 12 10
000000000000000000000000010000000000000000000000000000
000000000000000000000011110000000000000000000000000000
101100100000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000100000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000001110000000000000000000000000000000000000000000
000000000000000111000000000000000000000000000000000000
000001000000000000100000000000000000000000000000000000
000000000000000000000000000000011100000100000110000100
000000000000000000000000000000000000000000000001100000
000000000000000000000000000000000000000000000000000000
000000000000100000000000000000000000000000000000000000
.io_tile 13 10
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
001100000001000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 0 11
000000000000000000
000100000000001000
000000000000000000
100000000000000000
000001010000000000
001000001000000000
001100000000000000
000000000000000000
001000000000000000
000100000000100100
000000000000001100
000000000000001000
000000000000000000
000000000000010000
000000000000000000
000000000000000000
.logic_tile 1 11
000000000000000000000000000101000000000000000100100000
000000000000000000000000000000000000000001000000000010
001000000000000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
010000000000001000000000001000000000011001100000000000
100000000000000101000000000111001110100110010000000000
000000000000000000000010100101100000010000100000000000
000000000000000000000100000000101100010000100010000000
000000000001000111100000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000100000000000000000000000000000000000000000000000
000000000000000001000000000000000000000000000000000000
000000000000100000000000000000000000000000000000000000
000000000000000101000000000000000000000000000000000000
000000000010000000000000000000000000000000000000000000
.logic_tile 2 11
000000000000001111100000000111011110001000000000000000
000000000000001111100010111001001010001001000000000000
001000000000001000000010100101111100101000000000000000
100000000000001111000000000101110000000010100000000001
000000000000000101000000000111011011010010100000000000
000000001000000011000011000001111100001001010000000001
000000100000001001000111101000000000000000000100000000
000000000000000001100011110101000000000010000000000000
000000000000001000000110001000000000000000000100000000
000000000010000001000000000001000000000010000000000000
000000000000001000000000000101101101100000000000000000
000000000000000011000010000000001111100000000010000000
000010100000100001000010010001001100001100110000000000
000000000001000111000011001001011110000100100000000000
000000000000001000000000010101001111000000010000000000
000000000000000011000010001101011001100000000000000000
.ramb_tile 3 11
010000101100000000000000000000000000000000
001000010000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000100000000000000000000000000000
001000000001000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000100000000000000000000000000000000000
.logic_tile 4 11
000000000000001101000010101000000000000000000100000000
000000000000001011100100000101000000000010000000000000
001000000000001000000000000000001111100100000000000000
100000000000000111000010100001001011011000000000000000
110000000000000000000000000011001100010101010100000000
110000000000000000000000000000010000010101010000000000
000010000000001111100000010001011000110101110000000000
000000000000000011100011000111011001101111100000000000
000000000000000001000010000000011010000100000100000000
000000000010000000000000000000000000000000000000000000
000000000000000000000000000000000000000000100110000001
000000000000000000000000000000001101000000000000100100
000000000001000101100111100000000000000000000000000000
000000000000000101100000000000000000000000000000000000
010000000000000000000000000001100000010110100100000000
000000000000000000000000000000000000010110100000000000
.logic_tile 5 11
000000000000000101000011101111101001100000000000000000
000000000000000101100000001001111101000000000000000000
101000000000100011100010101001000000100000010000000000
000000000000000000100110101001001011000000000000000000
110000000000000000000000000101100000000000000100000000
110001000000000001000010100000000000000001000000000001
000001000010101001000111001000000000000000000100000000
000000100000001011000110001101000000000010000000000000
000000100000000000000000001000000000000000000100000000
000001000000000000000000000101000000000010000000000000
000000000000000000000000000000000000000000000100000100
000000000000000001000010100101000000000010000000000000
000000000000000000000011001001011111000100010000000000
000000000000000000000000000011001011010001000000000000
010000000001000000000000011000011010010101010100000100
000010000001110001000010000001010000101010100000000000
.logic_tile 6 11
000000000000001000000000001000000000000000000100000000
000000000000000001000000000001000000000010000000000000
001000000000001000000000000000001010000100000100000000
100000000000000101000000000000010000000000000000000000
000000000000000000000110100000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000001010000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000001100000000000000000000000000100100000
000000000000000000000000000001000000000010000010100000
000001000000000000000000000000000001000000100110100000
000000100000000000000000000000001111000000000000000000
000000000000000000000000000000000000000000000000000000
000000001100000000000000000000000000000000000000000000
000000000000000000000000000000000000000000100110000000
000000000000000000000011100000001100000000000010000000
.logic_tile 7 11
000000000000000001100000001001001010010011100010000000
000000000000000000100010101001011010010010100000000000
101000000000000000000000010111101101000000000000000000
000000000000000000000010011101011011010000000000000000
010001000000000001000000000000000000000000000110000000
010010101000000000000011111111000000000010000000000001
000000000000010000000000000000000000000000000000000000
000000000000000000000011110000000000000000000000000000
000000100000000001100010010000000000000000000000000000
000001000000000000000010000000000000000000000000000000
000010101001010000000000000001100000100000010000000000
000001000000100000000000000011101101000000000000000000
000000000000001000000011100111101110000001010001000100
000000000000000101000000000000000000000001010000100000
000001000000000001000000000001100000000000000000000000
000010101010001011000000001011101100010000100000000110
.logic_tile 8 11
000000100000000101000010111011001011111001010000000000
000001001000000000100111101011011100111100110000000000
101000000000000000000011100000000000000000100100000001
000000000000000000000110110000001010000000000000000000
010000000000100101000000010000000001000000100100000000
010000000001001101000010100000001001000000000000100000
000000000000000000000000000000000001000000100100100000
000000000000000000000010100000001001000000000000000000
000000000000000101100000000001000000000000000100000000
000000000000000000000000000000000000000001000000100000
000000000000001000000000010000000000000000000000000000
000000000000000101000010100000000000000000000000000000
000000001111000000000000000111111010100000000000000001
000000000000000000000000000000011010100000000010000101
000000000000000000000000000000000000000000000100000000
000000000000001001000000001001000000000010000000000010
.logic_tile 9 11
000000000000000000000000000111100001000110000000000000
000000000000000000000000000111101101001111000000000001
101000100000010000000000000101111010000001010100000001
000001001110100101000000000000010000000001010010000100
110000000000000001100111100000000000000000000000000000
110000000000000000000100000000000000000000000000000000
000010100000001011100011111101011101000010100000000000
000000000000000001000010000101001011000011000010000001
000000000000001000000000001000000001100000010110000000
000000000000001001000000000101001011010000100000000000
000010100000001000000000010111101101000100000010000000
000000000000001111000011010000101110000100000000000101
000000000000000001100011101000000001001001000110000000
000000000000000000100100001101001010000110000000000010
010000000000001000000110010101001111001000000000000010
010000000000001001000110010000101111001000000010000001
.ramb_tile 10 11
010000000000000000000000000000000000000000
001000010000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000100000000000000000000000000000
000001000000000000000000000000000000000000
001010100000000000000000000000000000000000
000010000001010000000000000000000000000000
001000000000100000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
.logic_tile 11 11
000000000000000000000000011111101110000000010001000000
000000000000000000000011111001101101000000000000000000
101000000000000000000000000000000000000000000000000000
101000000000000111000010100000000000000000000000000000
011000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000000000000010000000000000000000000000000
000000000000000000000011010000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000011110000000000000000000000000000
000000100010000011100000001001111101101001110100000000
000010000000000000100011111101011100000000110001000000
000000000000001001000000000000000000000000000000000000
000000001110001111000000000000000000000000000000000000
000000000000010000000000010000000000000000000000000000
000000000000100000000011100000000000000000000000000000
.logic_tile 12 11
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
101000000100000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010010000000000000000011000000000000000000000000000000
110001000000000000000000000000000000000000000000000000
000000000000000000000000000000011100000100000110000000
000000000000000000000000000000010000000000000100000100
000000000000000000000000000000000000000000000000000000
000000000000000111000000000000000000000000000000000000
000000000000000000000000000000001100000100000110000000
000010000000000000000011110000000000000000000101000000
000000000001010000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.io_tile 13 11
000000000000000010
000100000000000000
000000000000000000
000000000000000001
000000000000110010
000000000000010000
001100000000000000
000000000000000000
000010000000000000
000100010000000000
000000000000100010
000000000000010000
000000011000000000
000000000000000001
000000000000000010
000000000000000000
.io_tile 0 12
000000000100000000
000100000100000000
100000000100000000
011000000100000001
000001111100000000
000000000100000000
001100000100000000
000000000100000000
001000000000000000
000100000000000000
000000000000001100
000000000000001000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 12
010000000000000000000011100000000000000000001000000000
001000000000000000000100000000001010000000000000001000
001000000000000000000111001101101011001000011100000000
100010000000000000000000000011101011010010000100000000
110001000000000101000000001001101000100001000100000000
111000000000000000100000000011101101000100100100000000
000000000000000000000111010000001100101000000000000000
001000000000000000000010000011010000010100000000000000
000000000000000001100000010000000000000000000000000000
001000000000000000000010000000000000000000000000000000
000000000000000001000000000000000000000000000000000000
001000000000001001000000000000000000000000000000000000
000000000000001000000011000011000000010110100000000000
001000000000001001000000000000000000010110100000000000
010000000000000001100111000111111110000011010000000000
001000000000000000100100001001011110000011110000000000
.logic_tile 2 12
010000000000000000000000000000000000000000100100000000
001000000000000000000000000000001101000000000000000000
001000000000000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
000000000000001000000011100000001010000100000100000000
001000000000000001000000000000000000000000000000000010
000000000000001000000000000000000000000000000000000000
001000000000000001000000000000000000000000000000000000
000000100000000000000000010000000000000000100100000000
001001000000000000000011010000001011000000000000000000
000000000000000000000000001000000000000000000100000001
001000000000000000000000000101000000000010000000000000
000000100000000000000000000000000000000000000000000000
001001000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
.ramt_tile 3 12
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 12
010000000000000000000000000000000000000000000000000000
001000000000000101000000000000000000000000000000000000
101000000000000000000000000000000000000000000100000001
000000000000000101000000000101000000000010000000000010
000000000000000000000000000000011010000100000100100000
001000000000001101000010100000000000000000000000000010
000000000000001000000000011000000000000000000100000000
001000000000000001000010001101000000000010000000000010
000000000000000000000000000000000001000000100100000000
001000000000000000000000000000001000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000001010000100000100000000
001000000000000000000000000000010000000000000000000000
000000000000000000000000000001000000000000000100000000
001000000000000000000000000000000000000001000000000000
.logic_tile 5 12
010000000000000000000110000000001000000100000100000000
001000000000000000000000000000010000000000000000000010
101000000000000001100011100000000001000000100100000000
000000000000000000000000000000001000000000000000000000
000000000000000001100000000011000000000000000100100000
001000000000000000000000000000100000000001000000000000
000000000000001000000110101000000000000000000100000000
001000000000000001000000000011000000000010000000000000
000000000000000001100010100011011000000010000000000000
001000000000000001100100000101011100000100000000000000
000000000000000001100010000000011110000100000100000000
001000000000000000100000000000010000000000000000000000
000000000000000000000010000000000001000000100100000000
001000000100000000000000000000001011000000000000000010
000000000000000011100110001111011111000000110000000000
001000000000000000100100001011101010110000000000000000
.logic_tile 6 12
010000000000000000000000010000000000000000100100000000
001000000000000000000010000000001101000000000100000100
101000000000000000000011110000000000000000000000000000
000000000000000000000010100000000000000000000000000000
010000000000000111100000000000000001000000100000000000
011000000000000000100000000000001010000000000000000000
000000000000000001100000000000000000000000000000000000
001000000000000000100000000000000000000000000000000000
000000000000000000000000000000000000000000000100000000
001000000000000000000010000101000000000010000100000001
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000001100001100110010000000000
001000000000000000000000000000101001100110010000000000
010000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
.logic_tile 7 12
010000000000000101000111101101100001101111010100000000
001000000000000101100110101011001100001111000000000000
101000000000001000000000000001011000010100000000000001
000000000000000001000000000000000000010100000000000010
010010000000101111100010000001001010000100000000000000
111000000000001111000000001001101111000000000000000000
000000000000000000000000010011001011000000000000000000
001000000000001001000010010101001011010000000000000010
000000001110000000000011000001001100101000000000000000
001000000000000001000110000011110000000000000000000000
000000000000001101100010000000000000000000000000000000
001000000000000101000010000000000000000000000000000000
000000000000000000000011101011111110011111010000000000
001000000000000000000000000111101101001001010000000010
000000000000000111000110101000011110000110100000000000
001000000000000001000000000011011000001001010000000000
.logic_tile 8 12
010010100000001001100010110001100000011111100100000000
001000000000000111100111110001101011010110100000000000
001000000000001111000110110101101010001111010100000000
101000000000001001100010100000011001001111010000000000
010000000000100001000110000011011011111000000000000000
011000000000000001000100000000101111111000000011000100
000000000000001111000110011101011011110000000100000000
001000000000000101000010010001111101110110100000000000
000000000000000011100010011011001111000110100000000000
001000000000010000100010011001001101001111110000000000
000000000001000000000010101001101100000000000000000100
001000000110100000000110001101011000000001000000000000
000000000000100000000000000111101011110000000100000000
001000000001000001000000001101101011111001010000000000
000000000000000000000010110001101101000000000000000000
001000000110000000000011000001011011000010000010000000
.logic_tile 9 12
010010000000001000000010101111111111000110100000000000
001000000000001011000100001101011100001111110000000000
101000000000001000000000001000000000000000000100000000
000000000000001111000011100101000000000010000000000001
110000000000000000000111000101100000000000000100000000
111000000000000101000100000000100000000001000010000000
000010100100001101000010111001111010000001000000000000
001001000000000011100011111111001001000001010000000001
000000000000000000000000000000000000000000100100000000
001010000000000000000000000000001000000000000000000000
000000000000011000000010000001100000000000000100000000
001000001010000001000000000000100000000001000000000000
000000000000000011100110100101000000001001000000000000
001010100000000000100100001101001110101001010010000010
000000000000001000000000010000000001000000100100000000
001000000000001011000010010000001101000000000000100000
.ramt_tile 10 12
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000010000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000001000000000000000000000000000000000000
000000000000000000000000000000000000000000
000001000000100000000000000000000000000000
000010100001010000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 11 12
010000000000000000000000000000000000000000000000000000
001000000000001001000000000000000000000000000000000000
101000000000001000000011100001000000000000000100000000
000000000000001111000000000000000000000001000100000100
010010000000000000000011101011011111101000010000000000
111001000000000000000000001011011110000000100000000000
000000000000000000000000000000001101000011100000000000
001000000000000000000000001011011110000011010000000000
000000000000000011100011110000000000000000000000000000
001000000000000000000010000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000010000000000000000000000000000000
000010100000000000000000000000000001000000100100000100
001000000000000000000000000000001000000000000100000000
010000000000000101100000011000011101001000000000000000
001010000010001111000011001001011111000100000010000000
.logic_tile 12 12
010000000000000000000111101000000000000000000100000000
001000000000000000000000000111000000000010000000100000
101000000000000000000000000000000000000000000000000000
000000001000000000000000000000000000000000000000000000
110000000000000000000000000000000000000000000000000000
111000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000100000000
001000001000000000000000000011000000000010000000100100
000000000000000111100111100000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000100100000000
001000000000000000000000000000001001000000000000000000
000000000000000000000011100000001100000100000100000000
001000000001000000000100000000010000000000000000100000
000001000000000011100000000000000000000000000000000000
001010100000000000000000000000000000000000000000000000
.io_tile 13 12
000000000100000010
000000000100000000
000000000100000000
000000000100000001
000000000100010010
000000000100110000
000010000100000000
000010010100000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000100000
000000000000000001
000000000000000000
000000000000000000
.io_tile 0 13
000000000101000000
000100000100000000
100000000100000000
000000000100000000
000000000100000000
100000000100000000
001100000100000000
000000000100000000
001000000000000000
000100000000100100
000000000000001100
000000000000001100
000001010000000000
000000001000000000
000000000000000000
000000000000000000
.logic_tile 1 13
010000000000100101100010101001011011010000000000000000
001000000001010000000011111111001101000000000000000000
001000000000001000000000001000000000010110100000000000
100000000000000101000000000011000000101001010000000000
010000000000000000000010101001000001000000000000000000
011000000000000000000000001111001000001001000000000010
000000000000001000000110010000000000000000000000000000
001000000000000101000010000000000000000000000000000000
000000000000000000000000000111111010000001010000000010
001000000000000000000000000000110000000001010000100000
000000000000000001100000000011111111001001010100000000
001000000000000000000010101001111100001001000100000000
000000000000000000000000001001011011101001010000000000
001000000000000000000000001101001111010010100000000000
010000000000000000000010110011101011100000000000000000
001000000000000000000010100000111100100000000000000000
.logic_tile 2 13
010100100000000000000000010000000000000000000000000000
001101000000000000000011010000000000000000000000000000
001000000000000000000010111000011010101000000000000000
100000000000000000000111011001010000010100000010000000
010000000000000000000000001011000000101111010100000000
011000000000000000000000001001001101000110000000100000
000000000000000000000110100000000000000000000000000000
001000000000000000000010110000000000000000000000000000
000000000000000001100000000000000000000000000000000000
001000000000000000000011110000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000001111010111110100000000000
001000000000000000000000000000110000111110100010000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
.ramb_tile 3 13
010000000000000000000000000000000000000000
001000010000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000010000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
.logic_tile 4 13
010000000000000000000000000001100000000000000100000000
001000000000001101000000000000100000000001000000000000
101000000000000000000010100000000000000000000000000000
000000000000000000000100000000000000000000000000000000
000000000000000101000010110000000000000000100100000000
001000000000000000100110000000001000000000000000000000
000000000000000011100111000000001010000100000100000000
001000000000000000100000000000010000000000000000000000
000000000000000000000000001000000001011001100000000000
001000000000000000000000001101001010100110010000000000
000000000000000000000000000000000000000000000100000000
001000000000000000000000001101000000000010000000000010
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000101000000000000000100000000
001000000000000000000000000000000000000001000000000001
.logic_tile 5 13
010000000000000000000010100000000000000000000000000000
001000000100000000000110110000000000000000000000000000
101000000000001000000010101000011000000001010000000000
000000000000000101000100001001000000000010100000000000
010000000110001000000010001001001010000010000000100000
111000000000000011000000000011101110001000000000000000
000000000000000000000011100000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000010001000000000001001000000000000
001000000000000000000000001101001001000110000000000000
000000000000001000000000000000000000000000100100000000
001000000000000001000000000000001101000000000000000000
000000000000000001100010000000000000000000100100000000
001000000000000000000000000000001111000000000000000000
010000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
.logic_tile 6 13
010000000000000000000000000000000000000000000000000000
001000000001000000000000000000000000000000000000000000
001000000000000011100000000000000000000000000000000000
100000000000000000100000000000000000000000000000000000
000000001100000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000001000000000000000000100000000
001000000000000000000000000001000000000010000000100000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
.logic_tile 7 13
010001000001010000000111100001111000010110100000000000
001010100000000101000110100001010000000010100000000000
101000000000101001100110000111101010111110100100000000
000000000001010111100110101101110000101001010000000000
110000000000000000000010011111011011000110100000000000
111000000000000000000011101001001000001111110000000000
000000000000000001000010000000000000000000000000000000
001000000000000001000000000000000000000000000000000000
000000000000101001000000011000011101100000000000000110
001000000000001011000010000011001110010000000000000000
000000000000001001000010000101101101010000100000000000
001000000000001101000000000011101101111000110000000000
000000000001000000000111100001011001010111100000000000
001000000000100001000100001001111010000111010000000000
000000000000000001100010100101001101100011110100000000
001000000000000101000000000000111110100011110000000000
.logic_tile 8 13
010000000001000001000111000011011001000011100000000000
001000000000000000100110100000001011000011100000000000
101000000000001101000011100011111001101111010100000000
000000000000001011000011100001001001101111111000000000
010000000000001111000000000001011101100000000000000000
011000000000001001100010000011111010111000000000000000
000000000000000101000010101101111000000110100000000000
001000000000001001100010110011111111001111110000000000
000001000001010001100000010101111100101000000000000000
001010100010000001000010000101111100100100000000000000
000001000000001001100110101011011000101111010100000000
001000000000000001000000000101101010101111110000000000
000000000000001011000000010111001110010100000000000000
001000000000000001000010010111100000111100000000000000
110000000000000111000000000011000001000000000000000100
111000000000000001100000001101001110010000100000000010
.logic_tile 9 13
010000000000000011100111101000000001100000010000000100
001000000000000000000110011011001010010000100000000001
101000000000000101000000010001111011000110100000000000
000000000100001111000011111001001000001111110001000000
010000000100001111000000010000000001000000100100000000
011000000000001011000011010000001100000000000001000000
000000000001010111000111000000011010000100000100000000
001000000000000111000010000000010000000000000000000000
000000000110001000000000000001000000000000000100000000
001000000000000111000000000000000000000001000000000000
000000000000000000000000010001111110001000000000000000
001000000110000001000010000000111010001000000000000000
000000000000000000000010000101011010000000010010000000
001000000000000000000000000101111100000000000000000000
000000000000000000000110000000001111001100000000000000
001000000000000000000000000000011010001100000010100000
.ramb_tile 10 13
010000000000000000000000000000000000000000
001010010000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000001000000000000000000000000000000000
001000000000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000010000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
000001000000000000000000000000000000000000
001010000000000000000000000000000000000000
000001001010000000000000000000000000000000
001000100000000000000000000000000000000000
000000000000000000000000000000000000000000
001000000000000000000000000000000000000000
.logic_tile 11 13
010000000000000000000011110000000000000000000000000000
001000000000000000000011100000000000000000000000000000
101000000000001111100000000000000000000000000000000000
000000000000001111000000000000000000000000000000000000
010000000000000000000010100000000000000000000000000000
011000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000010100000000001000000000000000000000000000000000000
001001000000000000000000000000000000000000000000000000
000000000000000001000000000111000000101001010000000000
001000000000000000000000001001001100001001000010000000
000000000000000001000000000000000000000000000000000000
001000001110000000100000000000000000000000000000000000
010000000000000000000000001000001011001011110100000000
011000000000000000000000000001011100000111110010000000
.logic_tile 12 13
010000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
001000000100000000000000000000000000000000000000000000
100000000000010000000000000000000000000000000000000000
110010000000000000000000000000000000000000000000000000
011001000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
000000000000000000000000010000000000000000000000000000
001000000000000000000011110000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000001111000000000000000000000000000000000000
000000000000000000000000011111000000000000000100100000
001000000000000000000011100011100000101001010100000000
010001000000100000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
.io_tile 13 13
000000000100000000
000100000100000000
000000000100000000
000000000100000000
000001010100000000
000000001100000000
000100000100000000
000000000100000000
000000000000000000
000100000000000000
000000000000010010
000000000000010000
000000000000000000
000000000000000001
000000000000000010
000000000000000000
.io_tile 0 14
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 14
000000000000000101000010110000000001000000001000000000
000000000000000000100111100000001011000000000000001000
001000000000000000000010110001111011001000011100000000
100000000000000000000111110001111110010010000100000000
010000000000000101000110001111001000110000000100000000
010000000000000000100000001001101010000000110100000000
000000000000000000000110000011101011001001010100000000
000000000000000000000000000001111001001011100100000000
000000000000000000000000000000000000001111000000000000
000000000000000000000000000000001110001111000000000000
000000000000000000000000010011101011011111000000000000
000000000000000000000010001001101001010110000010000000
000000000000000001100000010001001110100000000001000000
000000000000000000000010001101011110000000000000000000
010000000000001000000000000000001010000011110000000000
000000000000000001000000000000010000000011110000000000
.logic_tile 2 14
000000000000000000000000010000000000000000000000000000
000000000000000000000010000000000000000000000000000000
001000000000000000000000010000000000000000000000000000
100000000000000000000010000000000000000000000000000000
010000000000000000000000000011011100111101010000000000
010001000000000000000000000000110000111101010000000000
000000000000000000000000000000011000000001010010000000
000000000000000000000000001111010000000010100000000000
000000000000000000000110000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000110000000000000000000000000000000
000000001110000000000100000000000000000000000000000000
000000000100001000000000010111000001101111010100000100
000000000000001001000010010000001001101111010100100000
010000000000000000000000000000000000000000100100000000
000000000000000000000000000000001110000000000100000000
.ramt_tile 3 14
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000001100000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 14
000000000000000000000000011000000000011001100100000000
000000000000000000000011111001001100100110010000000000
001000000000000000000000010000000001000000100100000000
100000000000000000000011010000001010000000000000000000
010000000000000000000000000111100000000000000100000000
010000000000000000000000000000100000000001000000000000
000000000000000000000000000000001110000100000100000000
000000000000000101000000000000010000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000011000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000011000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000000000100101100000000111100000000000000100000000
000000000000000000100010000000000000000001000000000000
.logic_tile 5 14
000000000000000000000000001000000000000000000100000000
000000000000000000000000001101000000000010000000000000
001000000000000001100000001000000000000000000100100001
100000000000000000000000000111000000000010000000000000
000000000000001000000111000000011000000100000100100000
000000000000000001000100000000000000000000000000000000
000000000000000101000111000000000000000000100100100000
000000000000000000000010100000001010000000000000000000
000000001010000000000000000000000000000000100100000000
000000000000000000000000000000001011000000000000000000
000000000000000000000000010101100000000000000100000000
000000000000000000000010000000000000000001000000000000
000000000000000000000000000101100000000000000100000000
000000000000000000000000000000100000000001000000000000
000000000000001000000000000011100000000000000100000000
000000000000000001000000000000100000000001000000100000
.logic_tile 6 14
000000000110000000000000010000000000000000000000000000
000000000000000000000011110000000000000000000000000000
001000000110000000000000000000001010110011110000000000
100000000000000000000000000000001111110011110010000000
010000000000001111000000000000000000000000000000000000
010000000000001011100000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000010000000000000000000000000000000000000000000000000
000000000000000000000011000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000111000000100000010100000000
000000000000000000000000000101101101110110110100100000
000000000000000000000010100000000000000000000000000000
000000000000000000000010000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 7 14
000000000000001000000000010111011010111011110100000000
000000000000000111000011111001111100101011110000000000
001000000000000000000000010000000000000000000000000000
001000000000000000000010010000000000000000000000000000
010001000000010000000011110000000000000000000000000000
110010100000000101000110110000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000010100000000000000000000000000000
000000000000001000000000000000000000000000000000000000
000000000000001011000000000000000000000000000000000000
000000000000000000000000000001101001010110110100000000
000000000000000000000000000000111111010110110000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000010000000000000000000000000000000
000000000000000000000000010000001000001111010100000000
000000000000000000000011001101011010001111100000000000
.logic_tile 8 14
000000000000000000000000001111001100010001110100000000
000000000000011101000011110011001100111000100010000000
101000000000000000000000000011101010110100010110000000
000000000000001101000000000111001100111110100001000000
010000000000010101000000000011101111110001110100100000
010000000000000000100000000000101011110001110010000000
000000000000000101000010100001011100111001010100000000
000000000000000000100100000011011110111001100000100000
000000100000101101000000001111011110010100000100000001
000001000001000101000000001101000000101001010000000000
000000000000000000000110110000011000011100100100000100
000000000000000101000010100011001110101100010000000000
000010100000000101100000001011001111011001010100000000
000000000010000101000000000101001100011010100000000000
000000000000001000000000000011101110011100100110000000
000000000000000101000000000011101110001100000000000000
.logic_tile 9 14
000000000000101000000110110000001110000100000100000000
000000000001000011000011100000010000000000000000000000
101000000000000000000111010000000001000000100100000000
000000000000000101000111010000001111000000000000000000
010000000000001001000011111001101011000000000000000000
010000000000001011000011010101111001001000000000000000
000000000000000111100010100101011000010111100000000000
000000000000001101100110100101101001001011100000000000
000000000000000000000000000000000000000000000100000000
000000000000000000000000000101000000000010000000000000
000000000000000000000000000101000001100000010000000000
000000000000000000000000000000101011100000010010000000
000000000000000000000000010000011011000011000000000000
000000000000000000000010110000001011000011000000000000
000000000000000000000000010001000000000000000100000000
000000000000000000000010110000000000000001000000000000
.ramt_tile 10 14
000000001000000000000000000000000000000000
000000000000010000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000001110100000000000000000000000000000
000000000001010000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000100000000000000000000000000000000000
000000000010000000000000000000000000000000
000000000000000000000000000000000000000000
000000001010000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 11 14
000000000000100000000011110000001111110000000100100000
000000001111010000000011010000011000110000000100000000
101000000000000000000000000001000000100000010101000000
000000000000000111000000000000101111100000010100000000
110000000000001111100010000000000000000000000000000000
010100000000001111100000000000000000000000000000000000
000000000000000000000111100000000000000000000000000000
000000000000000000000010000000000000000000000000000000
000000000000000000000000010101001000010111100000000000
000000000000000000000011011101011010000111010001000000
000000000000000111100000001101101011010111100000000001
000000000001010000000000001101101100000111010000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000011110000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 12 14
000000000000000000000000000001101100000000000100000010
000000000000000000000000001101100000010100000100000000
001000000000000000000111100000000000000000000000000000
100000000000000000000000000000000000000000000000000000
110001000000000000000110100000000000000000000000000000
010010000000000000000100000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000110000111000000010000000000000000000000000000
000000000000000000100011100000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.io_tile 13 14
000000000000000010
000100000000000000
000000111000000000
000000000000011001
000000000000010010
000000000000110000
001100000000011000
000011110000000000
000000000000000000
000100000000000000
000000000000000010
000000000000110000
000000000000000000
000000000000000001
000000000000000010
000000000000000000
.io_tile 0 15
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 15
000000000000000000000000000011001011000100000001000000
000000000000000000000000001101011111000000000000000000
001000000000000000000000000000000001110110110100100101
100000000000000000000000000011001100111001110101000000
110000000000000000000010010000000000000000000000000000
010000000000000000000011010000000000000000000000000000
000000000000000000000000000000001010010100000000000000
000000000000000000000000001101010000101000000000000000
000000000000000001100000000000000000000000000000000000
000000000000000000000010000000000000000000000000000000
000000000000000001100000000111011110000001010000000000
000000000000000000000000000011110000000000000000000000
000000000000000000000110000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000000000000000000110001000000000000000000100000000
000000000000000000000000000011000000000010000100100001
.logic_tile 2 15
000000000000000000000111000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
010000000000001000000000000000000000000000000000000000
100000000000000101000000000000000000000000000000000000
000000000000000001000110100000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000001000000000111001110000000000
000000000000000000000000001111001010110110110000100000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000011101111010111000100100000010
000000000000000000000010011111101001110000110000100000
.ramb_tile 3 15
000000000110000000000000000000000000000000
000000010000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000100000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 15
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 5 15
000000000000000000000000000000001100000100000100100100
000000000000000000000000000000010000000000000000000000
101000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000001100000100000100000000
000000000000000000000000000000010000000000000000000000
000000000000000000000110010000000000000000000000000000
000000000000000000000010010000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 6 15
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
001000000000000000000000000000000000000000000000000000
100000000000000000000000000000000000000000000000000000
010000000000000000000011000000000000000000000000000000
110000000000000000000100000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000001000000000000000000000000000000000000
000000000000000000000000000011111011101100010100000000
000000000000000000000000000000101100101100010101000000
000000000000000000000110100000000000000000000000000000
000000000000000001000100000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 7 15
000000000000000000000000000000001010000100000100000001
000000000000000000000000000000000000000000000000000000
101000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
010000100000000000000111100000000000000000000000000000
110001000000010101000000000000000000000000000000000000
000000000000000101000010100000000000000000100000000000
000000000000000000000000000000001110000000000000000000
000000000000000000000000000000000001000000100100000000
000000001110000000000000000000001010000000000000000010
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000001100100000000000000000000000000000000000000000
000000000001010101000000000000000000000000000000000000
000000000000000000000000000000011010000100000100000000
000000000000000000000000000000010000000000000000100100
.logic_tile 8 15
000000000000001000000000010000001010000100000100000000
000000000000001111000010000000000000000000000000000000
101000000000000000000000000000000000000000100100000000
000000000000000000000000000000001011000000000000000000
110000000000000000000000000011101101101001010000000000
110000000000000001000011100001001100000110100000000000
000000000000000001100000000101100000000000000000000000
000000000000000000100000000000000000000001000000000000
000000001110000101100000011000000000000000000100000000
000000000000000000000010100111000000000010000000000000
000000000000001101100000000000000000000000000100000000
000000000000000101000000001111000000000010000000000000
000000000000101000000110000000000000010000100000000100
000000000001000101000010001011001001100000010000000000
000000000000000001000110100011111110000000000000000000
000000000000000000000000000011011110100000100000000000
.logic_tile 9 15
000000000000000000000000000000000001000110000000000000
000000000000000000000010101011001110001001000000000000
101000000000000111000000000000000000000000100100000000
000000000000000000000000000000001100000000000110000000
010000000000000000000010100000011000000100000100100000
010000000000000000000000000000000000000000000100000000
000000000000001001000000000101011011001001010000000000
000000000000000001000000000000101010001001010000000000
000000000000000101100110110000000000000000000100000000
000000000000000000100110001111000000000010000100000000
000000000000000000000000000000000000000000100100000000
000000000000000000000000000000001101000000000100100000
000000000000000000000011010000000000000000000000000000
000000000000000000000011100000000000000000000000000000
010000000000000001100000000000000000000000000100000001
000000000000000000000000001111000000000010000100000000
.ramb_tile 10 15
000000000000100000000000000000000000000000
000000010001000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000001000000000000000000000000000000000000
000000100000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000001000000000000000000000000000000
000000000000100000000000000000000000000000
.logic_tile 11 15
000000000000000000000111100000000000000000000000000000
000000000000000000000100000000000000000000000000000000
101000000001000000000000000000000000000000000000000000
000000000000100000000000000000000000000000000000000000
110000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
000000000000000000000111100000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000010000000000000000000000000000
000000000000000000000011110000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000001000000000000000000000000000000000000
000000000000000000000000001001001110010110100100000000
000000000000000000000011111101110000111101010000100000
110000000000000000000000000000000000000000000000000000
010000000000000000000000000000000000000000000000000000
.logic_tile 12 15
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000001000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.io_tile 13 15
000000000000000010
000100000000000000
000000111000000000
000000001000000001
000000000000110010
000000000000110000
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000010
000000000000110000
000000000000000000
000000000000000001
000001010000000010
000000001000000000
.io_tile 0 16
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.logic_tile 1 16
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 2 16
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000001000000000000000000000000000000000000000000000000
000000100000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.ramt_tile 3 16
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 4 16
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 5 16
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 6 16
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000001000000000010110100000000000
000000000000000000000000001101000000101001010000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000011110000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000100000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 7 16
000000000000000000000000000000000000000000000000000000
000000001000000000000000000000000000000000000000000000
101000000000000000000000000000000000100000010100000000
000000000000000000000000000111001101010000100100000010
110000000000000000000000000011011100101000000100000000
110000000000000000000000000000110000101000000100000010
000000000000000000000000000000000000101111010100100000
000000000000000000000000001111001101011111100100000000
000000000000000101100010000011001100101000000100000000
000000000000000000000000000000010000101000000100100000
000000000000001000000110101000000000100000010100000001
000000000000000101000000001111001101010000100100000000
000000000000001000000110111000001100101000000100000000
000000000000000101000110100011010000010100000100000010
010000000000000000000000010000000000000000000000000000
000000000000000000000010100000000000000000000000000000
.logic_tile 8 16
000000000000000000000000010111000000000000000100000000
000000000000000000000011010000100000000001000100000000
101000000000000000000111000000000001000000100100000000
000000000000000000000000000000001001000000000100000000
010000000000001000000000000000001110000100000100000000
010000000000001011000000000000000000000000000100000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000100000000
000000000000000001000000000011000000000010000100000000
000000000000000000000000000000000000000000000000000000
000000000000000001000000000000000000000000000000000000
000000000000000000000000000000000001000000100100000000
000000000000000001000010000000001100000000000110000000
010000000000000000000000000000000000000000000100000000
000000000000000000000000000101000000000010000100000000
.logic_tile 9 16
000000000000000000000010101011101000101011110100100000
000000000000000000000000000001010000000011110000000000
101000000000000000000000000000000000000000000000000000
000000000000001101000000000000000000000000000000000000
010000000000000000000111000000000000000000000000000000
110000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000101100000000000000000000000000000000000
000000000000000000100000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.ramt_tile 10 16
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
000000000000000000000000000000000000000000
.logic_tile 11 16
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.logic_tile 12 16
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
.io_tile 13 16
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 1 17
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 2 17
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000100010
000001110000110000
000000000000000000
000000000000000001
000000000000000010
000000000000000000
.io_tile 3 17
000000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 4 17
000000000000000010
000000000000001000
000000000000000000
000000000000000001
000000000000100010
000000000000010000
001100000000000000
000000000000000000
000001010000000000
000100001000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 5 17
000000000000011000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 6 17
000000011000000000
000000001000000000
000000000000000000
000000000000000000
000000000000000100
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 7 17
110000000000000000
010000000000000000
010000000000000001
000000000000000001
000000000000000100
000000000000001100
001100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000010000000000000
000001010000000000
000000000000000000
000000000000000000
.io_tile 8 17
100000000000000000
000000000000000000
000000000001100000
000000000000000001
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
010000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 9 17
000000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
001000000000000000
000000000000000000
000000000000000000
100100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 10 17
000000000000000010
000000000000000000
000000000000000000
000000000000000001
000000000000100010
000000000000110000
000000000000000000
000000000000000000
100000000000000000
000000000000000000
000001111000000000
000000000000000000
000000000000000000
000000000000000001
000000000000000000
000000000000000000
.io_tile 11 17
000000000000000010
000000000000000000
000000000000000000
000011110000000001
000000000000000010
000000000000110000
001100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.io_tile 12 17
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000100000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
.ram_data 10 7
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.ram_data 10 3
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.ram_data 3 7
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.ram_data 3 3
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.ram_data 10 5
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.ram_data 3 5
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.ram_data 3 9
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.ram_data 3 1
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
.sym 1 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 2 lvds_clock_$glb_clk
.sym 3 r_counter_$glb_clk
.sym 4 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
.sym 5 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 6 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
.sym 7 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 8 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 48 w_rx_09_fifo_data[14]
.sym 49 w_rx_09_fifo_data[12]
.sym 177 w_rx_09_fifo_data[23]
.sym 178 w_rx_09_fifo_data[25]
.sym 180 rx_fifo.mem_i.0.2_WDATA_1
.sym 181 rx_fifo.mem_i.0.2_WDATA
.sym 182 w_rx_09_fifo_data[27]
.sym 183 rx_fifo.mem_i.0.1_WDATA
.sym 204 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 291 w_rx_09_fifo_data[15]
.sym 292 w_rx_09_fifo_data[19]
.sym 293 rx_fifo.mem_q.0.3_WDATA_1
.sym 295 w_rx_09_fifo_data[21]
.sym 296 w_rx_09_fifo_data[29]
.sym 297 w_rx_09_fifo_data[17]
.sym 298 w_rx_09_fifo_data[10]
.sym 323 rx_fifo.wr_addr[4]
.sym 324 rx_fifo.mem_i.0.1_WDATA
.sym 328 rx_fifo.mem_i.0.2_WDATA
.sym 374 iq_tx_n_OUTPUT_CLK
.sym 405 w_rx_09_fifo_data[6]
.sym 406 w_rx_09_fifo_data[9]
.sym 407 w_rx_09_fifo_data[11]
.sym 408 w_rx_09_fifo_data[31]
.sym 409 w_rx_09_fifo_data[7]
.sym 410 w_rx_09_fifo_data[8]
.sym 411 w_rx_09_fifo_data[13]
.sym 412 rx_fifo.mem_q.0.1_WDATA
.sym 485 lvds_clock
.sym 492 iq_tx_n_OUTPUT_CLK
.sym 497 lvds_clock
.sym 500 $PACKER_VCC_NET
.sym 505 $PACKER_VCC_NET
.sym 514 iq_tx_n_OUTPUT_CLK
.sym 515 lvds_clock
.sym 519 rx_fifo.mem_q.0.1_WDATA_3
.sym 520 rx_fifo.mem_q.0.2_WDATA_1
.sym 521 w_rx_24_fifo_data[15]
.sym 522 w_rx_24_fifo_data[11]
.sym 523 rx_fifo.mem_q.0.2_WDATA
.sym 524 w_rx_24_fifo_data[6]
.sym 525 w_rx_24_fifo_data[13]
.sym 526 w_rx_24_fifo_data[9]
.sym 555 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 561 $PACKER_VCC_NET
.sym 633 w_rx_24_fifo_data[7]
.sym 634 w_rx_24_fifo_data[2]
.sym 636 iq_tx_n_OUTPUT_CLK
.sym 637 w_rx_24_fifo_data[5]
.sym 638 rx_fifo.mem_q.0.1_WDATA_1
.sym 639 w_rx_24_fifo_data[3]
.sym 640 w_rx_24_fifo_data[4]
.sym 679 rx_fifo.mem_q.0.1_WDATA_3
.sym 714 iq_tx_n_OUTPUT_CLK
.sym 746 w_rx_09_fifo_data[5]
.sym 747 w_rx_09_fifo_data[30]
.sym 748 w_rx_09_fifo_data[4]
.sym 749 rx_fifo.mem_q.0.0_WDATA
.sym 750 w_rx_09_fifo_data[2]
.sym 751 rx_fifo.mem_q.0.0_WDATA_2
.sym 752 w_rx_09_fifo_data[3]
.sym 753 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
.sym 766 rx_fifo.mem_i.0.3_WDATA_2
.sym 779 lvds_clock
.sym 781 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 787 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 790 smi_ctrl_ins.r_fifo_pulled_data[18]
.sym 798 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 816 iq_tx_n_OUTPUT_CLK
.sym 826 lvds_clock
.sym 829 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 830 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
.sym 851 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
.sym 861 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1]
.sym 862 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2]
.sym 863 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2]
.sym 864 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1]
.sym 865 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
.sym 866 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 867 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1]
.sym 895 rx_fifo.mem_q.0.0_WDATA
.sym 899 rx_fifo.mem_q.0.0_WDATA_2
.sym 916 w_rx_09_fifo_data[0]
.sym 917 $PACKER_VCC_NET
.sym 940 lvds_clock
.sym 941 $PACKER_VCC_NET
.sym 944 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 961 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 974 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3]
.sym 975 w_rx_24_fifo_data[1]
.sym 976 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0]
.sym 977 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2]
.sym 978 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2]
.sym 979 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[3]
.sym 980 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2]
.sym 981 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1]
.sym 982 i_sck$SB_IO_IN
.sym 994 rx_fifo.wr_addr[5]
.sym 1000 rx_fifo.wr_addr[7]
.sym 1053 rx_fifo.wr_addr[8]
.sym 1054 lvds_clock
.sym 1061 $PACKER_GND_NET
.sym 1062 $PACKER_GND_NET
.sym 1066 $PACKER_VCC_NET
.sym 1067 $PACKER_VCC_NET
.sym 1069 $PACKER_VCC_NET
.sym 1071 iq_tx_n_OUTPUT_CLK
.sym 1073 iq_tx_n_OUTPUT_CLK
.sym 1074 $PACKER_VCC_NET
.sym 1076 $PACKER_GND_NET
.sym 1080 $PACKER_VCC_NET
.sym 1084 $PACKER_GND_NET
.sym 1088 w_rx_09_fifo_data[1]
.sym 1090 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[3]
.sym 1091 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 1092 $PACKER_GND_NET
.sym 1096 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 1120 $PACKER_VCC_NET
.sym 1122 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 1132 $PACKER_VCC_NET
.sym 1138 w_lvds_rx_24_d0
.sym 1145 iq_tx_n_OUTPUT_CLK
.sym 1165 $PACKER_VCC_NET
.sym 1168 w_lvds_rx_24_d0
.sym 1169 $PACKER_VCC_NET
.sym 1173 w_lvds_rx_09_d0
.sym 1174 w_lvds_rx_09_d1
.sym 1183 $PACKER_VCC_NET
.sym 1184 lvds_clock_$glb_clk
.sym 1191 $PACKER_VCC_NET
.sym 1203 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
.sym 1204 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
.sym 1205 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2]
.sym 1208 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[1]
.sym 1209 w_lvds_rx_09_d1_SB_LUT4_I0_O[1]
.sym 1228 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
.sym 1230 rx_fifo.rd_addr_gray_wr_r[1]
.sym 1247 i_rst_b$SB_IO_IN
.sym 1262 w_lvds_rx_09_d1
.sym 1269 w_lvds_rx_09_d0
.sym 1272 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 1282 lvds_clock
.sym 1287 lvds_clock
.sym 1297 $PACKER_VCC_NET
.sym 1305 $PACKER_VCC_NET
.sym 1316 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
.sym 1317 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3
.sym 1318 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1]
.sym 1320 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 1321 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0]
.sym 1322 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[1]
.sym 1323 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 1379 $PACKER_VCC_NET
.sym 1401 w_lvds_rx_24_d0
.sym 1402 w_lvds_rx_24_d1
.sym 1411 $PACKER_VCC_NET
.sym 1412 lvds_clock_$glb_clk
.sym 1427 $PACKER_VCC_NET
.sym 1431 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0
.sym 1432 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[2]
.sym 1433 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1
.sym 1434 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[1]
.sym 1435 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E
.sym 1436 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
.sym 1437 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[3]
.sym 1474 w_lvds_rx_24_d1
.sym 1510 lvds_clock
.sym 1544 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 1545 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 1547 w_lvds_rx_09_d1_SB_LUT4_I2_O[2]
.sym 1549 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
.sym 1551 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 1569 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
.sym 1579 $PACKER_VCC_NET
.sym 1687 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 1706 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 1879 rx_fifo.mem_i.0.1_WDATA_3
.sym 1880 w_rx_09_fifo_data[20]
.sym 1881 w_rx_09_fifo_data[24]
.sym 1883 rx_fifo.mem_i.0.1_WDATA_2
.sym 1885 w_rx_09_fifo_data[22]
.sym 1886 w_rx_09_fifo_data[26]
.sym 1907 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2063 w_rx_24_fifo_data[22]
.sym 2064 rx_fifo.mem_i.0.2_WDATA_3
.sym 2065 rx_fifo.mem_q.0.3_WDATA_2
.sym 2066 w_rx_24_fifo_data[24]
.sym 2067 w_rx_24_fifo_data[14]
.sym 2068 w_rx_24_fifo_data[16]
.sym 2069 w_rx_24_fifo_data[20]
.sym 2070 rx_fifo.mem_q.0.3_WDATA_3
.sym 2094 w_rx_09_fifo_data[18]
.sym 2106 w_rx_24_fifo_data[29]
.sym 2107 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 2117 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2124 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 2128 w_rx_09_fifo_data[14]
.sym 2129 rx_fifo.mem_i.0.2_WDATA_1
.sym 2137 w_rx_09_fifo_data[10]
.sym 2162 w_rx_09_fifo_data[12]
.sym 2173 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2182 w_rx_09_fifo_data[10]
.sym 2191 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2193 w_rx_09_fifo_data[12]
.sym 2198 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2200 w_rx_09_fifo_data[10]
.sym 2231 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
.sym 2232 lvds_clock_$glb_clk
.sym 2233 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 2234 w_rx_24_fifo_data[18]
.sym 2235 w_rx_24_fifo_data[29]
.sym 2236 w_rx_24_fifo_data[25]
.sym 2237 w_rx_24_fifo_data[26]
.sym 2238 w_rx_24_fifo_data[10]
.sym 2239 w_rx_24_fifo_data[27]
.sym 2240 w_rx_24_fifo_data[12]
.sym 2241 w_rx_24_fifo_data[28]
.sym 2260 rx_fifo.wr_addr[7]
.sym 2264 w_rx_24_fifo_data[16]
.sym 2265 w_rx_09_fifo_data[19]
.sym 2269 w_rx_24_fifo_data[29]
.sym 2272 rx_fifo.mem_q.0.1_WDATA
.sym 2288 w_rx_09_fifo_data[25]
.sym 2298 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2299 w_rx_09_fifo_data[21]
.sym 2300 w_rx_09_fifo_data[27]
.sym 2305 w_rx_24_fifo_data[25]
.sym 2308 w_rx_24_fifo_data[27]
.sym 2311 w_rx_09_fifo_data[23]
.sym 2313 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 2316 w_rx_24_fifo_data[23]
.sym 2321 w_rx_09_fifo_data[21]
.sym 2322 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2328 w_rx_09_fifo_data[23]
.sym 2329 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2338 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 2339 w_rx_24_fifo_data[25]
.sym 2340 w_rx_09_fifo_data[25]
.sym 2345 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 2346 w_rx_09_fifo_data[27]
.sym 2347 w_rx_24_fifo_data[27]
.sym 2351 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2352 w_rx_09_fifo_data[25]
.sym 2357 w_rx_09_fifo_data[23]
.sym 2358 w_rx_24_fifo_data[23]
.sym 2359 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 2366 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
.sym 2367 lvds_clock_$glb_clk
.sym 2368 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 2369 w_rx_09_fifo_data[16]
.sym 2370 rx_fifo.mem_i.0.0_WDATA_3
.sym 2371 rx_fifo.mem_i.0.1_WDATA_1
.sym 2372 rx_fifo.mem_q.0.3_WDATA
.sym 2373 w_rx_09_fifo_data[28]
.sym 2374 rx_fifo.mem_q.0.2_WDATA_2
.sym 2375 rx_fifo.mem_i.0.0_WDATA_2
.sym 2376 w_rx_09_fifo_data[18]
.sym 2384 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2386 rx_fifo.wr_addr[3]
.sym 2396 w_rx_24_fifo_data[21]
.sym 2397 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 2400 w_rx_09_fifo_data[18]
.sym 2402 w_rx_24_fifo_data[23]
.sym 2405 w_rx_24_fifo_data[13]
.sym 2406 w_rx_24_fifo_data[7]
.sym 2411 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 2415 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2427 w_rx_09_fifo_data[8]
.sym 2431 w_rx_09_fifo_data[19]
.sym 2435 w_rx_09_fifo_data[27]
.sym 2436 w_rx_09_fifo_data[13]
.sym 2437 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 2439 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2442 w_rx_24_fifo_data[13]
.sym 2444 w_rx_09_fifo_data[17]
.sym 2446 w_rx_09_fifo_data[15]
.sym 2456 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2458 w_rx_09_fifo_data[13]
.sym 2462 w_rx_09_fifo_data[17]
.sym 2463 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2467 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 2469 w_rx_24_fifo_data[13]
.sym 2470 w_rx_09_fifo_data[13]
.sym 2479 w_rx_09_fifo_data[19]
.sym 2482 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2486 w_rx_09_fifo_data[27]
.sym 2487 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2492 w_rx_09_fifo_data[15]
.sym 2494 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2497 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2499 w_rx_09_fifo_data[8]
.sym 2501 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
.sym 2502 lvds_clock_$glb_clk
.sym 2503 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 2504 smi_ctrl_ins.r_fifo_pulled_data[5]
.sym 2507 rx_fifo.mem_q.0.2_WDATA_3
.sym 2508 rx_fifo.mem_i.0.3_WDATA_1
.sym 2509 rx_fifo.mem_i.0.0_WDATA_1
.sym 2510 rx_fifo.mem_q.0.1_WDATA_2
.sym 2511 rx_fifo.mem_i.0.0_WDATA
.sym 2513 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2514 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2521 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 2522 rx_fifo.mem_q.0.3_WDATA_1
.sym 2529 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 2531 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 2532 w_rx_09_fifo_data[28]
.sym 2534 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 2537 w_rx_24_fifo_data[15]
.sym 2539 w_rx_24_fifo_data[29]
.sym 2541 w_rx_09_fifo_data[5]
.sym 2545 w_rx_09_fifo_data[4]
.sym 2557 w_rx_09_fifo_data[6]
.sym 2559 w_rx_09_fifo_data[11]
.sym 2566 w_rx_09_fifo_data[9]
.sym 2570 w_rx_09_fifo_data[29]
.sym 2573 w_rx_24_fifo_data[7]
.sym 2574 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 2577 w_rx_09_fifo_data[7]
.sym 2578 w_rx_09_fifo_data[5]
.sym 2582 w_rx_09_fifo_data[4]
.sym 2587 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2590 w_rx_09_fifo_data[4]
.sym 2591 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2596 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2599 w_rx_09_fifo_data[7]
.sym 2603 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2604 w_rx_09_fifo_data[9]
.sym 2608 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2609 w_rx_09_fifo_data[29]
.sym 2615 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2617 w_rx_09_fifo_data[5]
.sym 2621 w_rx_09_fifo_data[6]
.sym 2622 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2627 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2628 w_rx_09_fifo_data[11]
.sym 2633 w_rx_24_fifo_data[7]
.sym 2634 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 2635 w_rx_09_fifo_data[7]
.sym 2636 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
.sym 2637 lvds_clock_$glb_clk
.sym 2638 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 2639 w_rx_24_fifo_data[8]
.sym 2640 w_rx_24_fifo_data[21]
.sym 2641 w_rx_24_fifo_data[30]
.sym 2642 w_rx_24_fifo_data[19]
.sym 2643 w_rx_24_fifo_data[23]
.sym 2644 rx_fifo.mem_i.0.3_WDATA
.sym 2645 w_rx_24_fifo_data[31]
.sym 2646 w_rx_24_fifo_data[17]
.sym 2650 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 2652 rx_fifo.wr_addr[0]
.sym 2658 smi_ctrl_ins.r_fifo_pulled_data[5]
.sym 2663 rx_fifo.mem_q.0.2_WDATA
.sym 2666 w_rx_09_fifo_data[28]
.sym 2667 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2668 smi_ctrl_ins.r_fifo_pulled_data[3]
.sym 2669 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 2673 rx_fifo.mem_q.0.2_WDATA_1
.sym 2686 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 2694 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 2695 w_rx_24_fifo_data[11]
.sym 2700 w_rx_24_fifo_data[7]
.sym 2701 w_rx_09_fifo_data[9]
.sym 2702 w_rx_09_fifo_data[11]
.sym 2705 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 2707 w_rx_24_fifo_data[4]
.sym 2713 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 2714 w_rx_24_fifo_data[13]
.sym 2715 w_rx_24_fifo_data[9]
.sym 2720 w_rx_09_fifo_data[4]
.sym 2725 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 2727 w_rx_24_fifo_data[4]
.sym 2728 w_rx_09_fifo_data[4]
.sym 2732 w_rx_09_fifo_data[9]
.sym 2733 w_rx_24_fifo_data[9]
.sym 2734 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 2739 w_rx_24_fifo_data[13]
.sym 2740 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 2743 w_rx_24_fifo_data[9]
.sym 2745 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 2749 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 2750 w_rx_09_fifo_data[11]
.sym 2752 w_rx_24_fifo_data[11]
.sym 2756 w_rx_24_fifo_data[4]
.sym 2757 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 2762 w_rx_24_fifo_data[11]
.sym 2764 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 2767 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 2769 w_rx_24_fifo_data[7]
.sym 2771 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 2772 lvds_clock_$glb_clk
.sym 2773 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 2775 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 2776 smi_ctrl_ins.r_fifo_pulled_data[11]
.sym 2777 rx_fifo.mem_i.0.3_WDATA_3
.sym 2778 smi_ctrl_ins.r_fifo_pulled_data[10]
.sym 2779 smi_ctrl_ins.r_fifo_pulled_data[18]
.sym 2780 smi_ctrl_ins.r_fifo_pulled_data[9]
.sym 2781 rx_fifo.mem_i.0.3_WDATA_2
.sym 2791 rx_fifo.mem_q.0.1_WDATA
.sym 2798 smi_ctrl_ins.r_fifo_pulled_data[2]
.sym 2799 rx_fifo.wr_addr[7]
.sym 2805 rx_fifo.wr_addr[6]
.sym 2807 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1]
.sym 2809 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 2813 w_rx_24_fifo_data[1]
.sym 2831 lvds_clock
.sym 2835 w_rx_09_fifo_data[5]
.sym 2836 w_rx_24_fifo_data[2]
.sym 2839 w_rx_24_fifo_data[5]
.sym 2841 w_rx_24_fifo_data[3]
.sym 2845 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 2847 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 2851 w_rx_24_fifo_data[0]
.sym 2857 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 2858 w_rx_24_fifo_data[1]
.sym 2861 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 2863 w_rx_24_fifo_data[5]
.sym 2866 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 2868 w_rx_24_fifo_data[0]
.sym 2881 lvds_clock
.sym 2885 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 2887 w_rx_24_fifo_data[3]
.sym 2890 w_rx_24_fifo_data[5]
.sym 2891 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 2892 w_rx_09_fifo_data[5]
.sym 2897 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 2898 w_rx_24_fifo_data[1]
.sym 2903 w_rx_24_fifo_data[2]
.sym 2904 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 2906 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 2907 lvds_clock_$glb_clk
.sym 2908 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 2909 smi_ctrl_ins.r_fifo_pulled_data[0]
.sym 2911 smi_ctrl_ins.r_fifo_pulled_data[3]
.sym 2914 smi_ctrl_ins.r_fifo_pulled_data[1]
.sym 2915 smi_ctrl_ins.r_fifo_pulled_data[2]
.sym 2922 smi_ctrl_ins.r_fifo_pulled_data[9]
.sym 2926 rx_fifo.wr_addr[4]
.sym 2929 iq_tx_n_OUTPUT_CLK
.sym 2930 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 2936 iq_tx_n_OUTPUT_CLK
.sym 2937 w_rx_24_fifo_data[0]
.sym 2940 rx_fifo.mem_q.0.1_WDATA_1
.sym 2946 w_rx_09_fifo_data[1]
.sym 2947 rx_fifo.wr_addr[4]
.sym 2954 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
.sym 2955 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 2968 w_rx_24_fifo_data[3]
.sym 2971 w_rx_24_fifo_data[2]
.sym 2972 w_rx_09_fifo_data[28]
.sym 2974 w_rx_09_fifo_data[2]
.sym 2976 w_rx_09_fifo_data[3]
.sym 2977 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 2981 w_rx_09_fifo_data[0]
.sym 2983 w_rx_09_fifo_data[1]
.sym 2987 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 2990 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 2996 w_rx_09_fifo_data[3]
.sym 2997 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3001 w_rx_09_fifo_data[28]
.sym 3002 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3007 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3010 w_rx_09_fifo_data[2]
.sym 3013 w_rx_09_fifo_data[3]
.sym 3014 w_rx_24_fifo_data[3]
.sym 3016 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 3020 w_rx_09_fifo_data[0]
.sym 3021 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3026 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 3027 w_rx_09_fifo_data[2]
.sym 3028 w_rx_24_fifo_data[2]
.sym 3032 w_rx_09_fifo_data[1]
.sym 3033 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3039 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 3041 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
.sym 3042 lvds_clock_$glb_clk
.sym 3043 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 3044 rx_fifo.wr_addr[7]
.sym 3045 rx_fifo.mem_q.0.0_WDATA_3
.sym 3046 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2]
.sym 3047 rx_fifo.wr_addr[6]
.sym 3048 rx_fifo.wr_addr[1]
.sym 3049 rx_fifo.wr_addr[2]
.sym 3050 rx_fifo.mem_q.0.0_WDATA_1
.sym 3051 rx_fifo.wr_addr[5]
.sym 3057 $PACKER_VCC_NET
.sym 3061 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 3068 w_rx_09_fifo_data[1]
.sym 3073 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
.sym 3074 rx_fifo.wr_addr[9]
.sym 3076 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 3078 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
.sym 3086 $PACKER_VCC_NET
.sym 3101 rx_fifo.wr_addr[8]
.sym 3106 rx_fifo.wr_addr[3]
.sym 3113 rx_fifo.wr_addr[7]
.sym 3116 rx_fifo.wr_addr[6]
.sym 3117 rx_fifo.wr_addr[1]
.sym 3124 rx_fifo.wr_addr[4]
.sym 3126 rx_fifo.wr_addr[2]
.sym 3128 rx_fifo.wr_addr[5]
.sym 3129 $nextpnr_ICESTORM_LC_0$O
.sym 3132 rx_fifo.wr_addr[1]
.sym 3135 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3
.sym 3137 rx_fifo.wr_addr[2]
.sym 3139 rx_fifo.wr_addr[1]
.sym 3141 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2_SB_LUT4_O_I3
.sym 3144 rx_fifo.wr_addr[3]
.sym 3145 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3
.sym 3147 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_O_I3
.sym 3149 rx_fifo.wr_addr[4]
.sym 3151 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2_SB_LUT4_O_I3
.sym 3153 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 3156 rx_fifo.wr_addr[5]
.sym 3157 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_O_I3
.sym 3159 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 3162 rx_fifo.wr_addr[6]
.sym 3163 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 3165 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 3168 rx_fifo.wr_addr[7]
.sym 3169 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 3171 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3
.sym 3173 rx_fifo.wr_addr[8]
.sym 3175 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 3179 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0]
.sym 3180 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 3181 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 3182 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
.sym 3183 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1]
.sym 3184 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3]
.sym 3185 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
.sym 3186 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[3]
.sym 3191 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 3192 rx_fifo.wr_addr[3]
.sym 3193 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 3194 rx_fifo.wr_addr[6]
.sym 3195 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 3196 rx_fifo.wr_addr[5]
.sym 3198 rx_fifo.wr_addr[7]
.sym 3200 rx_fifo.wr_addr[0]
.sym 3201 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 3208 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1]
.sym 3210 w_rx_09_fifo_data[0]
.sym 3211 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3212 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 3214 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 3224 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 3227 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3
.sym 3232 rx_fifo.rd_addr_gray_wr_r[7]
.sym 3233 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1]
.sym 3234 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2]
.sym 3235 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2]
.sym 3237 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
.sym 3238 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 3242 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[3]
.sym 3245 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
.sym 3246 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 3247 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1]
.sym 3248 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0]
.sym 3250 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 3254 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2]
.sym 3255 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1]
.sym 3257 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
.sym 3258 rx_fifo.wr_addr[9]
.sym 3260 w_lvds_rx_24_d0
.sym 3261 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[3]
.sym 3266 rx_fifo.wr_addr[9]
.sym 3268 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3
.sym 3273 w_lvds_rx_24_d0
.sym 3277 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
.sym 3278 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 3279 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 3280 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[3]
.sym 3284 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2]
.sym 3285 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1]
.sym 3286 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0]
.sym 3289 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 3291 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
.sym 3292 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 3295 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1]
.sym 3296 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2]
.sym 3298 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
.sym 3301 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1]
.sym 3302 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 3303 rx_fifo.rd_addr_gray_wr_r[7]
.sym 3307 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
.sym 3308 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2]
.sym 3309 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2]
.sym 3310 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[3]
.sym 3311 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 3312 lvds_clock_$glb_clk
.sym 3314 rx_fifo.full_o_SB_LUT4_I0_O[1]
.sym 3315 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2]
.sym 3316 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
.sym 3317 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1]
.sym 3318 rx_fifo.rd_addr_gray_wr[0]
.sym 3319 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
.sym 3320 rx_fifo.full_o_SB_LUT4_I0_O[2]
.sym 3321 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3]
.sym 3326 rx_fifo.rd_addr_gray_wr_r[7]
.sym 3327 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
.sym 3330 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
.sym 3332 rx_fifo.rd_addr_gray_wr_r[4]
.sym 3337 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 3339 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 3341 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 3342 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1]
.sym 3343 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 3345 rx_fifo.rd_addr_gray[5]
.sym 3349 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 3375 w_lvds_rx_09_d0
.sym 3382 w_lvds_rx_09_d1_SB_LUT4_I0_O[1]
.sym 3384 i_rst_b$SB_IO_IN
.sym 3392 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1]
.sym 3396 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
.sym 3401 w_lvds_rx_09_d0
.sym 3412 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
.sym 3414 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1]
.sym 3419 w_lvds_rx_09_d1_SB_LUT4_I0_O[1]
.sym 3420 i_rst_b$SB_IO_IN
.sym 3446 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
.sym 3447 lvds_clock_$glb_clk
.sym 3449 rx_fifo.rd_addr_gray_wr[9]
.sym 3451 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
.sym 3453 rx_fifo.rd_addr_gray_wr[5]
.sym 3454 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
.sym 3464 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 3465 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 3466 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
.sym 3467 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 3468 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
.sym 3469 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 3472 rx_fifo.rd_addr_gray[0]
.sym 3475 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 3477 w_rx_fifo_full
.sym 3481 w_rx_24_fifo_data[0]
.sym 3484 rx_fifo.rd_addr[9]
.sym 3488 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3496 w_lvds_rx_09_d0
.sym 3505 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 3509 $PACKER_VCC_NET
.sym 3511 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3
.sym 3516 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[1]
.sym 3517 $PACKER_VCC_NET
.sym 3519 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
.sym 3520 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
.sym 3522 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 3523 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 3526 w_lvds_rx_09_d0
.sym 3529 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 3531 w_lvds_rx_09_d1
.sym 3533 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3534 $nextpnr_ICESTORM_LC_1$O
.sym 3537 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3
.sym 3540 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 3541 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 3542 $PACKER_VCC_NET
.sym 3543 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[1]
.sym 3544 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3
.sym 3547 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 3548 $PACKER_VCC_NET
.sym 3549 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
.sym 3550 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 3553 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
.sym 3556 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
.sym 3572 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
.sym 3577 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 3578 w_lvds_rx_09_d1
.sym 3579 w_lvds_rx_09_d0
.sym 3580 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3581 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 3582 lvds_clock_$glb_clk
.sym 3583 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 3585 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
.sym 3586 w_rx_24_fifo_data[0]
.sym 3590 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0]
.sym 3601 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 3608 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 3610 w_lvds_rx_09_d1
.sym 3619 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 3622 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 3638 w_lvds_rx_24_d1
.sym 3639 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 3640 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2]
.sym 3641 w_lvds_rx_24_d0
.sym 3648 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2]
.sym 3649 w_lvds_rx_24_d0
.sym 3651 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[1]
.sym 3652 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 3658 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0]
.sym 3659 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 3667 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0]
.sym 3668 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 3670 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 3671 w_lvds_rx_24_d1
.sym 3672 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 3673 w_lvds_rx_24_d0
.sym 3676 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0]
.sym 3682 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 3683 w_lvds_rx_24_d1
.sym 3684 w_lvds_rx_24_d0
.sym 3695 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0]
.sym 3697 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[1]
.sym 3700 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2]
.sym 3701 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 3702 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0]
.sym 3703 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 3706 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 3707 w_lvds_rx_24_d1
.sym 3708 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 3709 w_lvds_rx_24_d0
.sym 3713 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 3714 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0]
.sym 3715 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2]
.sym 3716 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 3717 lvds_clock_$glb_clk
.sym 3718 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 3721 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 3722 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 3725 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 3726 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 3732 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0]
.sym 3735 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 3745 w_rx_09_fifo_data[0]
.sym 3750 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3773 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3774 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E
.sym 3775 w_lvds_rx_09_d1_SB_LUT4_I2_O[2]
.sym 3778 $PACKER_VCC_NET
.sym 3779 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 3781 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3783 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1
.sym 3787 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[3]
.sym 3794 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
.sym 3797 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0
.sym 3798 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[2]
.sym 3800 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[1]
.sym 3804 $nextpnr_ICESTORM_LC_6$O
.sym 3807 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[3]
.sym 3810 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I1_I3
.sym 3811 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3812 $PACKER_VCC_NET
.sym 3813 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[1]
.sym 3814 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[3]
.sym 3817 $PACKER_VCC_NET
.sym 3818 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[2]
.sym 3819 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3820 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I1_I3
.sym 3823 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3824 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
.sym 3825 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 3826 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1
.sym 3831 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0
.sym 3835 w_lvds_rx_09_d1_SB_LUT4_I2_O[2]
.sym 3836 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
.sym 3837 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 3838 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3841 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1
.sym 3842 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3843 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0
.sym 3844 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[2]
.sym 3850 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1
.sym 3851 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E
.sym 3852 lvds_clock_$glb_clk
.sym 3853 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 3859 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 3861 w_rx_09_fifo_data[0]
.sym 3868 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E
.sym 3869 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 3886 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 3917 w_lvds_rx_09_d0
.sym 3918 w_lvds_rx_09_d1
.sym 3924 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3925 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 3928 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
.sym 3934 w_lvds_rx_09_d1_SB_LUT4_I2_O[2]
.sym 3938 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 3940 w_lvds_rx_09_d1
.sym 3941 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3942 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 3943 w_lvds_rx_09_d0
.sym 3946 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3948 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
.sym 3958 w_lvds_rx_09_d0
.sym 3961 w_lvds_rx_09_d1
.sym 3970 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 3971 w_lvds_rx_09_d1_SB_LUT4_I2_O[2]
.sym 3973 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 3982 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
.sym 3986 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 3987 lvds_clock_$glb_clk
.sym 3988 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 4019 o_shdn_tx_lna$SB_IO_OUT
.sym 4024 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 4238 w_rx_fifo_pulled_data[20]
.sym 4242 w_rx_fifo_pulled_data[22]
.sym 4254 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4255 w_rx_09_fifo_data[0]
.sym 4279 w_rx_24_fifo_data[22]
.sym 4285 w_rx_24_fifo_data[20]
.sym 4286 w_rx_09_fifo_data[18]
.sym 4288 w_rx_09_fifo_data[20]
.sym 4289 w_rx_09_fifo_data[24]
.sym 4296 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4299 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 4309 w_rx_09_fifo_data[22]
.sym 4312 w_rx_09_fifo_data[20]
.sym 4313 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4314 w_rx_24_fifo_data[20]
.sym 4320 w_rx_09_fifo_data[18]
.sym 4321 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 4324 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 4325 w_rx_09_fifo_data[22]
.sym 4337 w_rx_09_fifo_data[22]
.sym 4338 w_rx_24_fifo_data[22]
.sym 4339 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4348 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 4350 w_rx_09_fifo_data[20]
.sym 4355 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 4356 w_rx_09_fifo_data[24]
.sym 4358 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
.sym 4359 lvds_clock_$glb_clk
.sym 4360 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 4366 w_rx_fifo_pulled_data[21]
.sym 4370 w_rx_fifo_pulled_data[23]
.sym 4376 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2]
.sym 4382 rx_fifo.wr_addr[7]
.sym 4390 rx_fifo.wr_addr[1]
.sym 4400 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 4406 rx_fifo.rd_addr[2]
.sym 4408 rx_fifo.mem_q.0.3_WDATA_3
.sym 4411 rx_fifo.rd_addr[1]
.sym 4413 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 4414 w_rx_09_fifo_data[26]
.sym 4416 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 4417 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 4418 rx_fifo.wr_addr[2]
.sym 4422 w_rx_24_fifo_data[28]
.sym 4424 rx_fifo.mem_i.0.1_WDATA_1
.sym 4428 rx_fifo.wr_addr[5]
.sym 4429 $PACKER_VCC_NET
.sym 4431 w_rx_09_fifo_data[26]
.sym 4432 rx_fifo.wr_addr[2]
.sym 4442 w_rx_24_fifo_data[22]
.sym 4444 w_rx_09_fifo_data[12]
.sym 4448 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4450 w_rx_24_fifo_data[18]
.sym 4451 w_rx_09_fifo_data[14]
.sym 4452 w_rx_09_fifo_data[24]
.sym 4453 w_rx_24_fifo_data[24]
.sym 4454 w_rx_24_fifo_data[14]
.sym 4456 w_rx_24_fifo_data[12]
.sym 4464 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4469 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 4472 w_rx_24_fifo_data[20]
.sym 4475 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4476 w_rx_24_fifo_data[20]
.sym 4481 w_rx_09_fifo_data[24]
.sym 4482 w_rx_24_fifo_data[24]
.sym 4484 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4487 w_rx_09_fifo_data[14]
.sym 4488 w_rx_24_fifo_data[14]
.sym 4489 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4494 w_rx_24_fifo_data[22]
.sym 4496 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4499 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4502 w_rx_24_fifo_data[12]
.sym 4506 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4507 w_rx_24_fifo_data[14]
.sym 4511 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4514 w_rx_24_fifo_data[18]
.sym 4518 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4519 w_rx_24_fifo_data[12]
.sym 4520 w_rx_09_fifo_data[12]
.sym 4521 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 4522 lvds_clock_$glb_clk
.sym 4523 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 4525 w_rx_fifo_pulled_data[24]
.sym 4529 w_rx_fifo_pulled_data[26]
.sym 4541 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 4542 rx_fifo.mem_q.0.3_WDATA_2
.sym 4544 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 4549 rx_fifo.mem_i.0.0_WDATA_2
.sym 4550 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 4551 rx_fifo.wr_addr[2]
.sym 4552 rx_fifo.wr_addr[1]
.sym 4553 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4554 rx_fifo.wr_addr[6]
.sym 4555 rx_fifo.mem_i.0.0_WDATA_3
.sym 4559 rx_fifo.wr_addr[6]
.sym 4567 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 4568 w_rx_24_fifo_data[24]
.sym 4570 w_rx_24_fifo_data[16]
.sym 4578 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4583 w_rx_24_fifo_data[25]
.sym 4585 w_rx_24_fifo_data[8]
.sym 4586 w_rx_24_fifo_data[23]
.sym 4592 w_rx_24_fifo_data[26]
.sym 4593 w_rx_24_fifo_data[10]
.sym 4594 w_rx_24_fifo_data[27]
.sym 4598 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4599 w_rx_24_fifo_data[16]
.sym 4605 w_rx_24_fifo_data[27]
.sym 4607 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4612 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4613 w_rx_24_fifo_data[23]
.sym 4618 w_rx_24_fifo_data[24]
.sym 4619 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4622 w_rx_24_fifo_data[8]
.sym 4624 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4629 w_rx_24_fifo_data[25]
.sym 4631 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4634 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4637 w_rx_24_fifo_data[10]
.sym 4641 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4643 w_rx_24_fifo_data[26]
.sym 4644 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 4645 lvds_clock_$glb_clk
.sym 4646 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 4648 w_rx_fifo_pulled_data[25]
.sym 4652 w_rx_fifo_pulled_data[27]
.sym 4663 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 4666 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4667 w_rx_24_fifo_data[26]
.sym 4671 w_rx_24_fifo_data[8]
.sym 4672 rx_fifo.wr_addr[7]
.sym 4674 rx_fifo.mem_i.0.0_WDATA
.sym 4676 $PACKER_VCC_NET
.sym 4678 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 4679 $PACKER_VCC_NET
.sym 4680 rx_fifo.mem_q.0.1_WDATA_3
.sym 4682 w_rx_24_fifo_data[28]
.sym 4688 w_rx_24_fifo_data[18]
.sym 4690 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 4692 w_rx_24_fifo_data[10]
.sym 4695 w_rx_09_fifo_data[10]
.sym 4696 w_rx_09_fifo_data[15]
.sym 4698 w_rx_24_fifo_data[16]
.sym 4699 w_rx_09_fifo_data[14]
.sym 4700 w_rx_09_fifo_data[21]
.sym 4706 w_rx_09_fifo_data[26]
.sym 4711 w_rx_09_fifo_data[18]
.sym 4712 w_rx_09_fifo_data[16]
.sym 4713 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4714 w_rx_24_fifo_data[21]
.sym 4717 w_rx_24_fifo_data[15]
.sym 4721 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 4723 w_rx_09_fifo_data[14]
.sym 4727 w_rx_09_fifo_data[16]
.sym 4729 w_rx_24_fifo_data[16]
.sym 4730 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4733 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4734 w_rx_09_fifo_data[21]
.sym 4736 w_rx_24_fifo_data[21]
.sym 4740 w_rx_24_fifo_data[15]
.sym 4741 w_rx_09_fifo_data[15]
.sym 4742 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4745 w_rx_09_fifo_data[26]
.sym 4747 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 4752 w_rx_24_fifo_data[10]
.sym 4753 w_rx_09_fifo_data[10]
.sym 4754 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4757 w_rx_24_fifo_data[18]
.sym 4759 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4760 w_rx_09_fifo_data[18]
.sym 4764 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 4765 w_rx_09_fifo_data[16]
.sym 4767 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
.sym 4768 lvds_clock_$glb_clk
.sym 4769 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 4771 w_rx_fifo_pulled_data[4]
.sym 4775 w_rx_fifo_pulled_data[6]
.sym 4784 rx_fifo.mem_i.0.2_WDATA_1
.sym 4785 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 4788 smi_ctrl_ins.r_fifo_pulled_data[3]
.sym 4789 rx_fifo.rd_addr[2]
.sym 4790 rx_fifo.mem_q.0.3_WDATA
.sym 4792 w_rx_09_fifo_data[28]
.sym 4794 rx_fifo.wr_addr[1]
.sym 4795 rx_fifo.mem_i.0.2_WDATA
.sym 4796 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 4797 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 4798 smi_ctrl_ins.r_fifo_pulled_data[11]
.sym 4799 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4800 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 4801 rx_fifo.mem_q.0.2_WDATA_2
.sym 4802 rx_fifo.rd_addr[1]
.sym 4803 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 4804 rx_fifo.wr_addr[2]
.sym 4805 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 4811 w_rx_24_fifo_data[8]
.sym 4816 w_rx_09_fifo_data[8]
.sym 4818 w_rx_24_fifo_data[17]
.sym 4819 w_rx_09_fifo_data[6]
.sym 4821 w_rx_24_fifo_data[29]
.sym 4822 w_rx_24_fifo_data[19]
.sym 4823 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4825 w_rx_09_fifo_data[19]
.sym 4828 w_rx_fifo_pulled_data[5]
.sym 4832 w_rx_09_fifo_data[29]
.sym 4833 w_rx_09_fifo_data[17]
.sym 4836 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4840 w_rx_24_fifo_data[6]
.sym 4845 w_rx_fifo_pulled_data[5]
.sym 4862 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4863 w_rx_24_fifo_data[8]
.sym 4864 w_rx_09_fifo_data[8]
.sym 4869 w_rx_24_fifo_data[29]
.sym 4870 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4871 w_rx_09_fifo_data[29]
.sym 4874 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4876 w_rx_24_fifo_data[17]
.sym 4877 w_rx_09_fifo_data[17]
.sym 4881 w_rx_09_fifo_data[6]
.sym 4882 w_rx_24_fifo_data[6]
.sym 4883 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4886 w_rx_09_fifo_data[19]
.sym 4887 w_rx_24_fifo_data[19]
.sym 4888 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4890 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
.sym 4891 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 4892 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 4894 w_rx_fifo_pulled_data[5]
.sym 4898 w_rx_fifo_pulled_data[7]
.sym 4906 smi_ctrl_ins.r_fifo_pulled_data[2]
.sym 4907 rx_fifo.mem_i.0.0_WDATA_1
.sym 4908 rx_fifo.wr_addr[6]
.sym 4910 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 4912 rx_fifo.wr_addr[7]
.sym 4915 rx_fifo.mem_i.0.3_WDATA_1
.sym 4920 rx_fifo.mem_q.0.2_WDATA_3
.sym 4924 rx_fifo.wr_addr[5]
.sym 4928 w_rx_24_fifo_data[28]
.sym 4936 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 4937 w_rx_24_fifo_data[19]
.sym 4939 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4941 w_rx_24_fifo_data[17]
.sym 4943 w_rx_24_fifo_data[21]
.sym 4944 w_rx_24_fifo_data[15]
.sym 4947 w_rx_24_fifo_data[6]
.sym 4948 w_rx_24_fifo_data[31]
.sym 4949 w_rx_24_fifo_data[29]
.sym 4952 w_rx_24_fifo_data[28]
.sym 4961 w_rx_09_fifo_data[31]
.sym 4964 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4969 w_rx_24_fifo_data[6]
.sym 4970 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4973 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4975 w_rx_24_fifo_data[19]
.sym 4980 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4981 w_rx_24_fifo_data[28]
.sym 4985 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4987 w_rx_24_fifo_data[17]
.sym 4991 w_rx_24_fifo_data[21]
.sym 4994 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 4997 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 4999 w_rx_24_fifo_data[31]
.sym 5000 w_rx_09_fifo_data[31]
.sym 5003 w_rx_24_fifo_data[29]
.sym 5004 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 5009 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 5011 w_rx_24_fifo_data[15]
.sym 5013 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 5014 lvds_clock_$glb_clk
.sym 5015 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
.sym 5017 w_rx_fifo_pulled_data[8]
.sym 5021 w_rx_fifo_pulled_data[10]
.sym 5030 rx_fifo.mem_i.0.3_WDATA
.sym 5036 rx_fifo.mem_q.0.1_WDATA_1
.sym 5040 smi_ctrl_ins.r_fifo_pulled_data[10]
.sym 5041 $PACKER_VCC_NET
.sym 5046 rx_fifo.wr_addr[6]
.sym 5048 rx_fifo.wr_addr[1]
.sym 5050 rx_fifo.wr_addr[2]
.sym 5051 i_rst_b$SB_IO_IN
.sym 5066 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 5067 w_rx_24_fifo_data[30]
.sym 5068 w_rx_fifo_pulled_data[18]
.sym 5069 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 5070 w_rx_09_fifo_data[28]
.sym 5074 w_rx_fifo_pulled_data[9]
.sym 5075 i_rst_b$SB_IO_IN
.sym 5078 w_rx_fifo_pulled_data[10]
.sym 5081 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1]
.sym 5082 w_rx_09_fifo_data[30]
.sym 5086 w_rx_fifo_pulled_data[11]
.sym 5088 w_rx_24_fifo_data[28]
.sym 5096 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1]
.sym 5097 i_rst_b$SB_IO_IN
.sym 5099 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 5102 w_rx_fifo_pulled_data[11]
.sym 5109 w_rx_09_fifo_data[28]
.sym 5110 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 5111 w_rx_24_fifo_data[28]
.sym 5115 w_rx_fifo_pulled_data[10]
.sym 5121 w_rx_fifo_pulled_data[18]
.sym 5127 w_rx_fifo_pulled_data[9]
.sym 5132 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 5134 w_rx_24_fifo_data[30]
.sym 5135 w_rx_09_fifo_data[30]
.sym 5136 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
.sym 5137 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 5138 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 5140 w_rx_fifo_pulled_data[9]
.sym 5144 w_rx_fifo_pulled_data[11]
.sym 5147 rx_fifo.wr_addr[8]
.sym 5154 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
.sym 5155 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 5156 w_rx_fifo_pulled_data[18]
.sym 5159 rx_fifo.mem_i.0.3_WDATA_3
.sym 5162 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 5163 rx_fifo.rd_addr[9]
.sym 5165 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 5166 w_rx_fifo_pulled_data[1]
.sym 5168 rx_fifo.wr_addr[7]
.sym 5169 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
.sym 5171 smi_ctrl_ins.r_fifo_pulled_data[0]
.sym 5173 rx_fifo.rd_addr[0]
.sym 5174 w_rx_fifo_pulled_data[3]
.sym 5182 w_rx_fifo_pulled_data[1]
.sym 5198 w_rx_fifo_pulled_data[3]
.sym 5201 w_rx_fifo_pulled_data[2]
.sym 5205 w_rx_fifo_pulled_data[0]
.sym 5215 w_rx_fifo_pulled_data[0]
.sym 5227 w_rx_fifo_pulled_data[3]
.sym 5246 w_rx_fifo_pulled_data[1]
.sym 5252 w_rx_fifo_pulled_data[2]
.sym 5259 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
.sym 5260 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 5261 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 5263 w_rx_fifo_pulled_data[0]
.sym 5267 w_rx_fifo_pulled_data[2]
.sym 5275 rx_fifo.mem_q.0.2_WDATA
.sym 5276 smi_ctrl_ins.r_fifo_pulled_data[1]
.sym 5277 rx_fifo.mem_q.0.2_WDATA_1
.sym 5278 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5280 rx_fifo.rd_addr[2]
.sym 5281 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 5282 rx_fifo.rd_addr[1]
.sym 5283 $PACKER_VCC_NET
.sym 5286 rx_fifo.wr_addr[1]
.sym 5287 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 5288 rx_fifo.wr_addr[2]
.sym 5289 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 5292 rx_fifo.wr_addr[5]
.sym 5293 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 5294 rx_fifo.rd_addr[1]
.sym 5295 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 5296 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 5303 w_rx_24_fifo_data[0]
.sym 5308 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5310 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 5312 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 5313 rx_fifo.wr_addr[0]
.sym 5314 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
.sym 5316 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 5320 w_rx_24_fifo_data[1]
.sym 5321 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2]
.sym 5323 rx_fifo.wr_addr[1]
.sym 5328 w_rx_09_fifo_data[1]
.sym 5329 w_rx_09_fifo_data[0]
.sym 5332 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5337 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 5342 w_rx_09_fifo_data[0]
.sym 5343 w_rx_24_fifo_data[0]
.sym 5345 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 5349 rx_fifo.wr_addr[0]
.sym 5350 rx_fifo.wr_addr[1]
.sym 5355 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 5360 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2]
.sym 5366 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5372 w_rx_09_fifo_data[1]
.sym 5373 w_rx_24_fifo_data[1]
.sym 5374 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 5381 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5382 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
.sym 5383 lvds_clock_$glb_clk
.sym 5384 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 5386 w_rx_fifo_pulled_data[1]
.sym 5390 w_rx_fifo_pulled_data[3]
.sym 5394 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 5397 rx_fifo.rd_addr_gray[5]
.sym 5399 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 5405 rx_fifo.wr_addr[6]
.sym 5407 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 5411 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5413 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
.sym 5414 rx_fifo.wr_addr[1]
.sym 5415 rx_fifo.mem_q.0.0_WDATA_2
.sym 5416 rx_fifo.wr_addr[2]
.sym 5417 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5418 $PACKER_VCC_NET
.sym 5420 rx_fifo.wr_addr[5]
.sym 5428 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0]
.sym 5429 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2]
.sym 5430 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 5433 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3]
.sym 5434 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3]
.sym 5435 rx_fifo.rd_addr_gray_wr_r[4]
.sym 5436 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2]
.sym 5437 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1]
.sym 5438 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2]
.sym 5439 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
.sym 5441 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
.sym 5443 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5446 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1]
.sym 5447 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 5449 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2]
.sym 5451 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 5452 i_rst_b$SB_IO_IN
.sym 5453 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2]
.sym 5454 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1]
.sym 5455 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3]
.sym 5457 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1]
.sym 5459 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2]
.sym 5461 rx_fifo.rd_addr_gray_wr_r[4]
.sym 5462 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1]
.sym 5465 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2]
.sym 5467 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 5468 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 5472 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2]
.sym 5474 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5479 i_rst_b$SB_IO_IN
.sym 5480 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 5483 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3]
.sym 5484 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2]
.sym 5485 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
.sym 5486 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3]
.sym 5490 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
.sym 5492 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1]
.sym 5495 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0]
.sym 5496 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2]
.sym 5497 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1]
.sym 5498 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3]
.sym 5501 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3]
.sym 5502 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
.sym 5503 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2]
.sym 5504 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1]
.sym 5518 w_rx_09_fifo_data[0]
.sym 5524 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 5526 rx_fifo.rd_addr[9]
.sym 5527 w_rx_fifo_full
.sym 5528 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 5530 rx_fifo.rd_addr[2]
.sym 5536 rx_fifo.full_o_SB_LUT4_I0_O[0]
.sym 5538 i_rst_b$SB_IO_IN
.sym 5542 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2]
.sym 5549 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
.sym 5550 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 5551 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
.sym 5553 rx_fifo.rd_addr_gray[0]
.sym 5556 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[3]
.sym 5557 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
.sym 5558 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 5559 rx_fifo.rd_addr_gray_wr_r[1]
.sym 5561 rx_fifo.rd_addr_gray_wr[0]
.sym 5562 rx_fifo.full_o_SB_LUT4_I0_O[0]
.sym 5563 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
.sym 5564 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 5565 rx_fifo.full_o_SB_LUT4_I0_O[1]
.sym 5568 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1]
.sym 5569 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 5571 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5573 w_rx_fifo_full
.sym 5574 rx_fifo.wr_addr[1]
.sym 5575 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 5576 rx_fifo.wr_addr[2]
.sym 5577 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 5579 rx_fifo.full_o_SB_LUT4_I0_O[2]
.sym 5582 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
.sym 5583 w_rx_fifo_full
.sym 5584 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 5585 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 5588 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
.sym 5589 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 5591 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 5594 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
.sym 5595 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 5596 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 5597 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
.sym 5600 rx_fifo.rd_addr_gray_wr[0]
.sym 5606 rx_fifo.rd_addr_gray[0]
.sym 5613 rx_fifo.full_o_SB_LUT4_I0_O[0]
.sym 5614 rx_fifo.full_o_SB_LUT4_I0_O[2]
.sym 5615 rx_fifo.full_o_SB_LUT4_I0_O[1]
.sym 5618 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
.sym 5619 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 5620 rx_fifo.wr_addr[1]
.sym 5621 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1]
.sym 5624 rx_fifo.rd_addr_gray_wr_r[1]
.sym 5625 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 5626 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[3]
.sym 5627 rx_fifo.wr_addr[2]
.sym 5629 lvds_clock_$glb_clk
.sym 5645 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
.sym 5646 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
.sym 5647 rx_fifo.wr_addr[9]
.sym 5649 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
.sym 5651 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
.sym 5656 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
.sym 5657 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
.sym 5661 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
.sym 5680 rx_fifo.rd_addr_gray_wr[9]
.sym 5683 rx_fifo.rd_addr_gray[5]
.sym 5684 rx_fifo.rd_addr_gray_wr[5]
.sym 5690 rx_fifo.rd_addr[9]
.sym 5707 rx_fifo.rd_addr[9]
.sym 5720 rx_fifo.rd_addr_gray_wr[9]
.sym 5731 rx_fifo.rd_addr_gray[5]
.sym 5735 rx_fifo.rd_addr_gray_wr[5]
.sym 5752 lvds_clock_$glb_clk
.sym 5782 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 5797 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 5801 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 5802 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 5809 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 5810 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 5812 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
.sym 5813 w_lvds_rx_24_d1
.sym 5834 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 5837 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 5840 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 5841 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
.sym 5842 w_lvds_rx_24_d1
.sym 5865 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 5867 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 5874 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 5875 lvds_clock_$glb_clk
.sym 5885 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2]
.sym 5893 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
.sym 5920 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 5924 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 5937 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 5941 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 5942 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
.sym 5944 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1]
.sym 5964 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 5966 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 5969 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1]
.sym 5972 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 5988 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
.sym 5989 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 5995 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
.sym 5997 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
.sym 5998 lvds_clock_$glb_clk
.sym 5999 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 6013 o_shdn_tx_lna$SB_IO_OUT
.sym 6014 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 6017 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 6044 w_lvds_rx_09_d1
.sym 6049 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 6054 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 6056 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 6071 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
.sym 6104 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
.sym 6106 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 6116 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
.sym 6117 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 6118 w_lvds_rx_09_d1
.sym 6119 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 6120 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
.sym 6121 lvds_clock_$glb_clk
.sym 6262 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 6294 o_shdn_tx_lna$SB_IO_OUT
.sym 6310 o_shdn_tx_lna$SB_IO_OUT
.sym 6346 tx_fifo.rd_addr_gray_wr[3]
.sym 6347 tx_fifo.rd_addr_gray_wr[2]
.sym 6348 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 6349 tx_fifo.rd_addr_gray_wr[5]
.sym 6350 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
.sym 6351 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 6352 tx_fifo.rd_addr_gray_wr[6]
.sym 6386 rx_fifo.mem_i.0.1_WDATA_3
.sym 6390 rx_fifo.mem_i.0.1_WDATA_2
.sym 6392 rx_fifo.wr_addr[4]
.sym 6395 rx_fifo.wr_addr[1]
.sym 6397 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 6398 rx_fifo.wr_addr[3]
.sym 6399 rx_fifo.wr_addr[2]
.sym 6400 rx_fifo.wr_addr[7]
.sym 6401 rx_fifo.wr_addr[6]
.sym 6403 rx_fifo.wr_addr[9]
.sym 6406 rx_fifo.wr_addr[8]
.sym 6414 rx_fifo.wr_addr[5]
.sym 6415 $PACKER_VCC_NET
.sym 6416 rx_fifo.wr_addr[0]
.sym 6422 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
.sym 6423 smi_ctrl_ins.r_fifo_pulled_data[13]
.sym 6424 smi_ctrl_ins.r_fifo_pulled_data[26]
.sym 6425 smi_ctrl_ins.r_fifo_pulled_data[15]
.sym 6426 smi_ctrl_ins.r_fifo_pulled_data[23]
.sym 6427 smi_ctrl_ins.r_fifo_pulled_data[21]
.sym 6428 smi_ctrl_ins.r_fifo_pulled_data[20]
.sym 6429 smi_ctrl_ins.r_fifo_pulled_data[22]
.sym 6438 rx_fifo.wr_addr[2]
.sym 6439 rx_fifo.wr_addr[3]
.sym 6441 rx_fifo.wr_addr[4]
.sym 6442 rx_fifo.wr_addr[5]
.sym 6443 rx_fifo.wr_addr[6]
.sym 6444 rx_fifo.wr_addr[7]
.sym 6445 rx_fifo.wr_addr[8]
.sym 6446 rx_fifo.wr_addr[9]
.sym 6447 rx_fifo.wr_addr[1]
.sym 6448 rx_fifo.wr_addr[0]
.sym 6449 lvds_clock_$glb_clk
.sym 6450 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 6452 rx_fifo.mem_i.0.1_WDATA_3
.sym 6456 rx_fifo.mem_i.0.1_WDATA_2
.sym 6459 $PACKER_VCC_NET
.sym 6473 rx_fifo.wr_addr[6]
.sym 6481 rx_fifo.rd_addr[0]
.sym 6487 rx_fifo.rd_addr[5]
.sym 6490 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 6493 rx_fifo.rd_addr[9]
.sym 6494 rx_fifo.mem_i.0.1_WDATA
.sym 6495 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 6497 rx_fifo.wr_addr[3]
.sym 6498 smi_ctrl_ins.r_fifo_pulled_data[18]
.sym 6500 rx_fifo.wr_addr[4]
.sym 6502 tx_fifo.rd_addr_gray[5]
.sym 6503 rx_fifo.wr_addr[9]
.sym 6504 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 6506 rx_fifo.wr_addr[8]
.sym 6513 w_smi_data_direction
.sym 6515 w_smi_data_output[6]
.sym 6516 $PACKER_VCC_NET
.sym 6517 rx_fifo.wr_addr[0]
.sym 6518 smi_ctrl_ins.r_fifo_pulled_data[13]
.sym 6528 rx_fifo.rd_addr[1]
.sym 6532 $PACKER_VCC_NET
.sym 6536 rx_fifo.rd_addr[0]
.sym 6539 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 6540 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 6541 rx_fifo.rd_addr[2]
.sym 6542 rx_fifo.rd_addr[5]
.sym 6543 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 6544 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 6548 rx_fifo.mem_i.0.1_WDATA
.sym 6549 rx_fifo.rd_addr[9]
.sym 6557 rx_fifo.mem_i.0.1_WDATA_1
.sym 6558 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 6559 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 6563 tx_fifo.rd_addr_gray[6]
.sym 6564 tx_fifo.rd_addr_gray[5]
.sym 6565 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3]
.sym 6566 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
.sym 6567 rx_fifo.mem_i.0.2_WDATA_2
.sym 6576 rx_fifo.rd_addr[2]
.sym 6577 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 6579 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 6580 rx_fifo.rd_addr[5]
.sym 6581 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 6582 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 6583 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 6584 rx_fifo.rd_addr[9]
.sym 6585 rx_fifo.rd_addr[1]
.sym 6586 rx_fifo.rd_addr[0]
.sym 6587 r_counter_$glb_clk
.sym 6588 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 6589 $PACKER_VCC_NET
.sym 6593 rx_fifo.mem_i.0.1_WDATA
.sym 6597 rx_fifo.mem_i.0.1_WDATA_1
.sym 6603 w_rx_fifo_pulled_data[13]
.sym 6607 smi_ctrl_ins.int_cnt_rx[3]
.sym 6608 $PACKER_VCC_NET
.sym 6610 w_rx_fifo_pulled_data[15]
.sym 6621 smi_ctrl_ins.r_fifo_pulled_data[7]
.sym 6636 rx_fifo.wr_addr[1]
.sym 6641 rx_fifo.wr_addr[2]
.sym 6642 rx_fifo.wr_addr[5]
.sym 6643 $PACKER_VCC_NET
.sym 6647 rx_fifo.wr_addr[9]
.sym 6648 rx_fifo.wr_addr[6]
.sym 6649 rx_fifo.wr_addr[3]
.sym 6650 rx_fifo.wr_addr[8]
.sym 6651 rx_fifo.wr_addr[7]
.sym 6655 rx_fifo.mem_i.0.2_WDATA_3
.sym 6657 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 6659 rx_fifo.wr_addr[4]
.sym 6660 rx_fifo.wr_addr[0]
.sym 6661 rx_fifo.mem_i.0.2_WDATA_2
.sym 6662 smi_ctrl_ins.r_fifo_pulled_data[24]
.sym 6663 smi_ctrl_ins.r_fifo_pulled_data[25]
.sym 6664 smi_ctrl_ins.r_fifo_pulled_data[27]
.sym 6665 smi_ctrl_ins.r_fifo_pulled_data[12]
.sym 6666 smi_ctrl_ins.r_fifo_pulled_data[6]
.sym 6667 smi_ctrl_ins.r_fifo_pulled_data[14]
.sym 6668 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
.sym 6669 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
.sym 6678 rx_fifo.wr_addr[2]
.sym 6679 rx_fifo.wr_addr[3]
.sym 6681 rx_fifo.wr_addr[4]
.sym 6682 rx_fifo.wr_addr[5]
.sym 6683 rx_fifo.wr_addr[6]
.sym 6684 rx_fifo.wr_addr[7]
.sym 6685 rx_fifo.wr_addr[8]
.sym 6686 rx_fifo.wr_addr[9]
.sym 6687 rx_fifo.wr_addr[1]
.sym 6688 rx_fifo.wr_addr[0]
.sym 6689 lvds_clock_$glb_clk
.sym 6690 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 6692 rx_fifo.mem_i.0.2_WDATA_3
.sym 6696 rx_fifo.mem_i.0.2_WDATA_2
.sym 6699 $PACKER_VCC_NET
.sym 6704 smi_ctrl_ins.int_cnt_rx[4]
.sym 6705 w_rx_09_fifo_data[26]
.sym 6706 smi_ctrl_ins.r_fifo_pulled_data[11]
.sym 6707 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 6708 rx_fifo.mem_q.0.3_WDATA_3
.sym 6709 smi_ctrl_ins.int_cnt_rx[3]
.sym 6710 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 6712 rx_fifo.wr_addr[1]
.sym 6713 rx_fifo.rd_addr[2]
.sym 6715 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 6717 rx_fifo.rd_addr[0]
.sym 6721 smi_ctrl_ins.int_cnt_rx[4]
.sym 6725 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 6727 rx_fifo.rd_addr[5]
.sym 6732 rx_fifo.rd_addr[2]
.sym 6733 rx_fifo.rd_addr[5]
.sym 6740 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 6745 $PACKER_VCC_NET
.sym 6746 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 6747 rx_fifo.mem_i.0.2_WDATA_1
.sym 6748 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 6750 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 6752 rx_fifo.rd_addr[1]
.sym 6756 rx_fifo.rd_addr[0]
.sym 6759 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 6760 rx_fifo.rd_addr[9]
.sym 6761 rx_fifo.mem_i.0.2_WDATA
.sym 6763 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 6764 smi_ctrl_ins.r_fifo_pulled_data[8]
.sym 6766 smi_ctrl_ins.r_fifo_pulled_data[16]
.sym 6767 smi_ctrl_ins.r_fifo_pulled_data[7]
.sym 6768 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
.sym 6769 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
.sym 6771 smi_ctrl_ins.r_fifo_pulled_data[4]
.sym 6780 rx_fifo.rd_addr[2]
.sym 6781 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 6783 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 6784 rx_fifo.rd_addr[5]
.sym 6785 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 6786 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 6787 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 6788 rx_fifo.rd_addr[9]
.sym 6789 rx_fifo.rd_addr[1]
.sym 6790 rx_fifo.rd_addr[0]
.sym 6791 r_counter_$glb_clk
.sym 6792 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 6793 $PACKER_VCC_NET
.sym 6797 rx_fifo.mem_i.0.2_WDATA
.sym 6801 rx_fifo.mem_i.0.2_WDATA_1
.sym 6806 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 6808 smi_ctrl_ins.int_cnt_rx[4]
.sym 6810 w_rx_fifo_pulled_data[12]
.sym 6813 $PACKER_VCC_NET
.sym 6816 $PACKER_VCC_NET
.sym 6818 rx_fifo.wr_addr[9]
.sym 6819 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 6820 w_rx_fifo_pulled_data[8]
.sym 6821 smi_ctrl_ins.r_fifo_pulled_data[18]
.sym 6822 rx_fifo.rd_addr[0]
.sym 6823 rx_fifo.rd_addr[1]
.sym 6824 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 6825 rx_fifo.wr_addr[4]
.sym 6826 rx_fifo.rd_addr[9]
.sym 6827 rx_fifo.wr_addr[3]
.sym 6828 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 6829 w_rx_fifo_pulled_data[14]
.sym 6835 rx_fifo.wr_addr[9]
.sym 6836 rx_fifo.wr_addr[1]
.sym 6837 rx_fifo.wr_addr[3]
.sym 6838 $PACKER_VCC_NET
.sym 6840 rx_fifo.mem_q.0.1_WDATA_2
.sym 6842 rx_fifo.wr_addr[7]
.sym 6845 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 6847 rx_fifo.mem_q.0.1_WDATA_3
.sym 6849 rx_fifo.wr_addr[6]
.sym 6851 rx_fifo.wr_addr[0]
.sym 6853 rx_fifo.wr_addr[5]
.sym 6854 rx_fifo.wr_addr[8]
.sym 6861 rx_fifo.wr_addr[2]
.sym 6865 rx_fifo.wr_addr[4]
.sym 6866 rx_fifo.rd_addr[0]
.sym 6868 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 6869 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
.sym 6870 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 6871 rx_fifo.rd_addr[5]
.sym 6873 rx_fifo.wr_addr[4]
.sym 6882 rx_fifo.wr_addr[2]
.sym 6883 rx_fifo.wr_addr[3]
.sym 6885 rx_fifo.wr_addr[4]
.sym 6886 rx_fifo.wr_addr[5]
.sym 6887 rx_fifo.wr_addr[6]
.sym 6888 rx_fifo.wr_addr[7]
.sym 6889 rx_fifo.wr_addr[8]
.sym 6890 rx_fifo.wr_addr[9]
.sym 6891 rx_fifo.wr_addr[1]
.sym 6892 rx_fifo.wr_addr[0]
.sym 6893 lvds_clock_$glb_clk
.sym 6894 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 6896 rx_fifo.mem_q.0.1_WDATA_3
.sym 6900 rx_fifo.mem_q.0.1_WDATA_2
.sym 6903 $PACKER_VCC_NET
.sym 6908 rx_fifo.mem_i.0.0_WDATA_3
.sym 6909 smi_ctrl_ins.r_fifo_pulled_data[10]
.sym 6910 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 6911 rx_fifo.wr_addr[2]
.sym 6912 rx_fifo.wr_addr[1]
.sym 6913 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 6914 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 6916 rx_fifo.mem_i.0.0_WDATA_2
.sym 6917 $PACKER_VCC_NET
.sym 6920 rx_fifo.wr_addr[8]
.sym 6921 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 6922 rx_fifo.wr_addr[0]
.sym 6923 rx_fifo.rd_addr[5]
.sym 6925 w_smi_data_direction
.sym 6926 rx_fifo.wr_addr_gray_rd_r[5]
.sym 6929 $PACKER_VCC_NET
.sym 6938 rx_fifo.rd_addr[2]
.sym 6940 $PACKER_VCC_NET
.sym 6941 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 6942 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 6947 rx_fifo.mem_q.0.1_WDATA_1
.sym 6951 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 6954 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 6956 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 6957 rx_fifo.rd_addr[5]
.sym 6960 rx_fifo.rd_addr[0]
.sym 6961 rx_fifo.rd_addr[1]
.sym 6963 rx_fifo.mem_q.0.1_WDATA
.sym 6964 rx_fifo.rd_addr[9]
.sym 6966 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 6968 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 6970 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[3]
.sym 6971 rx_fifo.wr_addr[4]
.sym 6972 rx_fifo.wr_addr[3]
.sym 6974 rx_fifo.wr_addr[8]
.sym 6975 rx_fifo.wr_addr[0]
.sym 6984 rx_fifo.rd_addr[2]
.sym 6985 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 6987 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 6988 rx_fifo.rd_addr[5]
.sym 6989 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 6990 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 6991 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 6992 rx_fifo.rd_addr[9]
.sym 6993 rx_fifo.rd_addr[1]
.sym 6994 rx_fifo.rd_addr[0]
.sym 6995 r_counter_$glb_clk
.sym 6996 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 6997 $PACKER_VCC_NET
.sym 7001 rx_fifo.mem_q.0.1_WDATA
.sym 7005 rx_fifo.mem_q.0.1_WDATA_1
.sym 7013 i_rst_b$SB_IO_IN
.sym 7014 rx_fifo.rd_addr[2]
.sym 7016 $PACKER_VCC_NET
.sym 7017 rx_fifo.rd_addr[0]
.sym 7018 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 7020 rx_fifo.mem_i.0.0_WDATA
.sym 7021 smi_ctrl_ins.r_fifo_pulled_data[0]
.sym 7023 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 7027 rx_fifo.wr_addr[8]
.sym 7029 rx_fifo.wr_addr[0]
.sym 7032 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 7033 rx_fifo.wr_addr[9]
.sym 7039 rx_fifo.wr_addr[9]
.sym 7040 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 7044 rx_fifo.mem_q.0.2_WDATA_2
.sym 7046 rx_fifo.wr_addr[5]
.sym 7049 rx_fifo.wr_addr[4]
.sym 7053 rx_fifo.mem_q.0.2_WDATA_3
.sym 7055 rx_fifo.wr_addr[7]
.sym 7060 rx_fifo.wr_addr[8]
.sym 7061 rx_fifo.wr_addr[0]
.sym 7063 rx_fifo.wr_addr[1]
.sym 7065 rx_fifo.wr_addr[2]
.sym 7066 rx_fifo.wr_addr[3]
.sym 7067 $PACKER_VCC_NET
.sym 7069 rx_fifo.wr_addr[6]
.sym 7072 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 7073 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 7074 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 7075 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 7076 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 7077 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 7086 rx_fifo.wr_addr[2]
.sym 7087 rx_fifo.wr_addr[3]
.sym 7089 rx_fifo.wr_addr[4]
.sym 7090 rx_fifo.wr_addr[5]
.sym 7091 rx_fifo.wr_addr[6]
.sym 7092 rx_fifo.wr_addr[7]
.sym 7093 rx_fifo.wr_addr[8]
.sym 7094 rx_fifo.wr_addr[9]
.sym 7095 rx_fifo.wr_addr[1]
.sym 7096 rx_fifo.wr_addr[0]
.sym 7097 lvds_clock_$glb_clk
.sym 7098 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 7100 rx_fifo.mem_q.0.2_WDATA_3
.sym 7104 rx_fifo.mem_q.0.2_WDATA_2
.sym 7107 $PACKER_VCC_NET
.sym 7112 rx_fifo.wr_addr[5]
.sym 7113 rx_fifo.wr_addr[8]
.sym 7115 rx_fifo.wr_addr[4]
.sym 7117 rx_fifo.wr_addr[0]
.sym 7118 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 7119 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 7120 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 7121 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 7122 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 7123 rx_fifo.rd_addr[1]
.sym 7125 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 7126 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
.sym 7128 rx_fifo.wr_addr[3]
.sym 7129 rx_fifo.rd_addr[5]
.sym 7131 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 7133 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 7143 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 7144 rx_fifo.mem_q.0.2_WDATA
.sym 7146 rx_fifo.mem_q.0.2_WDATA_1
.sym 7148 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 7149 rx_fifo.rd_addr[2]
.sym 7150 rx_fifo.rd_addr[5]
.sym 7151 rx_fifo.rd_addr[1]
.sym 7153 $PACKER_VCC_NET
.sym 7156 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 7157 rx_fifo.rd_addr[9]
.sym 7159 rx_fifo.rd_addr[0]
.sym 7162 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 7167 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 7169 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 7172 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 7173 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 7174 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
.sym 7175 rx_fifo.full_o_SB_LUT4_I0_O[0]
.sym 7176 rx_fifo.rd_addr_gray[5]
.sym 7177 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3]
.sym 7178 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
.sym 7179 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 7188 rx_fifo.rd_addr[2]
.sym 7189 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 7191 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 7192 rx_fifo.rd_addr[5]
.sym 7193 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 7194 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 7195 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 7196 rx_fifo.rd_addr[9]
.sym 7197 rx_fifo.rd_addr[1]
.sym 7198 rx_fifo.rd_addr[0]
.sym 7199 r_counter_$glb_clk
.sym 7200 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 7201 $PACKER_VCC_NET
.sym 7205 rx_fifo.mem_q.0.2_WDATA
.sym 7209 rx_fifo.mem_q.0.2_WDATA_1
.sym 7217 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 7218 $PACKER_VCC_NET
.sym 7220 rx_fifo.wr_addr[1]
.sym 7222 rx_fifo.wr_addr[2]
.sym 7225 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 7226 rx_fifo.rd_addr[9]
.sym 7227 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 7228 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 7229 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 7231 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
.sym 7232 rx_fifo.rd_addr_gray_wr_r[1]
.sym 7233 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 7234 rx_fifo.wr_addr[4]
.sym 7235 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 7236 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 7237 rx_fifo.wr_addr[9]
.sym 7243 rx_fifo.wr_addr[9]
.sym 7244 rx_fifo.wr_addr[4]
.sym 7246 rx_fifo.wr_addr[1]
.sym 7249 rx_fifo.wr_addr[5]
.sym 7250 rx_fifo.wr_addr[7]
.sym 7251 rx_fifo.mem_q.0.0_WDATA_3
.sym 7253 rx_fifo.wr_addr[6]
.sym 7255 rx_fifo.wr_addr[2]
.sym 7256 rx_fifo.wr_addr[0]
.sym 7260 rx_fifo.mem_q.0.0_WDATA_2
.sym 7262 rx_fifo.wr_addr[8]
.sym 7266 rx_fifo.wr_addr[3]
.sym 7269 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 7271 $PACKER_VCC_NET
.sym 7274 rx_fifo.rd_addr_gray[0]
.sym 7275 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
.sym 7276 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
.sym 7277 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
.sym 7279 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1]
.sym 7280 rx_fifo.rd_addr[9]
.sym 7281 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
.sym 7290 rx_fifo.wr_addr[2]
.sym 7291 rx_fifo.wr_addr[3]
.sym 7293 rx_fifo.wr_addr[4]
.sym 7294 rx_fifo.wr_addr[5]
.sym 7295 rx_fifo.wr_addr[6]
.sym 7296 rx_fifo.wr_addr[7]
.sym 7297 rx_fifo.wr_addr[8]
.sym 7298 rx_fifo.wr_addr[9]
.sym 7299 rx_fifo.wr_addr[1]
.sym 7300 rx_fifo.wr_addr[0]
.sym 7301 lvds_clock_$glb_clk
.sym 7302 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 7304 rx_fifo.mem_q.0.0_WDATA_3
.sym 7308 rx_fifo.mem_q.0.0_WDATA_2
.sym 7311 $PACKER_VCC_NET
.sym 7316 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 7319 rx_fifo.full_o_SB_LUT4_I0_O[0]
.sym 7322 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2]
.sym 7323 i_rst_b$SB_IO_IN
.sym 7324 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 7325 $PACKER_VCC_NET
.sym 7333 rx_fifo.wr_addr_gray_rd_r[5]
.sym 7338 rx_fifo.mem_q.0.0_WDATA
.sym 7344 rx_fifo.mem_q.0.0_WDATA
.sym 7347 rx_fifo.rd_addr[0]
.sym 7348 rx_fifo.rd_addr[1]
.sym 7350 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 7351 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 7355 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 7356 rx_fifo.rd_addr[5]
.sym 7357 rx_fifo.rd_addr[2]
.sym 7360 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 7366 rx_fifo.mem_q.0.0_WDATA_1
.sym 7367 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 7371 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 7373 $PACKER_VCC_NET
.sym 7374 rx_fifo.rd_addr[9]
.sym 7376 rx_fifo.wr_addr_gray[1]
.sym 7377 w_smi_read_req_SB_LUT4_I1_I3[3]
.sym 7378 rx_fifo.wr_addr_gray[8]
.sym 7379 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
.sym 7380 rx_fifo.wr_addr_gray[5]
.sym 7381 rx_fifo.wr_addr[9]
.sym 7383 rx_fifo.wr_addr_gray[0]
.sym 7392 rx_fifo.rd_addr[2]
.sym 7393 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 7395 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 7396 rx_fifo.rd_addr[5]
.sym 7397 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 7398 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 7399 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 7400 rx_fifo.rd_addr[9]
.sym 7401 rx_fifo.rd_addr[1]
.sym 7402 rx_fifo.rd_addr[0]
.sym 7403 r_counter_$glb_clk
.sym 7404 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 7405 $PACKER_VCC_NET
.sym 7409 rx_fifo.mem_q.0.0_WDATA
.sym 7413 rx_fifo.mem_q.0.0_WDATA_1
.sym 7418 w_rx_fifo_full
.sym 7419 rx_fifo.rd_addr[9]
.sym 7423 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
.sym 7425 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
.sym 7426 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 7428 rx_fifo.rd_addr[1]
.sym 7433 rx_fifo.wr_addr[9]
.sym 7436 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 7479 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 7480 rx_fifo.wr_addr_gray_rd_r[5]
.sym 7481 rx_fifo.wr_addr_gray_rd_r[8]
.sym 7482 rx_fifo.wr_addr_gray_rd[5]
.sym 7484 rx_fifo.wr_addr_gray_rd[8]
.sym 7485 rx_fifo.wr_addr_gray_rd[1]
.sym 7521 rx_fifo.wr_addr[1]
.sym 7529 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 7530 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 7531 i_rst_b$SB_IO_IN
.sym 7533 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 7542 $PACKER_VCC_NET
.sym 7580 rx_fifo.wr_addr_gray_rd[4]
.sym 7582 rx_fifo.wr_addr_gray_rd[2]
.sym 7583 rx_fifo.wr_addr_gray_rd[6]
.sym 7584 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 7585 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 7587 rx_fifo.wr_addr_gray_rd[3]
.sym 7636 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 7682 rx_fifo.wr_addr_gray[2]
.sym 7683 rx_fifo.wr_addr_gray[3]
.sym 7684 rx_fifo.wr_addr_gray[7]
.sym 7685 rx_fifo.wr_addr_gray[6]
.sym 7689 rx_fifo.wr_addr_gray[4]
.sym 7728 i_rst_b$SB_IO_IN
.sym 7835 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
.sym 7929 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 7935 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 8093 w_smi_data_output[6]
.sym 8095 w_smi_data_direction
.sym 8099 $PACKER_VCC_NET
.sym 8106 w_smi_data_output[6]
.sym 8112 w_smi_data_direction
.sym 8115 $PACKER_VCC_NET
.sym 8118 tx_fifo.rd_addr[0]
.sym 8119 tx_fifo.rd_addr[2]
.sym 8120 tx_fifo.rd_addr[1]
.sym 8121 tx_fifo.rd_addr[4]
.sym 8122 tx_fifo.rd_addr_gray[2]
.sym 8123 tx_fifo.rd_addr[3]
.sym 8124 tx_fifo.rd_addr_gray[3]
.sym 8125 tx_fifo.rd_addr[7]
.sym 8137 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 8140 rx_fifo.rd_addr[5]
.sym 8168 tx_fifo.rd_addr_gray_wr[3]
.sym 8171 tx_fifo.rd_addr_gray_wr[5]
.sym 8176 tx_fifo.rd_addr_gray[5]
.sym 8180 tx_fifo.rd_addr_gray[2]
.sym 8182 tx_fifo.rd_addr_gray[3]
.sym 8190 tx_fifo.rd_addr_gray_wr[6]
.sym 8191 tx_fifo.rd_addr_gray[6]
.sym 8193 tx_fifo.rd_addr_gray[3]
.sym 8202 tx_fifo.rd_addr_gray[2]
.sym 8205 tx_fifo.rd_addr_gray_wr[5]
.sym 8212 tx_fifo.rd_addr_gray[5]
.sym 8218 tx_fifo.rd_addr_gray_wr[6]
.sym 8225 tx_fifo.rd_addr_gray_wr[3]
.sym 8231 tx_fifo.rd_addr_gray[6]
.sym 8240 r_counter_$glb_clk
.sym 8246 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2]
.sym 8247 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[3]
.sym 8248 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1]
.sym 8249 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 8250 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2]
.sym 8251 w_tx_fifo_pull
.sym 8252 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
.sym 8253 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[1]
.sym 8260 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 8262 tx_fifo.rd_addr_gray_wr[2]
.sym 8264 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 8268 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
.sym 8269 tx_fifo.rd_addr[1]
.sym 8287 smi_ctrl_ins.r_fifo_pulled_data[20]
.sym 8288 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
.sym 8294 tx_fifo.rd_addr[7]
.sym 8295 i_rst_b_SB_LUT4_I3_O
.sym 8298 tx_fifo.rd_addr[2]
.sym 8299 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 8300 tx_fifo.rd_addr[1]
.sym 8301 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 8307 tx_fifo.rd_addr[3]
.sym 8308 w_smi_data_direction
.sym 8309 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
.sym 8312 tx_fifo.rd_addr_gray[6]
.sym 8315 i_rst_b_SB_LUT4_I3_O
.sym 8323 smi_ctrl_ins.r_fifo_pulled_data[18]
.sym 8324 w_rx_fifo_pulled_data[21]
.sym 8326 w_rx_fifo_pulled_data[15]
.sym 8327 smi_ctrl_ins.int_cnt_rx[4]
.sym 8333 smi_ctrl_ins.r_fifo_pulled_data[26]
.sym 8335 w_rx_fifo_pulled_data[13]
.sym 8336 w_rx_fifo_pulled_data[23]
.sym 8337 smi_ctrl_ins.int_cnt_rx[3]
.sym 8344 w_rx_fifo_pulled_data[22]
.sym 8348 w_rx_fifo_pulled_data[20]
.sym 8352 w_rx_fifo_pulled_data[26]
.sym 8356 smi_ctrl_ins.int_cnt_rx[4]
.sym 8357 smi_ctrl_ins.int_cnt_rx[3]
.sym 8358 smi_ctrl_ins.r_fifo_pulled_data[18]
.sym 8359 smi_ctrl_ins.r_fifo_pulled_data[26]
.sym 8362 w_rx_fifo_pulled_data[13]
.sym 8368 w_rx_fifo_pulled_data[26]
.sym 8376 w_rx_fifo_pulled_data[15]
.sym 8380 w_rx_fifo_pulled_data[23]
.sym 8388 w_rx_fifo_pulled_data[21]
.sym 8394 w_rx_fifo_pulled_data[20]
.sym 8398 w_rx_fifo_pulled_data[22]
.sym 8402 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
.sym 8403 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 8404 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 8405 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[2]
.sym 8406 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[2]
.sym 8407 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
.sym 8408 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[3]
.sym 8409 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
.sym 8410 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[3]
.sym 8411 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
.sym 8412 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 8423 smi_ctrl_ins.int_cnt_rx[4]
.sym 8435 i_rst_b$SB_IO_IN
.sym 8436 smi_ctrl_ins.r_fifo_pulled_data[21]
.sym 8439 smi_ctrl_ins.r_fifo_pulled_data[5]
.sym 8440 smi_ctrl_ins.r_fifo_pulled_data[22]
.sym 8448 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1]
.sym 8449 smi_ctrl_ins.r_fifo_pulled_data[15]
.sym 8452 smi_ctrl_ins.int_cnt_rx[3]
.sym 8455 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 8457 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 8458 w_rx_09_fifo_data[26]
.sym 8459 smi_ctrl_ins.int_cnt_rx[4]
.sym 8460 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 8464 tx_fifo.rd_addr[2]
.sym 8466 tx_fifo.rd_addr[1]
.sym 8468 w_rx_24_fifo_data[26]
.sym 8469 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 8476 smi_ctrl_ins.r_fifo_pulled_data[7]
.sym 8498 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1]
.sym 8505 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 8510 tx_fifo.rd_addr[1]
.sym 8511 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 8512 tx_fifo.rd_addr[2]
.sym 8515 smi_ctrl_ins.int_cnt_rx[4]
.sym 8516 smi_ctrl_ins.r_fifo_pulled_data[15]
.sym 8517 smi_ctrl_ins.int_cnt_rx[3]
.sym 8518 smi_ctrl_ins.r_fifo_pulled_data[7]
.sym 8521 w_rx_09_fifo_data[26]
.sym 8522 w_rx_24_fifo_data[26]
.sym 8523 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 8525 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 8526 lvds_clock_$glb_clk
.sym 8527 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 8528 w_smi_data_output[2]
.sym 8529 w_smi_data_output[7]
.sym 8530 w_smi_data_output[6]
.sym 8531 smi_ctrl_ins.w_fifo_pull_trigger
.sym 8532 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
.sym 8533 w_smi_data_output[5]
.sym 8534 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
.sym 8542 w_rx_fifo_pulled_data[14]
.sym 8545 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 8548 rx_fifo.wr_addr[9]
.sym 8550 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 8556 smi_ctrl_ins.int_cnt_rx[3]
.sym 8558 smi_ctrl_ins.int_cnt_rx[4]
.sym 8560 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 8561 tx_fifo.rd_addr[6]
.sym 8562 smi_ctrl_ins.r_fifo_pulled_data[25]
.sym 8570 w_rx_fifo_pulled_data[25]
.sym 8571 smi_ctrl_ins.r_fifo_pulled_data[13]
.sym 8574 w_rx_fifo_pulled_data[27]
.sym 8576 smi_ctrl_ins.int_cnt_rx[4]
.sym 8582 smi_ctrl_ins.int_cnt_rx[3]
.sym 8584 w_rx_fifo_pulled_data[12]
.sym 8586 w_rx_fifo_pulled_data[24]
.sym 8589 smi_ctrl_ins.r_fifo_pulled_data[6]
.sym 8590 smi_ctrl_ins.r_fifo_pulled_data[14]
.sym 8592 w_rx_fifo_pulled_data[14]
.sym 8598 w_rx_fifo_pulled_data[6]
.sym 8599 smi_ctrl_ins.r_fifo_pulled_data[5]
.sym 8605 w_rx_fifo_pulled_data[24]
.sym 8610 w_rx_fifo_pulled_data[25]
.sym 8617 w_rx_fifo_pulled_data[27]
.sym 8621 w_rx_fifo_pulled_data[12]
.sym 8628 w_rx_fifo_pulled_data[6]
.sym 8634 w_rx_fifo_pulled_data[14]
.sym 8638 smi_ctrl_ins.r_fifo_pulled_data[13]
.sym 8639 smi_ctrl_ins.r_fifo_pulled_data[5]
.sym 8640 smi_ctrl_ins.int_cnt_rx[3]
.sym 8641 smi_ctrl_ins.int_cnt_rx[4]
.sym 8644 smi_ctrl_ins.r_fifo_pulled_data[14]
.sym 8645 smi_ctrl_ins.r_fifo_pulled_data[6]
.sym 8646 smi_ctrl_ins.int_cnt_rx[4]
.sym 8647 smi_ctrl_ins.int_cnt_rx[3]
.sym 8648 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
.sym 8649 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 8650 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 8651 smi_ctrl_ins.r_fifo_pull
.sym 8654 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 8657 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
.sym 8658 smi_ctrl_ins.r_fifo_pull_1
.sym 8659 rx_fifo.rd_addr[9]
.sym 8661 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 8662 rx_fifo.rd_addr[9]
.sym 8663 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 8664 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
.sym 8668 $PACKER_VCC_NET
.sym 8669 smi_ctrl_ins.r_fifo_pulled_data[27]
.sym 8672 rx_fifo.rd_addr[5]
.sym 8674 w_smi_data_output[6]
.sym 8675 smi_ctrl_ins.r_fifo_pulled_data[9]
.sym 8683 rx_fifo.wr_addr[3]
.sym 8685 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 8692 smi_ctrl_ins.r_fifo_pulled_data[24]
.sym 8693 smi_ctrl_ins.int_cnt_rx[4]
.sym 8694 w_rx_fifo_pulled_data[16]
.sym 8696 smi_ctrl_ins.r_fifo_pulled_data[10]
.sym 8701 w_rx_fifo_pulled_data[4]
.sym 8710 smi_ctrl_ins.r_fifo_pulled_data[16]
.sym 8711 w_rx_fifo_pulled_data[8]
.sym 8713 w_rx_fifo_pulled_data[7]
.sym 8716 smi_ctrl_ins.int_cnt_rx[3]
.sym 8717 smi_ctrl_ins.r_fifo_pulled_data[2]
.sym 8728 w_rx_fifo_pulled_data[8]
.sym 8739 w_rx_fifo_pulled_data[16]
.sym 8743 w_rx_fifo_pulled_data[7]
.sym 8749 smi_ctrl_ins.r_fifo_pulled_data[24]
.sym 8750 smi_ctrl_ins.int_cnt_rx[4]
.sym 8751 smi_ctrl_ins.r_fifo_pulled_data[16]
.sym 8752 smi_ctrl_ins.int_cnt_rx[3]
.sym 8755 smi_ctrl_ins.int_cnt_rx[3]
.sym 8756 smi_ctrl_ins.r_fifo_pulled_data[2]
.sym 8757 smi_ctrl_ins.int_cnt_rx[4]
.sym 8758 smi_ctrl_ins.r_fifo_pulled_data[10]
.sym 8768 w_rx_fifo_pulled_data[4]
.sym 8771 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
.sym 8772 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 8773 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 8774 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
.sym 8775 w_smi_data_output[1]
.sym 8776 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
.sym 8777 w_smi_data_output[0]
.sym 8780 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
.sym 8788 w_rx_fifo_pulled_data[16]
.sym 8797 rx_fifo.wr_addr[8]
.sym 8798 rx_fifo.wr_addr_gray_rd_r[5]
.sym 8799 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 8800 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 8805 w_smi_data_direction
.sym 8806 rx_fifo.rd_addr[0]
.sym 8815 rx_fifo.rd_addr[0]
.sym 8818 rx_fifo.wr_addr[4]
.sym 8819 smi_ctrl_ins.int_cnt_rx[4]
.sym 8823 smi_ctrl_ins.r_fifo_pulled_data[8]
.sym 8826 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 8827 smi_ctrl_ins.r_fifo_pulled_data[0]
.sym 8828 smi_ctrl_ins.int_cnt_rx[3]
.sym 8833 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
.sym 8844 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
.sym 8845 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 8850 rx_fifo.rd_addr[0]
.sym 8862 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 8866 smi_ctrl_ins.r_fifo_pulled_data[8]
.sym 8867 smi_ctrl_ins.int_cnt_rx[4]
.sym 8868 smi_ctrl_ins.r_fifo_pulled_data[0]
.sym 8869 smi_ctrl_ins.int_cnt_rx[3]
.sym 8873 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 8879 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
.sym 8892 rx_fifo.wr_addr[4]
.sym 8894 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
.sym 8895 r_counter_$glb_clk
.sym 8896 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 8898 w_smi_read_req_SB_LUT4_I1_I3[2]
.sym 8899 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
.sym 8900 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
.sym 8901 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
.sym 8902 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
.sym 8903 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 8904 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 8906 smi_ctrl_ins.r_fifo_pulled_data[17]
.sym 8908 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 8909 rx_fifo.rd_addr[0]
.sym 8911 rx_fifo.rd_addr[5]
.sym 8916 $PACKER_VCC_NET
.sym 8919 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 8920 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
.sym 8921 rx_fifo.wr_addr[3]
.sym 8922 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 8923 rx_fifo.wr_addr[5]
.sym 8924 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 8925 rx_fifo.wr_addr[7]
.sym 8926 i_rst_b$SB_IO_IN
.sym 8927 rx_fifo.wr_addr[0]
.sym 8928 rx_fifo.wr_addr[9]
.sym 8930 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 8931 rx_fifo.wr_addr[6]
.sym 8932 w_smi_read_req_SB_LUT4_I1_I3[2]
.sym 8941 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 8942 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 8943 rx_fifo.rd_addr[5]
.sym 8944 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 8945 rx_fifo.wr_addr[0]
.sym 8948 rx_fifo.wr_addr_gray_rd_r[5]
.sym 8949 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 8950 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 8953 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 8954 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 8965 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
.sym 8971 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 8973 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 8974 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 8984 rx_fifo.wr_addr_gray_rd_r[5]
.sym 8985 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 8986 rx_fifo.rd_addr[5]
.sym 8991 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 8997 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 9009 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 9013 rx_fifo.wr_addr[0]
.sym 9017 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
.sym 9018 lvds_clock_$glb_clk
.sym 9019 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 9020 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 9021 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 9022 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
.sym 9023 w_smi_data_direction
.sym 9024 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
.sym 9025 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
.sym 9026 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3]
.sym 9027 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1]
.sym 9028 rx_fifo.wr_addr[3]
.sym 9031 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
.sym 9032 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 9034 rx_fifo.wr_addr[9]
.sym 9035 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 9036 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 9038 rx_fifo.rd_addr[1]
.sym 9040 rx_fifo.wr_addr[4]
.sym 9042 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 9044 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 9045 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 9046 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 9047 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 9049 rx_fifo.rd_addr_gray_wr_r[4]
.sym 9050 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
.sym 9051 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
.sym 9052 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 9053 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 9055 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 9062 rx_fifo.wr_addr[1]
.sym 9064 rx_fifo.wr_addr[4]
.sym 9068 rx_fifo.wr_addr[0]
.sym 9072 rx_fifo.wr_addr[2]
.sym 9073 rx_fifo.wr_addr[3]
.sym 9083 rx_fifo.wr_addr[5]
.sym 9085 rx_fifo.wr_addr[7]
.sym 9091 rx_fifo.wr_addr[6]
.sym 9093 $nextpnr_ICESTORM_LC_8$O
.sym 9095 rx_fifo.wr_addr[0]
.sym 9099 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 9102 rx_fifo.wr_addr[1]
.sym 9105 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 9108 rx_fifo.wr_addr[2]
.sym 9109 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 9111 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 9114 rx_fifo.wr_addr[3]
.sym 9115 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 9117 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 9119 rx_fifo.wr_addr[4]
.sym 9121 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 9123 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 9125 rx_fifo.wr_addr[5]
.sym 9127 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 9129 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 9131 rx_fifo.wr_addr[6]
.sym 9133 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 9135 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
.sym 9138 rx_fifo.wr_addr[7]
.sym 9139 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 9143 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
.sym 9144 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
.sym 9145 spi_if_ins.spi.SCKr[0]
.sym 9146 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
.sym 9147 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 9148 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
.sym 9149 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
.sym 9150 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
.sym 9158 w_smi_data_direction
.sym 9160 $PACKER_VCC_NET
.sym 9161 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 9163 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 9164 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
.sym 9165 rx_fifo.rd_addr[5]
.sym 9167 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 9168 rx_fifo.rd_addr[9]
.sym 9169 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 9170 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 9171 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
.sym 9172 rx_fifo.rd_addr_gray[0]
.sym 9173 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
.sym 9174 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
.sym 9175 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 9176 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
.sym 9177 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 9179 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
.sym 9188 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 9189 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 9190 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 9193 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2]
.sym 9195 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 9196 rx_fifo.wr_addr[8]
.sym 9198 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
.sym 9199 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 9202 rx_fifo.wr_addr[9]
.sym 9205 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3]
.sym 9206 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 9207 rx_fifo.rd_addr_gray_wr_r[1]
.sym 9210 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
.sym 9211 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
.sym 9212 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 9216 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 9218 rx_fifo.wr_addr[8]
.sym 9220 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
.sym 9224 rx_fifo.wr_addr[9]
.sym 9226 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 9229 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 9231 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 9235 rx_fifo.rd_addr_gray_wr_r[1]
.sym 9236 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 9237 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3]
.sym 9238 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2]
.sym 9242 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 9244 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
.sym 9247 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
.sym 9248 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 9250 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 9255 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 9256 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 9261 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 9262 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 9263 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
.sym 9264 r_counter_$glb_clk
.sym 9265 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 9266 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
.sym 9267 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 9268 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[1]
.sym 9269 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
.sym 9270 w_rx_fifo_full
.sym 9271 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0]
.sym 9272 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3]
.sym 9273 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
.sym 9290 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 9291 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 9292 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 9293 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 9294 rx_fifo.wr_addr_gray_rd_r[5]
.sym 9295 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
.sym 9296 rx_fifo.wr_addr_gray_rd_r[8]
.sym 9297 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 9301 rx_fifo.wr_addr_gray_rd[3]
.sym 9307 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
.sym 9308 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 9309 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
.sym 9310 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 9312 rx_fifo.rd_addr[1]
.sym 9313 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
.sym 9314 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 9315 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 9317 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
.sym 9318 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
.sym 9319 rx_fifo.rd_addr_gray_wr_r[4]
.sym 9320 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 9321 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
.sym 9322 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
.sym 9325 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 9326 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
.sym 9327 rx_fifo.wr_addr_gray_rd_r[5]
.sym 9329 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 9331 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 9334 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 9338 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
.sym 9343 rx_fifo.rd_addr[1]
.sym 9346 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
.sym 9347 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
.sym 9348 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
.sym 9349 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
.sym 9352 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
.sym 9353 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 9354 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 9355 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 9358 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 9359 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
.sym 9360 rx_fifo.rd_addr_gray_wr_r[4]
.sym 9361 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 9370 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 9371 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 9372 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 9373 rx_fifo.wr_addr_gray_rd_r[5]
.sym 9376 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 9382 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
.sym 9385 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
.sym 9386 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
.sym 9387 r_counter_$glb_clk
.sym 9388 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 9389 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
.sym 9390 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
.sym 9391 rx_fifo.rd_addr_gray[1]
.sym 9392 rx_fifo.rd_addr_gray[6]
.sym 9393 rx_fifo.rd_addr_gray[2]
.sym 9394 rx_fifo.rd_addr_gray[7]
.sym 9395 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[2]
.sym 9396 rx_fifo.rd_addr_gray[8]
.sym 9404 $PACKER_VCC_NET
.sym 9407 $PACKER_VCC_NET
.sym 9409 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 9413 i_rst_b$SB_IO_IN
.sym 9414 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
.sym 9415 rx_fifo.wr_addr[9]
.sym 9418 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
.sym 9420 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 9423 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 9424 w_smi_read_req_SB_LUT4_I1_I3[2]
.sym 9430 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 9431 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 9433 rx_fifo.wr_addr_gray_rd_r[8]
.sym 9434 rx_fifo.wr_addr[1]
.sym 9436 rx_fifo.rd_addr[9]
.sym 9442 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
.sym 9443 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 9444 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 9447 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 9449 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 9454 rx_fifo.wr_addr_gray_rd_r[9]
.sym 9455 rx_fifo.rd_addr[5]
.sym 9457 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
.sym 9463 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 9469 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 9471 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 9472 rx_fifo.rd_addr[5]
.sym 9476 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 9478 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 9481 rx_fifo.wr_addr_gray_rd_r[9]
.sym 9482 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 9483 rx_fifo.wr_addr_gray_rd_r[8]
.sym 9484 rx_fifo.rd_addr[9]
.sym 9490 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
.sym 9495 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 9506 rx_fifo.wr_addr[1]
.sym 9509 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
.sym 9510 lvds_clock_$glb_clk
.sym 9511 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 9512 rx_fifo.wr_addr_gray_rd_r[9]
.sym 9513 w_smi_read_req_SB_LUT4_I1_I3[0]
.sym 9514 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
.sym 9515 rx_fifo.wr_addr_gray_rd[9]
.sym 9516 w_smi_read_req_SB_LUT4_I1_O[3]
.sym 9517 rx_fifo.wr_addr_gray_rd[0]
.sym 9518 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0]
.sym 9519 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[2]
.sym 9528 rx_fifo.rd_addr_gray_wr_r[1]
.sym 9532 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 9539 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
.sym 9541 rx_fifo.rd_addr_gray_wr_r[4]
.sym 9542 rx_fifo.rd_addr_gray[7]
.sym 9543 rx_fifo.rd_addr_gray_wr_r[7]
.sym 9546 rx_fifo.rd_addr_gray[8]
.sym 9547 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 9553 rx_fifo.wr_addr_gray[1]
.sym 9557 rx_fifo.wr_addr_gray[5]
.sym 9561 rx_fifo.wr_addr_gray_rd[4]
.sym 9563 rx_fifo.wr_addr_gray[8]
.sym 9565 rx_fifo.wr_addr_gray_rd[5]
.sym 9567 rx_fifo.wr_addr_gray_rd[8]
.sym 9592 rx_fifo.wr_addr_gray_rd[4]
.sym 9601 rx_fifo.wr_addr_gray_rd[5]
.sym 9604 rx_fifo.wr_addr_gray_rd[8]
.sym 9612 rx_fifo.wr_addr_gray[5]
.sym 9625 rx_fifo.wr_addr_gray[8]
.sym 9629 rx_fifo.wr_addr_gray[1]
.sym 9633 r_counter_$glb_clk
.sym 9636 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
.sym 9637 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
.sym 9639 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
.sym 9640 rx_fifo.rd_addr_gray[4]
.sym 9641 rx_fifo.rd_addr_gray[3]
.sym 9660 w_smi_read_req_SB_LUT4_I1_O[2]
.sym 9661 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
.sym 9669 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
.sym 9676 rx_fifo.wr_addr_gray[2]
.sym 9683 rx_fifo.wr_addr_gray[4]
.sym 9685 rx_fifo.wr_addr_gray[3]
.sym 9686 rx_fifo.wr_addr_gray_rd[2]
.sym 9687 rx_fifo.wr_addr_gray[6]
.sym 9689 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 9691 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 9710 rx_fifo.wr_addr_gray[4]
.sym 9723 rx_fifo.wr_addr_gray[2]
.sym 9730 rx_fifo.wr_addr_gray[6]
.sym 9733 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 9735 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 9739 rx_fifo.wr_addr_gray_rd[2]
.sym 9752 rx_fifo.wr_addr_gray[3]
.sym 9756 r_counter_$glb_clk
.sym 9758 rx_fifo.rd_addr_gray_wr[7]
.sym 9759 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
.sym 9760 rx_fifo.rd_addr_gray_wr_r[4]
.sym 9761 rx_fifo.rd_addr_gray_wr_r[7]
.sym 9762 rx_fifo.rd_addr_gray_wr[8]
.sym 9763 rx_fifo.rd_addr_gray_wr[4]
.sym 9764 rx_fifo.rd_addr_gray_wr[3]
.sym 9765 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
.sym 9778 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
.sym 9793 rx_fifo.wr_addr_gray_rd[3]
.sym 9801 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
.sym 9805 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 9811 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 9815 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 9826 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
.sym 9828 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 9829 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
.sym 9832 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 9834 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 9840 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 9845 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
.sym 9853 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
.sym 9875 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 9878 rx_fifo.mem_i.0.0_WCLKE_SB_LUT4_I3_O
.sym 9879 lvds_clock_$glb_clk
.sym 9880 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 9881 w_smi_read_req_SB_LUT4_I1_O[2]
.sym 9884 rx_fifo.wr_addr_gray_rd[7]
.sym 9905 i_rst_b$SB_IO_IN
.sym 10172 o_shdn_rx_lna$SB_IO_OUT
.sym 10190 o_shdn_rx_lna$SB_IO_OUT
.sym 10197 lvds_clock
.sym 10198 o_shdn_rx_lna$SB_IO_OUT
.sym 10201 w_smi_data_output[2]
.sym 10203 w_smi_data_direction
.sym 10204 w_smi_data_output[1]
.sym 10206 w_smi_data_direction
.sym 10207 $PACKER_VCC_NET
.sym 10212 $PACKER_VCC_NET
.sym 10213 w_smi_data_direction
.sym 10215 w_smi_data_output[1]
.sym 10221 w_smi_data_direction
.sym 10225 w_smi_data_output[2]
.sym 10227 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
.sym 10228 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
.sym 10229 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10230 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
.sym 10231 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
.sym 10232 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 10233 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 10239 w_smi_data_output[1]
.sym 10254 tx_fifo.rd_addr[4]
.sym 10255 w_smi_data_output[2]
.sym 10260 $PACKER_VCC_NET
.sym 10261 w_smi_data_direction
.sym 10279 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 10280 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2]
.sym 10284 tx_fifo.rd_addr[0]
.sym 10291 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 10293 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
.sym 10294 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
.sym 10295 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10296 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
.sym 10301 tx_fifo.rd_addr[0]
.sym 10307 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
.sym 10313 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
.sym 10319 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
.sym 10327 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10328 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
.sym 10332 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10338 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2]
.sym 10343 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 10347 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 10348 lvds_clock_$glb_clk
.sym 10349 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 10352 w_smi_data_input[7]
.sym 10354 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 10355 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 10356 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[2]
.sym 10357 smi_ctrl_ins.int_cnt_rx[3]
.sym 10358 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1]
.sym 10359 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[3]
.sym 10360 smi_ctrl_ins.int_cnt_rx[4]
.sym 10361 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[3]
.sym 10366 tx_fifo.rd_addr[0]
.sym 10370 i_rst_b_SB_LUT4_I3_O
.sym 10394 w_smi_data_output[0]
.sym 10403 tx_fifo.rd_addr[7]
.sym 10405 tx_fifo.wr_addr_gray_rd[1]
.sym 10406 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
.sym 10407 tx_fifo.rd_addr[2]
.sym 10409 $PACKER_VCC_NET
.sym 10410 w_smi_data_output[7]
.sym 10415 w_smi_data_direction
.sym 10418 tx_fifo.rd_addr[8]
.sym 10420 smi_ctrl_ins.r_fifo_pulled_data[3]
.sym 10432 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[3]
.sym 10433 i_rst_b_SB_LUT4_I3_O
.sym 10434 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10435 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
.sym 10437 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 10438 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 10441 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
.sym 10442 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10450 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3]
.sym 10454 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[1]
.sym 10456 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
.sym 10457 i_rst_b$SB_IO_IN
.sym 10458 tx_fifo.wr_addr_gray_rd_r[2]
.sym 10459 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2]
.sym 10460 w_tx_fifo_pull
.sym 10464 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
.sym 10465 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[3]
.sym 10466 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
.sym 10467 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10471 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10472 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
.sym 10473 tx_fifo.wr_addr_gray_rd_r[2]
.sym 10478 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 10479 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 10483 w_tx_fifo_pull
.sym 10484 i_rst_b$SB_IO_IN
.sym 10488 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10490 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
.sym 10496 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3]
.sym 10501 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2]
.sym 10502 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
.sym 10503 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[1]
.sym 10507 tx_fifo.wr_addr_gray_rd_r[2]
.sym 10508 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
.sym 10509 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10510 i_rst_b_SB_LUT4_I3_O
.sym 10511 lvds_clock_$glb_clk
.sym 10512 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 10513 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 10514 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
.sym 10515 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
.sym 10516 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3]
.sym 10517 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
.sym 10518 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
.sym 10519 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[1]
.sym 10520 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
.sym 10526 smi_ctrl_ins.int_cnt_rx[4]
.sym 10528 smi_ctrl_ins.int_cnt_rx[3]
.sym 10529 tx_fifo.rd_addr[6]
.sym 10539 smi_ctrl_ins.int_cnt_rx[3]
.sym 10542 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
.sym 10544 tx_fifo.wr_addr_gray_rd_r[2]
.sym 10545 smi_ctrl_ins.int_cnt_rx[4]
.sym 10548 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 10554 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[2]
.sym 10555 smi_ctrl_ins.r_fifo_pulled_data[31]
.sym 10556 tx_fifo.rd_addr[3]
.sym 10557 smi_ctrl_ins.int_cnt_rx[3]
.sym 10559 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3]
.sym 10560 smi_ctrl_ins.int_cnt_rx[4]
.sym 10561 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[3]
.sym 10562 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2]
.sym 10564 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1]
.sym 10565 smi_ctrl_ins.int_cnt_rx[3]
.sym 10567 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[3]
.sym 10568 tx_fifo.rd_addr[7]
.sym 10569 tx_fifo.rd_addr[7]
.sym 10571 tx_fifo.wr_addr_gray_rd[1]
.sym 10572 tx_fifo.rd_addr[4]
.sym 10573 tx_fifo.rd_addr[2]
.sym 10575 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[2]
.sym 10577 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[1]
.sym 10578 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[1]
.sym 10579 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 10580 smi_ctrl_ins.r_fifo_pulled_data[11]
.sym 10582 smi_ctrl_ins.r_fifo_pulled_data[23]
.sym 10583 tx_fifo.rd_addr[6]
.sym 10584 tx_fifo.wr_addr_gray_rd_r[2]
.sym 10585 smi_ctrl_ins.r_fifo_pulled_data[3]
.sym 10587 tx_fifo.rd_addr[3]
.sym 10588 tx_fifo.rd_addr[2]
.sym 10590 tx_fifo.wr_addr_gray_rd_r[2]
.sym 10593 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[3]
.sym 10594 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[2]
.sym 10595 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[1]
.sym 10596 tx_fifo.rd_addr[4]
.sym 10599 smi_ctrl_ins.int_cnt_rx[4]
.sym 10600 smi_ctrl_ins.r_fifo_pulled_data[11]
.sym 10601 smi_ctrl_ins.r_fifo_pulled_data[3]
.sym 10602 smi_ctrl_ins.int_cnt_rx[3]
.sym 10605 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[1]
.sym 10606 tx_fifo.rd_addr[7]
.sym 10607 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[2]
.sym 10608 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[3]
.sym 10611 smi_ctrl_ins.int_cnt_rx[4]
.sym 10612 smi_ctrl_ins.r_fifo_pulled_data[31]
.sym 10613 smi_ctrl_ins.int_cnt_rx[3]
.sym 10614 smi_ctrl_ins.r_fifo_pulled_data[23]
.sym 10617 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3]
.sym 10618 tx_fifo.rd_addr[6]
.sym 10619 tx_fifo.rd_addr[7]
.sym 10620 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 10623 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 10624 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2]
.sym 10626 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1]
.sym 10629 tx_fifo.wr_addr_gray_rd[1]
.sym 10634 lvds_clock_$glb_clk
.sym 10636 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[1]
.sym 10638 tx_fifo.rd_addr_gray[8]
.sym 10640 tx_fifo.rd_addr[8]
.sym 10641 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[2]
.sym 10642 tx_fifo.rd_addr_gray[4]
.sym 10643 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[1]
.sym 10647 w_smi_read_req_SB_LUT4_I1_O[2]
.sym 10648 smi_ctrl_ins.r_fifo_pulled_data[20]
.sym 10649 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
.sym 10651 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 10652 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[2]
.sym 10653 rx_fifo.wr_addr[3]
.sym 10654 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
.sym 10659 smi_ctrl_ins.r_fifo_pulled_data[31]
.sym 10661 w_smi_read_req
.sym 10662 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 10665 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 10666 w_smi_data_output[0]
.sym 10669 smi_ctrl_ins.r_fifo_pulled_data[29]
.sym 10670 tx_fifo.wr_addr_gray_rd_r[2]
.sym 10671 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 10679 i_rst_b$SB_IO_IN
.sym 10681 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
.sym 10683 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
.sym 10684 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
.sym 10685 smi_ctrl_ins.r_fifo_pulled_data[30]
.sym 10686 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
.sym 10688 smi_ctrl_ins.r_fifo_pulled_data[12]
.sym 10689 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
.sym 10691 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
.sym 10692 smi_ctrl_ins.r_fifo_pulled_data[22]
.sym 10699 smi_ctrl_ins.int_cnt_rx[3]
.sym 10700 smi_ctrl_ins.r_fifo_pulled_data[4]
.sym 10705 smi_ctrl_ins.int_cnt_rx[4]
.sym 10706 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
.sym 10707 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
.sym 10710 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
.sym 10712 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
.sym 10716 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
.sym 10718 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
.sym 10724 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
.sym 10725 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
.sym 10729 smi_ctrl_ins.int_cnt_rx[3]
.sym 10730 smi_ctrl_ins.int_cnt_rx[4]
.sym 10734 smi_ctrl_ins.r_fifo_pulled_data[22]
.sym 10735 smi_ctrl_ins.int_cnt_rx[4]
.sym 10736 smi_ctrl_ins.int_cnt_rx[3]
.sym 10737 smi_ctrl_ins.r_fifo_pulled_data[30]
.sym 10740 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
.sym 10741 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
.sym 10746 smi_ctrl_ins.int_cnt_rx[3]
.sym 10747 smi_ctrl_ins.r_fifo_pulled_data[4]
.sym 10748 smi_ctrl_ins.r_fifo_pulled_data[12]
.sym 10749 smi_ctrl_ins.int_cnt_rx[4]
.sym 10756 i_rst_b$SB_IO_IN
.sym 10757 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 10759 tx_fifo.wr_addr_gray_rd[6]
.sym 10760 tx_fifo.wr_addr_gray_rd[8]
.sym 10761 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
.sym 10762 tx_fifo.wr_addr_gray_rd_r[2]
.sym 10763 tx_fifo.wr_addr_gray_rd[4]
.sym 10764 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 10765 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
.sym 10766 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0]
.sym 10770 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
.sym 10771 smi_ctrl_ins.r_fifo_pulled_data[30]
.sym 10772 tx_fifo.rd_addr_gray[4]
.sym 10775 rx_fifo.rd_addr[0]
.sym 10779 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 10780 rx_fifo.mem_q.0.3_WDATA_1
.sym 10783 tx_fifo.wr_addr_gray_rd[1]
.sym 10790 w_smi_data_output[5]
.sym 10803 smi_ctrl_ins.w_fifo_pull_trigger
.sym 10811 smi_ctrl_ins.int_cnt_rx[3]
.sym 10814 smi_ctrl_ins.r_fifo_pulled_data[21]
.sym 10815 smi_ctrl_ins.r_fifo_pull_1
.sym 10816 smi_ctrl_ins.r_fifo_pull
.sym 10817 smi_ctrl_ins.int_cnt_rx[4]
.sym 10821 w_smi_read_req
.sym 10829 smi_ctrl_ins.r_fifo_pulled_data[29]
.sym 10834 smi_ctrl_ins.w_fifo_pull_trigger
.sym 10851 w_smi_read_req
.sym 10852 smi_ctrl_ins.r_fifo_pull_1
.sym 10854 smi_ctrl_ins.r_fifo_pull
.sym 10869 smi_ctrl_ins.r_fifo_pulled_data[29]
.sym 10870 smi_ctrl_ins.int_cnt_rx[4]
.sym 10871 smi_ctrl_ins.int_cnt_rx[3]
.sym 10872 smi_ctrl_ins.r_fifo_pulled_data[21]
.sym 10878 smi_ctrl_ins.r_fifo_pull
.sym 10880 r_counter_$glb_clk
.sym 10881 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 10884 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 10886 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0]
.sym 10888 tx_fifo.wr_addr_gray_rd[1]
.sym 10894 rx_fifo.wr_addr[0]
.sym 10895 rx_fifo.wr_addr[3]
.sym 10897 rx_fifo.wr_addr[9]
.sym 10904 rx_fifo.wr_addr[5]
.sym 10906 rx_fifo.rd_addr[1]
.sym 10907 $PACKER_VCC_NET
.sym 10909 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 10910 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 10911 smi_ctrl_ins.r_fifo_pulled_data[1]
.sym 10912 w_smi_data_direction
.sym 10916 rx_fifo.rd_addr[2]
.sym 10926 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
.sym 10927 smi_ctrl_ins.r_fifo_pulled_data[9]
.sym 10928 smi_ctrl_ins.int_cnt_rx[3]
.sym 10933 smi_ctrl_ins.r_fifo_pulled_data[17]
.sym 10934 smi_ctrl_ins.r_fifo_pulled_data[25]
.sym 10935 smi_ctrl_ins.r_fifo_pulled_data[1]
.sym 10938 smi_ctrl_ins.int_cnt_rx[4]
.sym 10941 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 10942 i_rst_b$SB_IO_IN
.sym 10945 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
.sym 10947 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
.sym 10950 i_rst_b$SB_IO_IN
.sym 10951 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
.sym 10956 smi_ctrl_ins.r_fifo_pulled_data[9]
.sym 10957 smi_ctrl_ins.int_cnt_rx[3]
.sym 10958 smi_ctrl_ins.int_cnt_rx[4]
.sym 10959 smi_ctrl_ins.r_fifo_pulled_data[1]
.sym 10962 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
.sym 10965 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
.sym 10968 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 10969 i_rst_b$SB_IO_IN
.sym 10974 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
.sym 10976 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
.sym 10992 smi_ctrl_ins.int_cnt_rx[4]
.sym 10993 smi_ctrl_ins.r_fifo_pulled_data[17]
.sym 10994 smi_ctrl_ins.r_fifo_pulled_data[25]
.sym 10995 smi_ctrl_ins.int_cnt_rx[3]
.sym 11002 i_rst_b$SB_IO_IN
.sym 11003 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 11005 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 11006 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 11008 rx_fifo.rd_addr[2]
.sym 11009 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 11010 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 11011 rx_fifo.rd_addr[1]
.sym 11018 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 11030 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
.sym 11032 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 11035 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 11038 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 11039 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
.sym 11040 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 11062 rx_fifo.rd_addr[0]
.sym 11063 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 11066 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 11068 rx_fifo.rd_addr[1]
.sym 11070 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 11073 rx_fifo.rd_addr[2]
.sym 11074 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 11075 rx_fifo.rd_addr[5]
.sym 11078 $nextpnr_ICESTORM_LC_3$O
.sym 11081 rx_fifo.rd_addr[0]
.sym 11084 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 11086 rx_fifo.rd_addr[1]
.sym 11088 rx_fifo.rd_addr[0]
.sym 11090 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3
.sym 11093 rx_fifo.rd_addr[2]
.sym 11094 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 11096 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
.sym 11099 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 11100 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3
.sym 11102 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 11105 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 11106 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
.sym 11108 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 11110 rx_fifo.rd_addr[5]
.sym 11112 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 11114 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 11116 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 11118 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 11120 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 11123 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 11124 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 11129 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 11130 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 11131 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
.sym 11132 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1]
.sym 11133 spi_if_ins.r_tx_data_valid
.sym 11134 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 11135 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 11143 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 11149 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 11152 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 11153 w_smi_read_req
.sym 11154 rx_fifo.rd_addr[2]
.sym 11156 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3]
.sym 11158 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
.sym 11159 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 11160 rx_fifo.rd_addr[1]
.sym 11164 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 11170 rx_fifo.wr_addr_gray_rd_r[5]
.sym 11171 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
.sym 11172 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 11173 w_rx_data[0]
.sym 11174 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
.sym 11175 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 11176 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 11177 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 11179 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 11180 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
.sym 11181 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 11182 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 11185 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 11187 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[3]
.sym 11190 rx_fifo.rd_addr[9]
.sym 11198 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
.sym 11201 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 11204 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 11205 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 11210 rx_fifo.rd_addr[9]
.sym 11211 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 11214 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 11217 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 11223 w_rx_data[0]
.sym 11227 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 11228 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
.sym 11229 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 11233 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 11234 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 11238 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
.sym 11239 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 11240 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[3]
.sym 11241 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 11244 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
.sym 11245 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 11246 rx_fifo.wr_addr_gray_rd_r[5]
.sym 11248 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
.sym 11249 r_counter_$glb_clk
.sym 11250 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 11251 spi_if_ins.state_if[0]
.sym 11252 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
.sym 11253 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
.sym 11254 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
.sym 11255 spi_if_ins.state_if[1]
.sym 11256 spi_if_ins.state_if_SB_DFFESR_Q_E
.sym 11257 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
.sym 11258 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
.sym 11263 spi_if_ins.spi.r_tx_bit_count[0]
.sym 11264 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 11265 $PACKER_VCC_NET
.sym 11267 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 11269 w_rx_data[0]
.sym 11271 w_smi_data_direction
.sym 11272 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 11274 rx_fifo.rd_addr[0]
.sym 11276 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
.sym 11277 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
.sym 11279 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1]
.sym 11282 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
.sym 11284 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
.sym 11286 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
.sym 11292 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 11293 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 11294 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
.sym 11295 i_sck$SB_IO_IN
.sym 11296 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 11299 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1]
.sym 11303 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
.sym 11305 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
.sym 11308 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 11315 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 11318 spi_if_ins.spi.SCKr[0]
.sym 11320 w_smi_read_req_SB_LUT4_I1_O[2]
.sym 11322 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 11323 rx_fifo.wr_addr_gray_rd[3]
.sym 11325 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 11326 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 11331 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 11332 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 11333 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 11334 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
.sym 11340 i_sck$SB_IO_IN
.sym 11346 rx_fifo.wr_addr_gray_rd[3]
.sym 11351 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 11357 spi_if_ins.spi.SCKr[0]
.sym 11361 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
.sym 11362 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1]
.sym 11364 w_smi_read_req_SB_LUT4_I1_O[2]
.sym 11370 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
.sym 11372 r_counter_$glb_clk
.sym 11374 w_smi_read_req
.sym 11375 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
.sym 11376 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
.sym 11377 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 11378 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 11379 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 11380 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3]
.sym 11381 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
.sym 11386 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
.sym 11390 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 11396 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 11398 rx_fifo.wr_addr_gray_rd_r[9]
.sym 11406 rx_fifo.rd_addr[1]
.sym 11407 w_smi_read_req
.sym 11415 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 11416 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
.sym 11417 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 11419 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 11420 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1]
.sym 11421 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
.sym 11423 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 11424 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
.sym 11425 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
.sym 11426 rx_fifo.rd_addr[2]
.sym 11427 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
.sym 11428 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3]
.sym 11430 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
.sym 11432 rx_fifo.rd_addr[1]
.sym 11434 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
.sym 11436 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0]
.sym 11437 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
.sym 11438 rx_fifo.wr_addr_gray_rd_r[8]
.sym 11439 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1]
.sym 11440 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
.sym 11442 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 11443 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
.sym 11444 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0]
.sym 11445 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 11446 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
.sym 11448 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 11449 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
.sym 11450 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
.sym 11451 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 11454 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 11457 rx_fifo.rd_addr[2]
.sym 11460 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0]
.sym 11461 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1]
.sym 11462 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3]
.sym 11463 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
.sym 11466 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
.sym 11467 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 11468 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
.sym 11469 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
.sym 11472 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
.sym 11473 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
.sym 11474 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
.sym 11475 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
.sym 11478 rx_fifo.rd_addr[1]
.sym 11479 rx_fifo.rd_addr[2]
.sym 11480 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0]
.sym 11484 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 11486 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 11487 rx_fifo.wr_addr_gray_rd_r[8]
.sym 11490 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1]
.sym 11491 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
.sym 11492 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 11493 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
.sym 11495 lvds_clock_$glb_clk
.sym 11496 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 11497 rx_fifo.rd_addr_gray_wr[2]
.sym 11498 rx_fifo.rd_addr_gray_wr[6]
.sym 11501 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
.sym 11502 rx_fifo.rd_addr_gray_wr_r[1]
.sym 11504 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 11514 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
.sym 11515 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
.sym 11522 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0]
.sym 11523 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
.sym 11524 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 11526 w_rx_fifo_full
.sym 11528 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 11531 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
.sym 11532 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 11538 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
.sym 11539 w_smi_read_req_SB_LUT4_I1_I3[0]
.sym 11541 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 11543 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 11544 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3]
.sym 11545 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[2]
.sym 11546 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
.sym 11548 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[1]
.sym 11550 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 11551 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1]
.sym 11552 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
.sym 11553 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 11558 rx_fifo.wr_addr_gray_rd_r[9]
.sym 11560 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[1]
.sym 11565 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
.sym 11566 rx_fifo.rd_addr[1]
.sym 11568 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[2]
.sym 11571 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3]
.sym 11572 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[2]
.sym 11573 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[1]
.sym 11574 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 11577 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[2]
.sym 11578 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
.sym 11579 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[1]
.sym 11584 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 11589 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
.sym 11595 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1]
.sym 11601 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
.sym 11607 rx_fifo.wr_addr_gray_rd_r[9]
.sym 11608 w_smi_read_req_SB_LUT4_I1_I3[0]
.sym 11609 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 11610 rx_fifo.rd_addr[1]
.sym 11613 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 11616 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 11617 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
.sym 11618 r_counter_$glb_clk
.sym 11619 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 11620 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 11622 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
.sym 11624 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 11626 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[1]
.sym 11628 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 11637 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 11645 rx_fifo.rd_addr_gray[1]
.sym 11651 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 11653 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 11654 rx_fifo.rd_addr_gray_wr[1]
.sym 11655 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 11664 rx_fifo.wr_addr_gray_rd[9]
.sym 11666 rx_fifo.wr_addr_gray_rd[0]
.sym 11668 w_smi_read_req_SB_LUT4_I1_I3[2]
.sym 11670 w_smi_read_req_SB_LUT4_I1_I3[0]
.sym 11673 w_smi_read_req_SB_LUT4_I1_O[3]
.sym 11676 rx_fifo.wr_addr_gray_rd[1]
.sym 11677 w_smi_read_req
.sym 11678 w_smi_read_req_SB_LUT4_I1_I3[3]
.sym 11680 rx_fifo.wr_addr_gray_rd[6]
.sym 11682 rx_fifo.wr_addr[9]
.sym 11684 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 11688 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 11690 w_smi_read_req_SB_LUT4_I1_O[2]
.sym 11692 rx_fifo.wr_addr_gray[0]
.sym 11697 rx_fifo.wr_addr_gray_rd[9]
.sym 11702 rx_fifo.wr_addr_gray_rd[0]
.sym 11707 rx_fifo.wr_addr_gray_rd[6]
.sym 11712 rx_fifo.wr_addr[9]
.sym 11718 w_smi_read_req_SB_LUT4_I1_I3[0]
.sym 11719 w_smi_read_req_SB_LUT4_I1_I3[3]
.sym 11720 w_smi_read_req
.sym 11721 w_smi_read_req_SB_LUT4_I1_I3[2]
.sym 11727 rx_fifo.wr_addr_gray[0]
.sym 11732 rx_fifo.wr_addr_gray_rd[1]
.sym 11736 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 11737 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 11738 w_smi_read_req_SB_LUT4_I1_O[3]
.sym 11739 w_smi_read_req_SB_LUT4_I1_O[2]
.sym 11741 r_counter_$glb_clk
.sym 11746 rx_fifo.rd_addr_gray_wr[1]
.sym 11756 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
.sym 11761 w_rx_data[0]
.sym 11774 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
.sym 11786 rx_fifo.rd_addr_gray_wr_r[4]
.sym 11787 rx_fifo.rd_addr_gray_wr_r[7]
.sym 11788 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 11791 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
.sym 11792 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
.sym 11795 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
.sym 11799 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 11803 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
.sym 11804 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
.sym 11809 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
.sym 11811 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 11823 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
.sym 11826 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 11829 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
.sym 11830 rx_fifo.rd_addr_gray_wr_r[7]
.sym 11831 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
.sym 11832 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
.sym 11841 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 11843 rx_fifo.rd_addr_gray_wr_r[4]
.sym 11849 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
.sym 11855 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 11863 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
.sym 11864 r_counter_$glb_clk
.sym 11865 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 11867 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
.sym 11871 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 11884 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0]
.sym 11912 rx_fifo.rd_addr_gray_wr[4]
.sym 11915 rx_fifo.rd_addr_gray_wr[7]
.sym 11918 rx_fifo.rd_addr_gray[8]
.sym 11920 rx_fifo.rd_addr_gray[4]
.sym 11921 rx_fifo.rd_addr_gray[3]
.sym 11922 rx_fifo.rd_addr_gray[7]
.sym 11929 rx_fifo.rd_addr_gray_wr[3]
.sym 11935 rx_fifo.rd_addr_gray_wr[8]
.sym 11940 rx_fifo.rd_addr_gray[7]
.sym 11946 rx_fifo.rd_addr_gray_wr[8]
.sym 11955 rx_fifo.rd_addr_gray_wr[4]
.sym 11960 rx_fifo.rd_addr_gray_wr[7]
.sym 11966 rx_fifo.rd_addr_gray[8]
.sym 11971 rx_fifo.rd_addr_gray[4]
.sym 11977 rx_fifo.rd_addr_gray[3]
.sym 11983 rx_fifo.rd_addr_gray_wr[3]
.sym 11987 lvds_clock_$glb_clk
.sym 11993 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 12010 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 12048 rx_fifo.wr_addr_gray[7]
.sym 12049 rx_fifo.wr_addr_gray_rd[7]
.sym 12066 rx_fifo.wr_addr_gray_rd[7]
.sym 12084 rx_fifo.wr_addr_gray[7]
.sym 12110 r_counter_$glb_clk
.sym 12113 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
.sym 12305 i_rst_b$SB_IO_IN
.sym 12309 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
.sym 12310 w_smi_data_output[0]
.sym 12312 w_smi_data_direction
.sym 12313 w_smi_data_output[7]
.sym 12315 w_smi_data_direction
.sym 12316 $PACKER_VCC_NET
.sym 12321 w_smi_data_direction
.sym 12324 $PACKER_VCC_NET
.sym 12326 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
.sym 12329 w_smi_data_direction
.sym 12333 w_smi_data_output[7]
.sym 12334 w_smi_data_output[0]
.sym 12335 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
.sym 12336 tx_fifo.wr_addr_gray_rd[9]
.sym 12337 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
.sym 12338 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 12339 tx_fifo.wr_addr_gray_rd[3]
.sym 12340 i_rst_b_SB_LUT4_I3_O
.sym 12341 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 12342 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
.sym 12369 w_smi_data_input[7]
.sym 12379 tx_fifo.rd_addr[1]
.sym 12382 tx_fifo.rd_addr[3]
.sym 12385 tx_fifo.rd_addr[0]
.sym 12386 tx_fifo.rd_addr[2]
.sym 12388 tx_fifo.rd_addr[4]
.sym 12390 tx_fifo.rd_addr[0]
.sym 12392 tx_fifo.rd_addr[7]
.sym 12399 tx_fifo.rd_addr[5]
.sym 12406 tx_fifo.rd_addr[6]
.sym 12409 $nextpnr_ICESTORM_LC_7$O
.sym 12411 tx_fifo.rd_addr[0]
.sym 12415 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D_SB_LUT4_O_I3
.sym 12417 tx_fifo.rd_addr[1]
.sym 12419 tx_fifo.rd_addr[0]
.sym 12421 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 12424 tx_fifo.rd_addr[2]
.sym 12425 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D_SB_LUT4_O_I3
.sym 12427 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 12430 tx_fifo.rd_addr[3]
.sym 12431 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 12433 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3
.sym 12436 tx_fifo.rd_addr[4]
.sym 12437 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 12439 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 12441 tx_fifo.rd_addr[5]
.sym 12443 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3
.sym 12445 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 12448 tx_fifo.rd_addr[6]
.sym 12449 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 12451 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 12453 tx_fifo.rd_addr[7]
.sym 12455 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 12463 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[1]
.sym 12464 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
.sym 12465 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 12466 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 12467 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
.sym 12468 tx_fifo.rd_addr[6]
.sym 12469 tx_fifo.rd_addr[5]
.sym 12470 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[3]
.sym 12477 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
.sym 12489 $PACKER_VCC_NET
.sym 12502 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 12504 smi_ctrl_ins.int_cnt_rx[4]
.sym 12511 w_smi_data_output[3]
.sym 12513 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
.sym 12515 smi_ctrl_ins.int_cnt_rx[3]
.sym 12516 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 12517 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
.sym 12518 i_ss$SB_IO_IN
.sym 12519 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 12522 smi_ctrl_ins.int_cnt_rx[4]
.sym 12526 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 12529 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
.sym 12535 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 12540 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 12543 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3]
.sym 12550 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
.sym 12551 smi_ctrl_ins.int_cnt_rx[3]
.sym 12553 w_tx_fifo_pull
.sym 12555 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 12557 tx_fifo.rd_addr[2]
.sym 12559 tx_fifo.wr_addr_gray_rd_r[2]
.sym 12561 tx_fifo.rd_addr[3]
.sym 12562 smi_ctrl_ins.int_cnt_rx[4]
.sym 12564 tx_fifo.rd_addr[8]
.sym 12565 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
.sym 12567 tx_fifo.rd_addr[4]
.sym 12569 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
.sym 12572 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 12574 tx_fifo.rd_addr[8]
.sym 12576 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 12580 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
.sym 12582 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 12585 w_tx_fifo_pull
.sym 12586 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3]
.sym 12587 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
.sym 12588 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
.sym 12592 smi_ctrl_ins.int_cnt_rx[3]
.sym 12597 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 12599 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 12603 tx_fifo.wr_addr_gray_rd_r[2]
.sym 12604 tx_fifo.rd_addr[4]
.sym 12605 tx_fifo.rd_addr[2]
.sym 12606 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
.sym 12609 smi_ctrl_ins.int_cnt_rx[3]
.sym 12611 smi_ctrl_ins.int_cnt_rx[4]
.sym 12615 tx_fifo.rd_addr[3]
.sym 12616 tx_fifo.rd_addr[4]
.sym 12618 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
.sym 12620 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 12621 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 12622 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
.sym 12623 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
.sym 12624 tx_fifo.rd_addr_gray[1]
.sym 12625 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
.sym 12626 tx_fifo.rd_addr_gray[7]
.sym 12627 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
.sym 12628 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
.sym 12629 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
.sym 12639 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 12643 rx_fifo.mem_q.0.3_WDATA_2
.sym 12647 tx_fifo.wr_addr[1]
.sym 12648 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 12649 smi_ctrl_ins.int_cnt_rx[3]
.sym 12650 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
.sym 12654 tx_fifo.rd_addr[5]
.sym 12655 tx_fifo.wr_addr_gray_rd[3]
.sym 12657 $PACKER_VCC_NET
.sym 12664 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 12665 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[2]
.sym 12667 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
.sym 12668 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
.sym 12669 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
.sym 12670 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
.sym 12671 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 12672 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
.sym 12673 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
.sym 12674 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[3]
.sym 12675 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1]
.sym 12676 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[3]
.sym 12677 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[1]
.sym 12678 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[2]
.sym 12679 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 12682 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[0]
.sym 12683 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
.sym 12684 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
.sym 12686 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0]
.sym 12688 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
.sym 12689 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 12690 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
.sym 12691 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0]
.sym 12692 w_tx_fifo_pull
.sym 12693 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
.sym 12696 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[2]
.sym 12697 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[0]
.sym 12698 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[3]
.sym 12699 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[1]
.sym 12702 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0]
.sym 12705 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
.sym 12708 w_tx_fifo_pull
.sym 12709 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 12710 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
.sym 12714 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
.sym 12715 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
.sym 12716 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
.sym 12717 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 12721 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 12723 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 12726 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1]
.sym 12727 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
.sym 12728 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 12729 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
.sym 12732 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[3]
.sym 12733 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
.sym 12734 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[2]
.sym 12735 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0]
.sym 12738 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
.sym 12739 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
.sym 12740 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
.sym 12743 lvds_clock_$glb_clk
.sym 12744 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 12745 tx_fifo.full_o_SB_LUT4_I1_O[2]
.sym 12746 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
.sym 12747 tx_fifo.wr_addr_gray[6]
.sym 12748 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[0]
.sym 12750 tx_fifo.wr_addr_gray[4]
.sym 12759 smi_ctrl_ins.r_fifo_pulled_data[28]
.sym 12760 w_smi_data_output[5]
.sym 12769 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 12770 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
.sym 12772 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0]
.sym 12777 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0]
.sym 12779 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 12780 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0]
.sym 12790 tx_fifo.rd_addr[8]
.sym 12791 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
.sym 12793 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0]
.sym 12795 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
.sym 12798 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
.sym 12799 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 12800 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
.sym 12803 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 12804 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
.sym 12813 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 12814 tx_fifo.rd_addr[5]
.sym 12820 tx_fifo.rd_addr[5]
.sym 12822 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0]
.sym 12834 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
.sym 12844 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 12849 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
.sym 12850 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
.sym 12851 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
.sym 12852 tx_fifo.rd_addr[8]
.sym 12857 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
.sym 12862 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 12864 tx_fifo.rd_addr[8]
.sym 12865 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 12866 lvds_clock_$glb_clk
.sym 12867 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 12868 tx_fifo.wr_addr_gray[1]
.sym 12869 tx_fifo.wr_addr_gray[0]
.sym 12870 tx_fifo.wr_addr_gray[8]
.sym 12871 tx_fifo.wr_addr_gray[2]
.sym 12872 tx_fifo.wr_addr_gray[5]
.sym 12875 tx_fifo.wr_addr_gray[7]
.sym 12884 rx_fifo.mem_q.0.3_WDATA
.sym 12886 tx_fifo.rd_addr_gray[8]
.sym 12889 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 12892 rx_fifo.wr_addr[8]
.sym 12894 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 12895 i_rst_b$SB_IO_IN
.sym 12898 rx_fifo.rd_addr[2]
.sym 12900 rx_fifo.wr_addr[0]
.sym 12911 tx_fifo.wr_addr_gray[6]
.sym 12913 tx_fifo.wr_addr_gray_rd[4]
.sym 12922 tx_fifo.wr_addr_gray[4]
.sym 12925 tx_fifo.wr_addr_gray_rd[3]
.sym 12926 tx_fifo.wr_addr_gray_rd[8]
.sym 12927 tx_fifo.wr_addr_gray[8]
.sym 12939 tx_fifo.wr_addr_gray_rd[7]
.sym 12940 tx_fifo.wr_addr_gray_rd[2]
.sym 12944 tx_fifo.wr_addr_gray[6]
.sym 12949 tx_fifo.wr_addr_gray[8]
.sym 12956 tx_fifo.wr_addr_gray_rd[3]
.sym 12963 tx_fifo.wr_addr_gray_rd[2]
.sym 12966 tx_fifo.wr_addr_gray[4]
.sym 12972 tx_fifo.wr_addr_gray_rd[7]
.sym 12981 tx_fifo.wr_addr_gray_rd[8]
.sym 12987 tx_fifo.wr_addr_gray_rd[4]
.sym 12989 lvds_clock_$glb_clk
.sym 12991 tx_fifo.wr_addr_gray_rd[0]
.sym 12993 tx_fifo.wr_addr_gray_rd[5]
.sym 12996 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0]
.sym 12997 tx_fifo.wr_addr_gray_rd[7]
.sym 12998 tx_fifo.wr_addr_gray_rd[2]
.sym 13005 rx_fifo.mem_i.0.0_WDATA_1
.sym 13007 rx_fifo.wr_addr[6]
.sym 13011 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 13012 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 13013 rx_fifo.mem_i.0.3_WDATA_1
.sym 13016 rx_fifo.rd_addr[1]
.sym 13018 $PACKER_VCC_NET
.sym 13019 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 13020 rx_fifo.wr_addr[1]
.sym 13022 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 13024 i_ss$SB_IO_IN
.sym 13026 rx_fifo.rd_addr[2]
.sym 13032 tx_fifo.wr_addr_gray_rd[6]
.sym 13040 tx_fifo.wr_addr_gray[1]
.sym 13048 tx_fifo.wr_addr_gray_rd[0]
.sym 13079 tx_fifo.wr_addr_gray_rd[6]
.sym 13089 tx_fifo.wr_addr_gray_rd[0]
.sym 13102 tx_fifo.wr_addr_gray[1]
.sym 13112 lvds_clock_$glb_clk
.sym 13116 tx_fifo.rd_addr_gray[0]
.sym 13122 io_pmod_in[3]$SB_IO_IN
.sym 13125 io_pmod_in[3]$SB_IO_IN
.sym 13128 rx_fifo.mem_i.0.3_WDATA
.sym 13131 smi_ctrl_ins.r_fifo_pulled_data[29]
.sym 13132 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 13133 w_smi_read_req
.sym 13138 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 13140 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
.sym 13142 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
.sym 13144 $PACKER_VCC_NET
.sym 13146 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 13147 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
.sym 13159 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
.sym 13164 w_smi_read_req_SB_LUT4_I1_I3[2]
.sym 13165 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
.sym 13166 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
.sym 13170 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 13173 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
.sym 13179 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 13190 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
.sym 13197 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 13206 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
.sym 13214 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
.sym 13218 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 13226 w_smi_read_req_SB_LUT4_I1_I3[2]
.sym 13234 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
.sym 13235 r_counter_$glb_clk
.sym 13236 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 13238 $PACKER_VCC_NET
.sym 13239 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
.sym 13240 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 13241 spi_if_ins.spi.r_tx_bit_count[0]
.sym 13242 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
.sym 13244 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
.sym 13245 io_pmod_in[2]$SB_IO_IN
.sym 13248 io_pmod_in[2]$SB_IO_IN
.sym 13249 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 13251 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 13253 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 13257 rx_fifo.rd_addr[2]
.sym 13258 w_rx_fifo_pulled_data[18]
.sym 13259 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 13260 rx_fifo.mem_i.0.3_WDATA_3
.sym 13264 rx_fifo.rd_addr[2]
.sym 13265 i_rst_b$SB_IO_IN
.sym 13267 rx_fifo.rd_addr[9]
.sym 13268 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 13270 rx_fifo.rd_addr[1]
.sym 13272 $PACKER_VCC_NET
.sym 13280 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
.sym 13288 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 13289 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
.sym 13291 spi_if_ins.r_tx_data_valid
.sym 13294 i_ss$SB_IO_IN
.sym 13298 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 13299 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
.sym 13301 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
.sym 13303 w_smi_read_req_SB_LUT4_I1_I3[2]
.sym 13304 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
.sym 13305 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
.sym 13306 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
.sym 13307 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
.sym 13319 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
.sym 13320 w_smi_read_req_SB_LUT4_I1_I3[2]
.sym 13323 spi_if_ins.r_tx_data_valid
.sym 13325 i_ss$SB_IO_IN
.sym 13329 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
.sym 13331 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
.sym 13335 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
.sym 13336 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
.sym 13342 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
.sym 13347 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
.sym 13348 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
.sym 13350 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 13355 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
.sym 13356 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
.sym 13357 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
.sym 13358 r_counter_$glb_clk
.sym 13359 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 13360 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
.sym 13361 w_smi_read_req
.sym 13363 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
.sym 13364 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
.sym 13366 w_fetch
.sym 13367 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
.sym 13378 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 13379 o_led0_SB_LUT4_I1_O[1]
.sym 13381 $PACKER_VCC_NET
.sym 13382 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 13388 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
.sym 13389 w_cs[2]
.sym 13390 w_rx_data[2]
.sym 13391 i_rst_b$SB_IO_IN
.sym 13392 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 13403 spi_if_ins.state_if_SB_DFFESR_Q_E
.sym 13404 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
.sym 13405 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 13407 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3]
.sym 13408 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 13409 spi_if_ins.state_if[0]
.sym 13411 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
.sym 13413 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 13414 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 13416 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
.sym 13417 i_rst_b$SB_IO_IN
.sym 13420 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
.sym 13421 spi_if_ins.state_if[1]
.sym 13424 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 13425 i_rst_b$SB_IO_IN
.sym 13427 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
.sym 13431 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
.sym 13437 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
.sym 13440 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
.sym 13442 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 13446 spi_if_ins.state_if[1]
.sym 13448 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
.sym 13449 spi_if_ins.state_if[0]
.sym 13452 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 13453 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
.sym 13454 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
.sym 13455 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 13459 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 13460 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 13461 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
.sym 13464 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
.sym 13465 i_rst_b$SB_IO_IN
.sym 13466 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
.sym 13467 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3]
.sym 13470 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 13471 i_rst_b$SB_IO_IN
.sym 13476 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
.sym 13480 spi_if_ins.state_if_SB_DFFESR_Q_E
.sym 13481 r_counter_$glb_clk
.sym 13482 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 13483 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
.sym 13484 w_rx_data[2]
.sym 13485 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 13486 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
.sym 13488 spi_if_ins.o_data_in_SB_DFFE_Q_E
.sym 13489 w_rx_data[6]
.sym 13490 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1]
.sym 13496 w_fetch
.sym 13497 spi_if_ins.state_if_SB_DFFESR_Q_E
.sym 13499 rx_fifo.wr_addr[6]
.sym 13507 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 13509 spi_if_ins.r_tx_byte[7]
.sym 13510 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 13518 w_rx_data[2]
.sym 13524 spi_if_ins.state_if[0]
.sym 13526 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
.sym 13528 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 13530 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
.sym 13531 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
.sym 13532 spi_if_ins.state_if[0]
.sym 13535 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
.sym 13536 spi_if_ins.state_if[1]
.sym 13537 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 13538 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3]
.sym 13539 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
.sym 13541 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
.sym 13544 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 13548 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
.sym 13549 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
.sym 13557 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
.sym 13558 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
.sym 13559 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
.sym 13560 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
.sym 13563 spi_if_ins.state_if[0]
.sym 13564 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
.sym 13565 spi_if_ins.state_if[1]
.sym 13569 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 13571 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 13576 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 13581 spi_if_ins.state_if[0]
.sym 13584 spi_if_ins.state_if[1]
.sym 13587 spi_if_ins.state_if[1]
.sym 13588 spi_if_ins.state_if[0]
.sym 13590 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
.sym 13593 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 13594 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
.sym 13595 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 13599 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3]
.sym 13600 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
.sym 13602 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
.sym 13604 r_counter_$glb_clk
.sym 13605 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 13606 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
.sym 13607 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
.sym 13608 w_cs[0]
.sym 13611 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
.sym 13612 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 13613 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 13618 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 13619 w_rx_data[6]
.sym 13620 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 13621 spi_if_ins.w_rx_data[6]
.sym 13627 rx_fifo.rd_addr[9]
.sym 13628 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 13629 spi_if_ins.w_rx_data[2]
.sym 13633 spi_if_ins.r_tx_byte[7]
.sym 13634 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 13637 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 13640 i_rst_b$SB_IO_IN
.sym 13647 rx_fifo.rd_addr_gray_wr[2]
.sym 13651 rx_fifo.rd_addr_gray[2]
.sym 13658 rx_fifo.rd_addr_gray[6]
.sym 13664 rx_fifo.rd_addr_gray_wr[6]
.sym 13677 rx_fifo.rd_addr_gray_wr[1]
.sym 13680 rx_fifo.rd_addr_gray[2]
.sym 13689 rx_fifo.rd_addr_gray[6]
.sym 13704 rx_fifo.rd_addr_gray_wr[2]
.sym 13712 rx_fifo.rd_addr_gray_wr[1]
.sym 13724 rx_fifo.rd_addr_gray_wr[6]
.sym 13727 lvds_clock_$glb_clk
.sym 13729 w_tx_data_io[7]
.sym 13730 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
.sym 13731 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1]
.sym 13732 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
.sym 13733 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 13735 i_button_SB_LUT4_I0_I3[3]
.sym 13736 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2]
.sym 13748 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
.sym 13751 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
.sym 13752 w_cs[0]
.sym 13757 i_rst_b$SB_IO_IN
.sym 13760 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
.sym 13761 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 13772 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
.sym 13776 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0]
.sym 13777 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 13779 w_rx_data[0]
.sym 13783 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
.sym 13788 w_rx_data[2]
.sym 13805 w_rx_data[2]
.sym 13817 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
.sym 13827 w_rx_data[0]
.sym 13840 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 13841 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0]
.sym 13849 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
.sym 13850 r_counter_$glb_clk
.sym 13851 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 13852 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
.sym 13853 w_tx_data_io[5]
.sym 13854 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
.sym 13856 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E
.sym 13857 sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2]
.sym 13858 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3]
.sym 13859 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
.sym 13871 w_cs[2]
.sym 13872 w_cs[1]
.sym 13878 i_rst_b$SB_IO_IN
.sym 13880 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
.sym 13881 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 13882 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 13883 w_cs[3]
.sym 13885 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 13887 w_rx_data[2]
.sym 13898 rx_fifo.rd_addr_gray[1]
.sym 13944 rx_fifo.rd_addr_gray[1]
.sym 13973 lvds_clock_$glb_clk
.sym 13975 r_tx_data[2]
.sym 13980 r_tx_data[0]
.sym 13982 r_tx_data[7]
.sym 13988 i_button_SB_LUT4_I0_I3[1]
.sym 13991 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
.sym 13993 w_rx_fifo_full
.sym 13994 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
.sym 13995 w_tx_data_io[2]
.sym 13999 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 14001 spi_if_ins.r_tx_byte[7]
.sym 14003 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E
.sym 14006 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[0]
.sym 14008 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0]
.sym 14018 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 14024 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 14025 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 14035 io_pmod_in[2]$SB_IO_IN
.sym 14042 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 14043 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 14057 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 14058 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 14079 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 14080 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 14081 io_pmod_in[2]$SB_IO_IN
.sym 14095 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 14096 lvds_clock_$glb_clk
.sym 14097 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 14098 spi_if_ins.r_tx_byte[2]
.sym 14101 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 14102 spi_if_ins.r_tx_byte[0]
.sym 14105 spi_if_ins.r_tx_byte[7]
.sym 14107 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
.sym 14111 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 14112 o_shdn_tx_lna$SB_IO_OUT
.sym 14114 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
.sym 14118 o_tr_vc1$SB_IO_OUT
.sym 14119 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 14129 spi_if_ins.r_tx_byte[7]
.sym 14131 i_rst_b$SB_IO_IN
.sym 14150 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 14151 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 14159 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 14162 io_pmod_in[3]$SB_IO_IN
.sym 14197 io_pmod_in[3]$SB_IO_IN
.sym 14198 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 14199 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 14218 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 14219 lvds_clock_$glb_clk
.sym 14220 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 14222 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0]
.sym 14223 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
.sym 14224 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[0]
.sym 14225 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0]
.sym 14226 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
.sym 14227 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
.sym 14249 i_rst_b$SB_IO_IN
.sym 14276 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 14301 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 14344 i_rst_b$SB_IO_IN
.sym 14360 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 14365 i_rst_b$SB_IO_IN
.sym 14388 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
.sym 14399 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
.sym 14418 i_rst_b_SB_LUT4_I3_O
.sym 14419 w_smi_data_output[3]
.sym 14421 w_smi_data_direction
.sym 14425 $PACKER_VCC_NET
.sym 14430 $PACKER_VCC_NET
.sym 14431 w_smi_data_direction
.sym 14433 i_rst_b_SB_LUT4_I3_O
.sym 14434 w_smi_data_output[3]
.sym 14445 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
.sym 14446 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
.sym 14447 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
.sym 14448 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 14449 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 14450 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
.sym 14451 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 14456 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 14460 i_rst_b$SB_IO_IN
.sym 14478 i_ss$SB_IO_IN
.sym 14487 tx_fifo.wr_addr_gray_rd[9]
.sym 14489 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
.sym 14504 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
.sym 14505 tx_fifo.wr_addr_gray[3]
.sym 14506 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 14508 smi_ctrl_ins.int_cnt_rx[4]
.sym 14510 i_rst_b$SB_IO_IN
.sym 14511 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
.sym 14512 tx_fifo.wr_addr[9]
.sym 14513 smi_ctrl_ins.int_cnt_rx[3]
.sym 14515 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 14516 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
.sym 14519 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 14520 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
.sym 14527 tx_fifo.wr_addr[9]
.sym 14532 tx_fifo.wr_addr_gray_rd[9]
.sym 14538 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 14539 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
.sym 14546 tx_fifo.wr_addr_gray[3]
.sym 14551 i_rst_b$SB_IO_IN
.sym 14555 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
.sym 14557 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
.sym 14562 smi_ctrl_ins.int_cnt_rx[3]
.sym 14563 i_rst_b$SB_IO_IN
.sym 14564 smi_ctrl_ins.int_cnt_rx[4]
.sym 14566 lvds_clock_$glb_clk
.sym 14568 o_smi_write_req$SB_IO_OUT
.sym 14572 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 14573 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 14574 tx_fifo.wr_addr[9]
.sym 14575 tx_fifo.wr_addr_gray[3]
.sym 14576 tx_fifo.wr_addr[5]
.sym 14577 tx_fifo.wr_addr[3]
.sym 14578 tx_fifo.wr_addr[8]
.sym 14579 tx_fifo.wr_addr[7]
.sym 14587 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
.sym 14589 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 14592 tx_fifo.wr_addr[1]
.sym 14594 tx_fifo.wr_addr_gray_rd[3]
.sym 14623 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
.sym 14626 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
.sym 14631 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 14632 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
.sym 14633 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 14635 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
.sym 14636 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 14637 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 14651 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 14659 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
.sym 14660 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
.sym 14661 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
.sym 14663 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
.sym 14664 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 14669 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
.sym 14670 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
.sym 14671 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 14674 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
.sym 14675 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
.sym 14677 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
.sym 14683 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
.sym 14684 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
.sym 14685 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
.sym 14688 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
.sym 14690 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
.sym 14694 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
.sym 14697 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
.sym 14700 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
.sym 14703 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 14708 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
.sym 14709 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
.sym 14715 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 14719 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
.sym 14724 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
.sym 14725 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
.sym 14727 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 14728 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 14729 lvds_clock_$glb_clk
.sym 14730 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 14731 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3]
.sym 14732 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
.sym 14733 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 14734 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3]
.sym 14735 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 14736 w_smi_data_output[4]
.sym 14737 w_smi_data_output[3]
.sym 14738 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
.sym 14748 w_rx_fifo_pulled_data[15]
.sym 14750 w_rx_fifo_pulled_data[13]
.sym 14752 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 14755 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
.sym 14757 tx_fifo.wr_addr[1]
.sym 14758 tx_fifo.rd_addr_gray_wr[2]
.sym 14760 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 14762 tx_fifo.rd_addr[6]
.sym 14763 tx_fifo.rd_addr[1]
.sym 14764 i_sck$SB_IO_IN
.sym 14766 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 14772 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
.sym 14773 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 14774 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
.sym 14776 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
.sym 14780 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
.sym 14781 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
.sym 14782 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 14783 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 14784 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
.sym 14787 smi_ctrl_ins.r_fifo_pulled_data[28]
.sym 14788 smi_ctrl_ins.r_fifo_pulled_data[20]
.sym 14789 tx_fifo.rd_addr[1]
.sym 14791 smi_ctrl_ins.int_cnt_rx[3]
.sym 14792 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0]
.sym 14794 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 14795 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0]
.sym 14797 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 14798 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
.sym 14799 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 14800 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1]
.sym 14802 smi_ctrl_ins.int_cnt_rx[4]
.sym 14805 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 14806 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 14807 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 14808 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0]
.sym 14811 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
.sym 14812 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 14813 tx_fifo.rd_addr[1]
.sym 14814 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0]
.sym 14818 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 14823 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
.sym 14824 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
.sym 14826 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
.sym 14830 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1]
.sym 14838 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 14841 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
.sym 14842 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 14843 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
.sym 14844 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
.sym 14847 smi_ctrl_ins.int_cnt_rx[4]
.sym 14848 smi_ctrl_ins.r_fifo_pulled_data[28]
.sym 14849 smi_ctrl_ins.int_cnt_rx[3]
.sym 14850 smi_ctrl_ins.r_fifo_pulled_data[20]
.sym 14851 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 14852 lvds_clock_$glb_clk
.sym 14853 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 14854 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 14855 tx_fifo.rd_addr_gray_wr[9]
.sym 14856 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
.sym 14857 tx_fifo.rd_addr_gray_wr[7]
.sym 14858 tx_fifo.rd_addr_gray_wr[4]
.sym 14859 tx_fifo.rd_addr_gray_wr[1]
.sym 14860 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
.sym 14861 tx_fifo.rd_addr_gray_wr_r[1]
.sym 14865 w_fetch
.sym 14867 w_smi_data_output[3]
.sym 14868 rx_fifo.mem_q.0.3_WDATA_3
.sym 14870 rx_fifo.wr_addr[0]
.sym 14874 rx_fifo.wr_addr[8]
.sym 14875 i_rst_b$SB_IO_IN
.sym 14876 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 14881 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 14885 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 14886 i_ss$SB_IO_IN
.sym 14889 tx_fifo.rd_addr_gray_wr[9]
.sym 14897 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 14900 smi_ctrl_ins.int_cnt_rx[4]
.sym 14902 smi_ctrl_ins.int_cnt_rx[3]
.sym 14906 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 14907 tx_fifo.rd_addr[5]
.sym 14908 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 14910 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 14911 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 14912 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
.sym 14914 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 14918 tx_fifo.rd_addr_gray_wr_r[1]
.sym 14920 smi_ctrl_ins.r_fifo_pulled_data[27]
.sym 14921 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0]
.sym 14922 tx_fifo.rd_addr[6]
.sym 14925 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 14926 smi_ctrl_ins.r_fifo_pulled_data[19]
.sym 14928 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 14929 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 14930 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 14931 tx_fifo.rd_addr_gray_wr_r[1]
.sym 14934 smi_ctrl_ins.int_cnt_rx[3]
.sym 14935 smi_ctrl_ins.r_fifo_pulled_data[27]
.sym 14936 smi_ctrl_ins.int_cnt_rx[4]
.sym 14937 smi_ctrl_ins.r_fifo_pulled_data[19]
.sym 14941 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
.sym 14943 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 14946 tx_fifo.rd_addr[5]
.sym 14947 tx_fifo.rd_addr[6]
.sym 14948 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0]
.sym 14959 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 14961 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 14974 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 14975 r_counter_$glb_clk
.sym 14976 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 14977 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
.sym 14979 spi_if_ins.spi.r_rx_done
.sym 14980 tx_fifo.full_o_SB_LUT4_I1_O[1]
.sym 14981 tx_fifo.full_o_SB_LUT4_I1_O[0]
.sym 14982 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
.sym 14983 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
.sym 14984 smi_ctrl_ins.r_fifo_pulled_data[19]
.sym 14992 w_rx_fifo_pulled_data[12]
.sym 14993 $PACKER_VCC_NET
.sym 14994 rx_fifo.rd_addr[2]
.sym 14995 rx_fifo.wr_addr[1]
.sym 14996 rx_fifo.rd_addr[1]
.sym 14997 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 15008 rx_fifo.wr_addr[4]
.sym 15020 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 15021 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 15022 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 15023 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
.sym 15024 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 15026 tx_fifo.wr_addr[1]
.sym 15038 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 15045 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 15053 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 15057 tx_fifo.wr_addr[1]
.sym 15063 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 15065 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 15071 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
.sym 15075 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 15093 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 15096 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 15097 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 15098 r_counter_$glb_clk
.sym 15099 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 15100 spi_if_ins.spi.r3_rx_done
.sym 15102 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 15104 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 15105 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 15106 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 15107 spi_if_ins.spi.r2_rx_done
.sym 15111 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E
.sym 15112 rx_fifo.mem_i.0.0_WDATA_3
.sym 15113 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 15114 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 15115 rx_fifo.wr_addr[2]
.sym 15116 rx_fifo.wr_addr[1]
.sym 15118 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 15120 rx_fifo.mem_i.0.0_WDATA_2
.sym 15126 $PACKER_VCC_NET
.sym 15132 w_tx_fifo_full
.sym 15133 i_ss$SB_IO_IN
.sym 15135 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 15144 tx_fifo.wr_addr_gray[2]
.sym 15145 tx_fifo.wr_addr_gray[5]
.sym 15148 tx_fifo.wr_addr_gray[7]
.sym 15150 tx_fifo.wr_addr_gray[0]
.sym 15151 tx_fifo.wr_addr_gray_rd[5]
.sym 15174 tx_fifo.wr_addr_gray[0]
.sym 15186 tx_fifo.wr_addr_gray[5]
.sym 15204 tx_fifo.wr_addr_gray_rd[5]
.sym 15213 tx_fifo.wr_addr_gray[7]
.sym 15218 tx_fifo.wr_addr_gray[2]
.sym 15221 lvds_clock_$glb_clk
.sym 15225 tx_fifo.rd_addr_gray_wr[0]
.sym 15226 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 15235 rx_fifo.rd_addr[9]
.sym 15236 rx_fifo.rd_addr[1]
.sym 15238 rx_fifo.mem_i.0.0_WDATA
.sym 15244 rx_fifo.rd_addr[2]
.sym 15250 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
.sym 15251 tx_fifo.rd_addr[1]
.sym 15255 w_tx_data_smi[2]
.sym 15258 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 15277 tx_fifo.rd_addr[1]
.sym 15291 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 15311 tx_fifo.rd_addr[1]
.sym 15343 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
.sym 15344 lvds_clock_$glb_clk
.sym 15345 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 15346 w_tx_data_smi[1]
.sym 15347 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0]
.sym 15348 w_tx_data_smi[2]
.sym 15349 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
.sym 15350 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 15351 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
.sym 15353 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
.sym 15358 rx_fifo.wr_addr[5]
.sym 15361 rx_fifo.wr_addr[4]
.sym 15363 rx_fifo.wr_addr[0]
.sym 15366 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 15368 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 15371 w_fetch
.sym 15379 w_tx_data_smi[1]
.sym 15380 $PACKER_VCC_NET
.sym 15381 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
.sym 15391 spi_if_ins.spi.r_tx_bit_count[0]
.sym 15392 spi_if_ins.r_tx_data_valid
.sym 15396 $PACKER_VCC_NET
.sym 15400 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 15403 i_ss$SB_IO_IN
.sym 15404 $PACKER_VCC_NET
.sym 15405 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 15413 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
.sym 15414 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 15419 $nextpnr_ICESTORM_LC_9$O
.sym 15422 spi_if_ins.spi.r_tx_bit_count[0]
.sym 15425 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3
.sym 15427 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 15428 $PACKER_VCC_NET
.sym 15433 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
.sym 15434 $PACKER_VCC_NET
.sym 15435 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3
.sym 15439 spi_if_ins.spi.r_tx_bit_count[0]
.sym 15440 $PACKER_VCC_NET
.sym 15441 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 15444 spi_if_ins.spi.r_tx_bit_count[0]
.sym 15451 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 15452 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
.sym 15453 spi_if_ins.spi.r_tx_bit_count[0]
.sym 15462 spi_if_ins.r_tx_data_valid
.sym 15463 i_ss$SB_IO_IN
.sym 15466 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 15467 r_counter_$glb_clk
.sym 15468 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 15469 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
.sym 15470 spi_if_ins.spi.r_tx_byte[4]
.sym 15471 spi_if_ins.spi.r_tx_byte[2]
.sym 15472 spi_if_ins.spi.r_tx_byte[3]
.sym 15473 spi_if_ins.spi.r_tx_byte[6]
.sym 15474 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
.sym 15475 spi_if_ins.spi.r_tx_byte[1]
.sym 15476 spi_if_ins.spi.r_tx_byte[0]
.sym 15485 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 15486 spi_if_ins.r_tx_byte[7]
.sym 15489 rx_fifo.rd_addr[1]
.sym 15490 rx_fifo.wr_addr[1]
.sym 15491 $PACKER_VCC_NET
.sym 15492 rx_fifo.wr_addr[2]
.sym 15493 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 15494 spi_if_ins.r_tx_byte[0]
.sym 15497 w_fetch
.sym 15498 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
.sym 15500 spi_if_ins.r_tx_byte[3]
.sym 15502 spi_if_ins.r_tx_byte[1]
.sym 15503 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 15512 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
.sym 15517 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
.sym 15521 i_rst_b$SB_IO_IN
.sym 15523 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
.sym 15525 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
.sym 15526 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 15530 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 15531 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 15533 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 15534 w_smi_read_req
.sym 15537 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
.sym 15543 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 15551 w_smi_read_req
.sym 15562 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
.sym 15564 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 15567 i_rst_b$SB_IO_IN
.sym 15568 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
.sym 15569 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 15570 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 15581 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
.sym 15586 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
.sym 15587 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 15588 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 15589 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
.sym 15590 r_counter_$glb_clk
.sym 15591 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
.sym 15592 w_ioc[2]
.sym 15593 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 15595 i_button_SB_LUT4_I0_O[1]
.sym 15596 w_ioc[4]
.sym 15597 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
.sym 15598 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 15599 w_ioc[3]
.sym 15603 i_rst_b$SB_IO_IN
.sym 15604 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
.sym 15607 i_rst_b$SB_IO_IN
.sym 15608 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
.sym 15613 spi_if_ins.r_tx_byte[7]
.sym 15615 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
.sym 15617 spi_if_ins.r_tx_byte[2]
.sym 15618 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
.sym 15619 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 15620 w_rx_data[6]
.sym 15622 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
.sym 15624 spi_if_ins.r_tx_byte[4]
.sym 15625 w_fetch
.sym 15626 w_rx_data[2]
.sym 15627 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 15634 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
.sym 15635 spi_if_ins.o_data_in_SB_DFFE_Q_E
.sym 15636 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
.sym 15637 spi_if_ins.w_rx_data[2]
.sym 15639 spi_if_ins.w_rx_data[6]
.sym 15642 w_cs[2]
.sym 15643 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
.sym 15644 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 15645 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 15646 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 15647 w_fetch
.sym 15649 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 15656 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
.sym 15659 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
.sym 15663 i_rst_b$SB_IO_IN
.sym 15664 i_rst_b$SB_IO_IN
.sym 15667 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
.sym 15668 i_rst_b$SB_IO_IN
.sym 15669 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
.sym 15673 spi_if_ins.w_rx_data[2]
.sym 15678 i_rst_b$SB_IO_IN
.sym 15679 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
.sym 15680 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 15681 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 15684 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
.sym 15686 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
.sym 15687 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 15697 i_rst_b$SB_IO_IN
.sym 15698 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
.sym 15699 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 15704 spi_if_ins.w_rx_data[6]
.sym 15708 w_fetch
.sym 15709 w_cs[2]
.sym 15710 i_rst_b$SB_IO_IN
.sym 15711 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 15712 spi_if_ins.o_data_in_SB_DFFE_Q_E
.sym 15713 r_counter_$glb_clk
.sym 15715 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
.sym 15716 spi_if_ins.r_tx_byte[5]
.sym 15717 spi_if_ins.r_tx_byte[4]
.sym 15718 spi_if_ins.r_tx_byte[3]
.sym 15719 spi_if_ins.r_tx_byte[1]
.sym 15721 i_button_SB_LUT4_I0_I3[2]
.sym 15722 spi_if_ins.r_tx_byte[6]
.sym 15727 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
.sym 15728 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 15729 spi_if_ins.o_data_in_SB_DFFE_Q_E
.sym 15733 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 15737 w_rx_fifo_full
.sym 15740 i_button_SB_LUT4_I0_I3[3]
.sym 15741 i_button_SB_LUT4_I0_O[1]
.sym 15742 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 15743 w_tx_data_smi[2]
.sym 15744 i_button_SB_LUT4_I0_I3[2]
.sym 15745 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 15746 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
.sym 15747 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 15748 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
.sym 15749 io_pmod_out[1]$SB_IO_OUT
.sym 15757 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 15758 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 15762 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 15765 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 15766 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 15770 w_load
.sym 15773 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
.sym 15774 w_cs[0]
.sym 15775 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 15780 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
.sym 15783 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
.sym 15784 i_rst_b$SB_IO_IN
.sym 15785 w_fetch
.sym 15789 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 15790 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 15791 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 15792 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 15795 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 15796 w_fetch
.sym 15797 w_load
.sym 15798 w_cs[0]
.sym 15801 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
.sym 15819 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
.sym 15820 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 15821 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 15826 i_rst_b$SB_IO_IN
.sym 15828 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
.sym 15831 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 15832 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 15833 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
.sym 15835 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 15836 r_counter_$glb_clk
.sym 15838 r_tx_data[5]
.sym 15839 r_tx_data[1]
.sym 15840 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
.sym 15841 r_tx_data[6]
.sym 15842 i_button_SB_LUT4_I0_O[2]
.sym 15843 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
.sym 15844 r_tx_data[4]
.sym 15845 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 15846 o_led1_SB_DFFER_Q_E
.sym 15850 w_cs[3]
.sym 15851 i_button_SB_LUT4_I0_I3[2]
.sym 15854 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 15855 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 15856 w_cs[2]
.sym 15858 w_load
.sym 15859 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 15862 o_led0_SB_LUT4_I1_O[1]
.sym 15863 w_cs[0]
.sym 15865 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 15866 i_button_SB_LUT4_I0_I3[0]
.sym 15867 o_rx_h_tx_l$SB_IO_OUT
.sym 15869 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
.sym 15870 i_button$SB_IO_IN
.sym 15871 w_fetch
.sym 15872 w_tx_data_smi[1]
.sym 15873 o_led0_SB_LUT4_I1_O[3]
.sym 15879 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
.sym 15880 w_tx_data_io[5]
.sym 15881 w_cs[0]
.sym 15882 w_cs[1]
.sym 15883 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 15887 w_cs[2]
.sym 15888 w_load
.sym 15890 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
.sym 15891 o_rx_h_tx_l$SB_IO_OUT
.sym 15893 i_button_SB_LUT4_I0_I3[2]
.sym 15895 w_fetch
.sym 15897 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 15898 i_rst_b$SB_IO_IN
.sym 15899 i_button_SB_LUT4_I0_O[2]
.sym 15900 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
.sym 15901 i_button_SB_LUT4_I0_O[1]
.sym 15902 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 15906 w_cs[3]
.sym 15907 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 15908 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 15910 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 15912 i_button_SB_LUT4_I0_O[1]
.sym 15913 o_rx_h_tx_l$SB_IO_OUT
.sym 15914 i_button_SB_LUT4_I0_O[2]
.sym 15919 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
.sym 15921 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 15924 w_cs[0]
.sym 15925 w_cs[1]
.sym 15926 w_cs[3]
.sym 15927 w_cs[2]
.sym 15930 w_cs[2]
.sym 15931 w_fetch
.sym 15932 i_button_SB_LUT4_I0_I3[2]
.sym 15933 w_load
.sym 15936 w_fetch
.sym 15937 w_cs[1]
.sym 15939 i_rst_b$SB_IO_IN
.sym 15948 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 15949 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 15950 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 15951 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 15954 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
.sym 15956 w_tx_data_io[5]
.sym 15957 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 15958 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
.sym 15959 r_counter_$glb_clk
.sym 15961 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[2]
.sym 15962 w_tx_data_io[0]
.sym 15963 o_led1_SB_LUT4_I1_O[2]
.sym 15964 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
.sym 15965 o_led0_SB_LUT4_I1_O[2]
.sym 15966 w_tx_data_io[1]
.sym 15967 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[2]
.sym 15968 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 15978 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 15980 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E
.sym 15982 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 15984 w_load
.sym 15985 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
.sym 15991 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
.sym 15993 spi_if_ins.r_tx_byte[0]
.sym 15995 o_tr_vc1_b$SB_IO_OUT
.sym 16002 w_tx_data_io[7]
.sym 16004 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1]
.sym 16005 w_tx_data_io[2]
.sym 16006 i_button_SB_LUT4_I0_I3[1]
.sym 16007 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
.sym 16008 i_button_SB_LUT4_I0_I3[3]
.sym 16009 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 16012 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2]
.sym 16013 i_button_SB_LUT4_I0_O[1]
.sym 16014 i_button_SB_LUT4_I0_I3[2]
.sym 16015 w_tx_data_smi[2]
.sym 16017 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 16018 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 16019 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 16020 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
.sym 16022 w_fetch
.sym 16023 w_cs[0]
.sym 16025 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 16026 i_button_SB_LUT4_I0_I3[0]
.sym 16029 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
.sym 16030 o_rx_h_tx_l_b$SB_IO_OUT
.sym 16031 sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2]
.sym 16033 o_tr_vc1$SB_IO_OUT
.sym 16035 w_tx_data_io[7]
.sym 16036 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
.sym 16038 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 16041 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2]
.sym 16042 o_tr_vc1$SB_IO_OUT
.sym 16044 i_button_SB_LUT4_I0_O[1]
.sym 16047 i_button_SB_LUT4_I0_I3[3]
.sym 16048 i_button_SB_LUT4_I0_I3[0]
.sym 16049 i_button_SB_LUT4_I0_I3[1]
.sym 16050 i_button_SB_LUT4_I0_I3[2]
.sym 16059 w_fetch
.sym 16061 sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2]
.sym 16062 w_cs[0]
.sym 16065 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 16066 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 16067 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 16068 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 16071 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1]
.sym 16072 w_tx_data_io[2]
.sym 16073 w_tx_data_smi[2]
.sym 16074 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 16078 i_button_SB_LUT4_I0_O[1]
.sym 16079 o_rx_h_tx_l_b$SB_IO_OUT
.sym 16080 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
.sym 16081 io_ctrl_ins.o_data_out_SB_DFFE_Q_E
.sym 16082 r_counter_$glb_clk
.sym 16084 o_tr_vc2$SB_IO_OUT
.sym 16085 o_shdn_tx_lna$SB_IO_OUT
.sym 16086 o_rx_h_tx_l$SB_IO_OUT
.sym 16087 o_tr_vc1_b$SB_IO_OUT
.sym 16088 o_rx_h_tx_l_b$SB_IO_OUT
.sym 16089 o_shdn_rx_lna$SB_IO_OUT
.sym 16090 io_ctrl_ins.mixer_en_state
.sym 16091 o_tr_vc1$SB_IO_OUT
.sym 16096 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 16098 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2]
.sym 16102 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 16106 i_rst_b$SB_IO_IN
.sym 16110 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0]
.sym 16112 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
.sym 16113 spi_if_ins.r_tx_byte[2]
.sym 16114 w_rx_data[2]
.sym 16117 w_rx_data[6]
.sym 16118 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 16119 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 16125 i_glob_clock$SB_IO_IN
.sym 16127 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 16131 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[2]
.sym 16133 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
.sym 16135 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
.sym 16136 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 16139 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3]
.sym 16141 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0]
.sym 16151 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
.sym 16155 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[0]
.sym 16158 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 16159 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
.sym 16160 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0]
.sym 16161 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3]
.sym 16189 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[2]
.sym 16190 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[0]
.sym 16191 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 16200 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
.sym 16202 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
.sym 16203 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 16204 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 16205 i_glob_clock$SB_IO_IN
.sym 16207 io_ctrl_ins.rf_pin_state[4]
.sym 16208 io_ctrl_ins.rf_pin_state[2]
.sym 16209 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1]
.sym 16210 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
.sym 16211 io_ctrl_ins.rf_pin_state[1]
.sym 16212 io_ctrl_ins.rf_pin_state[0]
.sym 16213 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
.sym 16214 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 16224 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 16228 o_shdn_tx_lna$SB_IO_OUT
.sym 16229 i_glob_clock$SB_IO_IN
.sym 16232 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
.sym 16237 o_shdn_rx_lna$SB_IO_OUT
.sym 16256 r_tx_data[2]
.sym 16259 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
.sym 16261 r_tx_data[0]
.sym 16263 r_tx_data[7]
.sym 16272 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 16284 r_tx_data[2]
.sym 16301 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 16307 r_tx_data[0]
.sym 16326 r_tx_data[7]
.sym 16327 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
.sym 16328 r_counter_$glb_clk
.sym 16330 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 16331 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0]
.sym 16332 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0]
.sym 16334 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0]
.sym 16336 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 16337 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
.sym 16344 w_rx_data[2]
.sym 16345 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
.sym 16349 i_rst_b$SB_IO_IN
.sym 16354 i_button$SB_IO_IN
.sym 16356 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
.sym 16358 i_button_SB_LUT4_I0_I3[0]
.sym 16362 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
.sym 16388 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0]
.sym 16390 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 16391 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0]
.sym 16394 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
.sym 16395 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 16397 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0]
.sym 16398 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E
.sym 16401 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 16410 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 16412 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 16417 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 16419 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
.sym 16422 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0]
.sym 16424 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 16429 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0]
.sym 16431 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 16434 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 16436 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 16440 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0]
.sym 16443 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 16450 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E
.sym 16451 r_counter_$glb_clk
.sym 16452 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 16453 i_button_SB_LUT4_I0_I3[0]
.sym 16455 i_button$SB_IO_IN
.sym 16462 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 16497 lvds_clock
.sym 16519 lvds_clock
.sym 16554 tx_fifo.wr_addr[0]
.sym 16555 tx_fifo.wr_addr[2]
.sym 16556 tx_fifo.wr_addr[6]
.sym 16560 tx_fifo.wr_addr[1]
.sym 16585 o_smi_write_req$SB_IO_OUT
.sym 16599 tx_fifo.wr_addr[5]
.sym 16602 tx_fifo.wr_addr[7]
.sym 16608 tx_fifo.wr_addr[3]
.sym 16613 tx_fifo.wr_addr[2]
.sym 16615 tx_fifo.wr_addr[4]
.sym 16618 tx_fifo.wr_addr[1]
.sym 16620 tx_fifo.wr_addr[0]
.sym 16622 tx_fifo.wr_addr[6]
.sym 16627 $nextpnr_ICESTORM_LC_5$O
.sym 16630 tx_fifo.wr_addr[0]
.sym 16633 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3
.sym 16636 tx_fifo.wr_addr[1]
.sym 16637 tx_fifo.wr_addr[0]
.sym 16639 tx_fifo.wr_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3
.sym 16642 tx_fifo.wr_addr[2]
.sym 16643 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3
.sym 16645 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
.sym 16647 tx_fifo.wr_addr[3]
.sym 16649 tx_fifo.wr_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3
.sym 16651 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 16654 tx_fifo.wr_addr[4]
.sym 16655 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
.sym 16657 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 16659 tx_fifo.wr_addr[5]
.sym 16661 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 16663 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3
.sym 16666 tx_fifo.wr_addr[6]
.sym 16667 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 16669 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 16672 tx_fifo.wr_addr[7]
.sym 16673 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3
.sym 16682 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1]
.sym 16683 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 16684 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 16685 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 16686 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 16687 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
.sym 16688 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 16698 tx_fifo.wr_addr[1]
.sym 16703 i_sck$SB_IO_IN
.sym 16723 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 16725 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 16730 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
.sym 16734 w_smi_data_output[4]
.sym 16735 tx_fifo.wr_addr[4]
.sym 16736 $PACKER_VCC_NET
.sym 16737 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 16743 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 16747 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 16753 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 16758 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 16759 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 16760 tx_fifo.wr_addr[9]
.sym 16761 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
.sym 16763 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 16769 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 16773 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 16782 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
.sym 16788 tx_fifo.wr_addr[8]
.sym 16790 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 16792 tx_fifo.wr_addr[8]
.sym 16794 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 16798 tx_fifo.wr_addr[9]
.sym 16800 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 16804 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 16811 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
.sym 16818 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 16821 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
.sym 16827 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 16834 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 16837 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 16838 r_counter_$glb_clk
.sym 16839 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 16840 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
.sym 16841 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3]
.sym 16842 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0]
.sym 16843 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1]
.sym 16844 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3]
.sym 16845 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 16846 tx_fifo.wr_addr[4]
.sym 16847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 16852 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 16856 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 16863 i_ss$SB_IO_IN
.sym 16871 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 16874 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 16881 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 16882 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
.sym 16883 i_rst_b$SB_IO_IN
.sym 16884 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3]
.sym 16885 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 16886 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 16887 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
.sym 16888 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
.sym 16889 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 16890 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 16891 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 16892 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 16893 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
.sym 16895 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
.sym 16896 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
.sym 16897 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[1]
.sym 16898 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
.sym 16899 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 16901 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 16902 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 16904 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[3]
.sym 16905 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
.sym 16906 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
.sym 16908 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 16909 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 16912 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 16914 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 16915 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
.sym 16916 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 16917 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3]
.sym 16920 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 16921 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 16922 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 16923 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
.sym 16926 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[1]
.sym 16927 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
.sym 16928 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 16929 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[3]
.sym 16932 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 16933 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 16934 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 16938 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 16939 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 16940 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 16941 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
.sym 16945 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
.sym 16946 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
.sym 16950 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
.sym 16951 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
.sym 16956 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
.sym 16957 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 16959 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 16960 i_rst_b$SB_IO_IN
.sym 16961 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 16963 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2]
.sym 16964 smi_ctrl_ins.r_fifo_push_1
.sym 16965 w_tx_fifo_full
.sym 16966 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0]
.sym 16967 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
.sym 16968 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
.sym 16969 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
.sym 16970 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 16978 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 16979 w_rx_fifo_pulled_data[14]
.sym 16980 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 16983 rx_fifo.wr_addr[4]
.sym 16984 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 16986 rx_fifo.wr_addr[9]
.sym 16988 i_ss$SB_IO_IN
.sym 16991 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
.sym 16997 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 17008 tx_fifo.rd_addr_gray_wr[4]
.sym 17011 tx_fifo.rd_addr_gray_wr[2]
.sym 17015 tx_fifo.rd_addr_gray_wr[7]
.sym 17024 tx_fifo.rd_addr_gray[4]
.sym 17025 tx_fifo.rd_addr_gray_wr[1]
.sym 17030 tx_fifo.rd_addr_gray[1]
.sym 17032 tx_fifo.rd_addr_gray[7]
.sym 17033 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
.sym 17037 tx_fifo.rd_addr_gray_wr[7]
.sym 17046 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
.sym 17052 tx_fifo.rd_addr_gray_wr[2]
.sym 17057 tx_fifo.rd_addr_gray[7]
.sym 17061 tx_fifo.rd_addr_gray[4]
.sym 17067 tx_fifo.rd_addr_gray[1]
.sym 17075 tx_fifo.rd_addr_gray_wr[4]
.sym 17081 tx_fifo.rd_addr_gray_wr[1]
.sym 17084 r_counter_$glb_clk
.sym 17087 spi_if_ins.spi.r_rx_bit_count[1]
.sym 17088 spi_if_ins.spi.r_rx_bit_count[2]
.sym 17089 spi_if_ins.spi.r_rx_bit_count[0]
.sym 17093 o_smi_read_req$SB_IO_OUT
.sym 17100 rx_fifo.rd_addr[5]
.sym 17102 i_ss$SB_IO_IN
.sym 17103 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 17108 smi_ctrl_ins.r_fifo_push
.sym 17109 w_tx_fifo_full
.sym 17111 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 17112 smi_ctrl_ins.r_fifo_pulled_data[31]
.sym 17118 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
.sym 17127 i_sck$SB_IO_IN
.sym 17129 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
.sym 17130 tx_fifo.full_o_SB_LUT4_I1_O[1]
.sym 17131 i_ss$SB_IO_IN
.sym 17133 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
.sym 17134 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 17137 w_tx_fifo_full
.sym 17138 tx_fifo.wr_addr[1]
.sym 17139 i_ss$SB_IO_IN
.sym 17140 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 17141 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 17143 tx_fifo.full_o_SB_LUT4_I1_O[2]
.sym 17144 spi_if_ins.spi.r_rx_bit_count[1]
.sym 17145 spi_if_ins.spi.r_rx_bit_count[2]
.sym 17147 tx_fifo.full_o_SB_LUT4_I1_O[0]
.sym 17148 smi_ctrl_ins.r_fifo_pulled_data[19]
.sym 17154 spi_if_ins.spi.r_rx_bit_count[0]
.sym 17160 spi_if_ins.spi.r_rx_bit_count[0]
.sym 17161 spi_if_ins.spi.r_rx_bit_count[1]
.sym 17162 spi_if_ins.spi.r_rx_bit_count[2]
.sym 17163 i_ss$SB_IO_IN
.sym 17174 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
.sym 17178 w_tx_fifo_full
.sym 17180 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 17181 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 17184 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 17185 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 17186 tx_fifo.wr_addr[1]
.sym 17187 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 17190 tx_fifo.full_o_SB_LUT4_I1_O[1]
.sym 17191 tx_fifo.full_o_SB_LUT4_I1_O[2]
.sym 17193 tx_fifo.full_o_SB_LUT4_I1_O[0]
.sym 17196 spi_if_ins.spi.r_rx_bit_count[0]
.sym 17198 spi_if_ins.spi.r_rx_bit_count[2]
.sym 17199 spi_if_ins.spi.r_rx_bit_count[1]
.sym 17204 smi_ctrl_ins.r_fifo_pulled_data[19]
.sym 17206 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
.sym 17207 i_sck$SB_IO_IN
.sym 17208 i_ss$SB_IO_IN
.sym 17209 smi_ctrl_ins.r_fifo_pulled_data[28]
.sym 17210 smi_ctrl_ins.r_fifo_pulled_data[17]
.sym 17212 smi_ctrl_ins.r_fifo_pulled_data[29]
.sym 17213 smi_ctrl_ins.r_fifo_pulled_data[30]
.sym 17214 smi_ctrl_ins.r_fifo_pulled_data[19]
.sym 17216 smi_ctrl_ins.r_fifo_pulled_data[31]
.sym 17219 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0]
.sym 17223 w_rx_fifo_pulled_data[16]
.sym 17227 i_sck$SB_IO_IN
.sym 17232 rx_fifo.wr_addr[8]
.sym 17234 smi_ctrl_ins.r_fifo_pulled_data[30]
.sym 17236 spi_if_ins.w_rx_data[6]
.sym 17238 $PACKER_VCC_NET
.sym 17240 w_smi_data_direction
.sym 17243 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
.sym 17250 spi_if_ins.spi.r3_rx_done
.sym 17252 spi_if_ins.spi.r_rx_done
.sym 17254 tx_fifo.rd_addr_gray_wr[9]
.sym 17259 i_ss$SB_IO_IN
.sym 17260 tx_fifo.rd_addr_gray_wr[0]
.sym 17264 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
.sym 17273 spi_if_ins.spi.r2_rx_done
.sym 17284 spi_if_ins.spi.r2_rx_done
.sym 17297 spi_if_ins.spi.r3_rx_done
.sym 17298 spi_if_ins.spi.r2_rx_done
.sym 17307 i_ss$SB_IO_IN
.sym 17308 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
.sym 17316 tx_fifo.rd_addr_gray_wr[9]
.sym 17320 tx_fifo.rd_addr_gray_wr[0]
.sym 17328 spi_if_ins.spi.r_rx_done
.sym 17330 r_counter_$glb_clk
.sym 17332 spi_if_ins.spi.r_rx_byte[0]
.sym 17333 spi_if_ins.spi.r_rx_byte[7]
.sym 17334 spi_if_ins.spi.r_rx_byte[2]
.sym 17335 spi_if_ins.spi.r_rx_byte[4]
.sym 17336 spi_if_ins.spi.r_rx_byte[5]
.sym 17337 spi_if_ins.spi.r_rx_byte[3]
.sym 17338 spi_if_ins.spi.r_rx_byte[1]
.sym 17339 spi_if_ins.spi.r_rx_byte[6]
.sym 17344 rx_fifo.rd_addr[0]
.sym 17346 rx_fifo.rd_addr[5]
.sym 17347 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 17350 tx_fifo.rd_addr_gray_wr[9]
.sym 17351 $PACKER_VCC_NET
.sym 17357 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 17362 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 17363 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 17377 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 17383 tx_fifo.rd_addr_gray[0]
.sym 17421 tx_fifo.rd_addr_gray[0]
.sym 17427 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 17453 r_counter_$glb_clk
.sym 17455 spi_if_ins.w_rx_data[2]
.sym 17456 spi_if_ins.w_rx_data[6]
.sym 17457 spi_if_ins.w_rx_data[0]
.sym 17458 spi_if_ins.w_rx_data[4]
.sym 17459 spi_if_ins.w_rx_data[5]
.sym 17460 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 17461 spi_if_ins.w_rx_data[1]
.sym 17462 spi_if_ins.w_rx_data[3]
.sym 17468 spi_if_ins.spi.r_temp_rx_byte[3]
.sym 17469 rx_fifo.wr_addr[9]
.sym 17470 spi_if_ins.spi.r_temp_rx_byte[1]
.sym 17471 rx_fifo.wr_addr[4]
.sym 17472 spi_if_ins.spi.r_temp_rx_byte[5]
.sym 17473 i_sck$SB_IO_IN
.sym 17476 spi_if_ins.spi.r_temp_rx_byte[6]
.sym 17478 spi_if_ins.spi.r_temp_rx_byte[0]
.sym 17486 spi_if_ins.w_rx_data[3]
.sym 17488 spi_if_ins.w_rx_data[2]
.sym 17489 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 17490 spi_if_ins.w_rx_data[6]
.sym 17496 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
.sym 17498 spi_if_ins.spi.r_tx_byte[2]
.sym 17499 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 17501 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
.sym 17503 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
.sym 17505 w_tx_fifo_full
.sym 17506 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
.sym 17507 spi_if_ins.spi.r_tx_byte[3]
.sym 17508 spi_if_ins.spi.r_tx_bit_count[0]
.sym 17509 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
.sym 17514 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
.sym 17516 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 17517 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
.sym 17521 w_smi_read_req
.sym 17522 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 17523 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
.sym 17524 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 17525 o_led0_SB_LUT4_I1_O[1]
.sym 17531 w_tx_fifo_full
.sym 17536 w_smi_read_req
.sym 17544 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 17547 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
.sym 17548 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
.sym 17549 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 17553 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
.sym 17554 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
.sym 17555 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
.sym 17556 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
.sym 17559 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
.sym 17560 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 17561 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 17571 spi_if_ins.spi.r_tx_bit_count[0]
.sym 17572 spi_if_ins.spi.r_tx_byte[3]
.sym 17574 spi_if_ins.spi.r_tx_byte[2]
.sym 17575 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
.sym 17576 r_counter_$glb_clk
.sym 17577 o_led0_SB_LUT4_I1_O[1]
.sym 17580 spi_if_ins.spi.r_tx_byte[7]
.sym 17581 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
.sym 17582 spi_if_ins.spi.r_tx_byte[5]
.sym 17583 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
.sym 17593 rx_fifo.rd_addr[5]
.sym 17599 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 17600 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 17601 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 17602 spi_if_ins.w_rx_data[0]
.sym 17604 spi_if_ins.w_rx_data[4]
.sym 17606 spi_if_ins.w_rx_data[5]
.sym 17608 o_led0_SB_LUT4_I1_O[1]
.sym 17610 w_rx_data[4]
.sym 17613 i_button_SB_LUT4_I0_O[1]
.sym 17623 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
.sym 17631 spi_if_ins.spi.r_tx_byte[6]
.sym 17635 spi_if_ins.r_tx_byte[1]
.sym 17638 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 17639 spi_if_ins.spi.r_tx_bit_count[0]
.sym 17640 spi_if_ins.r_tx_byte[2]
.sym 17641 spi_if_ins.r_tx_byte[3]
.sym 17642 spi_if_ins.r_tx_byte[6]
.sym 17643 spi_if_ins.r_tx_byte[0]
.sym 17644 spi_if_ins.spi.r_tx_byte[4]
.sym 17646 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
.sym 17647 spi_if_ins.r_tx_byte[4]
.sym 17649 spi_if_ins.spi.r_tx_byte[1]
.sym 17650 spi_if_ins.spi.r_tx_byte[0]
.sym 17652 spi_if_ins.spi.r_tx_byte[4]
.sym 17653 spi_if_ins.spi.r_tx_byte[6]
.sym 17654 spi_if_ins.spi.r_tx_bit_count[0]
.sym 17655 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 17658 spi_if_ins.r_tx_byte[4]
.sym 17667 spi_if_ins.r_tx_byte[2]
.sym 17673 spi_if_ins.r_tx_byte[3]
.sym 17677 spi_if_ins.r_tx_byte[6]
.sym 17682 spi_if_ins.spi.r_tx_byte[1]
.sym 17683 spi_if_ins.spi.r_tx_byte[0]
.sym 17685 spi_if_ins.spi.r_tx_bit_count[0]
.sym 17690 spi_if_ins.r_tx_byte[1]
.sym 17694 spi_if_ins.r_tx_byte[0]
.sym 17698 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
.sym 17699 r_counter_$glb_clk
.sym 17700 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
.sym 17701 w_rx_data[1]
.sym 17702 o_led0_SB_LUT4_I1_O[1]
.sym 17703 w_rx_data[4]
.sym 17704 w_rx_data[7]
.sym 17705 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
.sym 17706 w_rx_data[3]
.sym 17707 w_rx_data[0]
.sym 17708 w_rx_data[5]
.sym 17715 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 17720 io_pmod_out[1]$SB_IO_OUT
.sym 17723 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
.sym 17725 i_glob_clock$SB_IO_IN
.sym 17726 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
.sym 17728 spi_if_ins.r_tx_byte[6]
.sym 17729 spi_if_ins.spi.r_tx_bit_count[0]
.sym 17730 w_rx_data[0]
.sym 17731 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
.sym 17732 spi_if_ins.r_tx_byte[5]
.sym 17734 w_rx_data[1]
.sym 17735 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 17736 spi_if_ins.w_rx_data[6]
.sym 17742 w_ioc[2]
.sym 17744 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 17748 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 17749 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1]
.sym 17751 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 17754 w_ioc[4]
.sym 17756 spi_if_ins.w_rx_data[3]
.sym 17758 spi_if_ins.w_rx_data[2]
.sym 17761 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 17762 spi_if_ins.w_rx_data[0]
.sym 17764 spi_if_ins.w_rx_data[4]
.sym 17773 w_ioc[3]
.sym 17777 spi_if_ins.w_rx_data[2]
.sym 17782 w_ioc[2]
.sym 17783 w_ioc[4]
.sym 17784 w_ioc[3]
.sym 17793 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 17796 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 17801 spi_if_ins.w_rx_data[4]
.sym 17806 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 17807 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1]
.sym 17813 spi_if_ins.w_rx_data[0]
.sym 17819 spi_if_ins.w_rx_data[3]
.sym 17821 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 17822 r_counter_$glb_clk
.sym 17824 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2]
.sym 17825 w_cs[1]
.sym 17827 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 17828 w_cs[3]
.sym 17829 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 17830 w_cs[2]
.sym 17831 o_led1_SB_LUT4_I1_I3[3]
.sym 17836 w_fetch
.sym 17837 w_rx_data[0]
.sym 17839 w_rx_data[7]
.sym 17840 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 17843 w_rx_data[1]
.sym 17844 i_button_SB_LUT4_I0_O[1]
.sym 17845 o_led0_SB_LUT4_I1_O[1]
.sym 17848 w_rx_data[4]
.sym 17850 io_ctrl_ins.pmod_dir_state[7]
.sym 17851 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 17852 i_button_SB_LUT4_I0_I3[2]
.sym 17854 w_rx_data[3]
.sym 17856 w_rx_data[0]
.sym 17857 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 17858 w_rx_data[5]
.sym 17859 w_cs[1]
.sym 17866 r_tx_data[1]
.sym 17867 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
.sym 17868 r_tx_data[6]
.sym 17871 r_tx_data[4]
.sym 17872 r_tx_data[3]
.sym 17873 r_tx_data[5]
.sym 17874 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 17875 w_cs[0]
.sym 17879 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 17882 w_cs[1]
.sym 17885 w_cs[3]
.sym 17887 w_cs[2]
.sym 17893 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 17898 w_cs[2]
.sym 17899 w_cs[1]
.sym 17900 w_cs[3]
.sym 17901 w_cs[0]
.sym 17906 r_tx_data[5]
.sym 17912 r_tx_data[4]
.sym 17918 r_tx_data[3]
.sym 17923 r_tx_data[1]
.sym 17935 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 17936 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 17937 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 17940 r_tx_data[6]
.sym 17944 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
.sym 17945 r_counter_$glb_clk
.sym 17947 o_led1_SB_LUT4_I1_O[3]
.sym 17948 o_led1_SB_LUT4_I1_I3[0]
.sym 17949 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[0]
.sym 17950 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2]
.sym 17951 io_ctrl_ins.pmod_dir_state[1]
.sym 17952 io_ctrl_ins.pmod_dir_state[5]
.sym 17953 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
.sym 17954 io_ctrl_ins.pmod_dir_state[7]
.sym 17960 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 17961 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
.sym 17964 o_led1_SB_LUT4_I1_I3[3]
.sym 17966 w_fetch
.sym 17967 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 17968 r_tx_data[3]
.sym 17972 w_rx_data[7]
.sym 17973 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 17974 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 17976 w_load
.sym 17979 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 17980 i_button_SB_LUT4_I0_I3[2]
.sym 17982 w_load
.sym 17988 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0]
.sym 17989 w_cs[1]
.sym 17990 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 17991 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
.sym 17992 w_cs[3]
.sym 17993 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
.sym 17994 i_button_SB_LUT4_I0_I3[3]
.sym 17995 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2]
.sym 17996 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
.sym 17997 i_glob_clock$SB_IO_IN
.sym 17999 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 18000 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 18001 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
.sym 18002 w_cs[2]
.sym 18003 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 18005 i_button$SB_IO_IN
.sym 18006 w_cs[0]
.sym 18007 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 18010 io_ctrl_ins.pmod_dir_state[7]
.sym 18011 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
.sym 18012 i_button_SB_LUT4_I0_I3[2]
.sym 18018 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
.sym 18019 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 18021 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0]
.sym 18022 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2]
.sym 18023 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 18028 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
.sym 18029 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
.sym 18030 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 18034 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 18035 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 18036 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 18039 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
.sym 18040 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 18041 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
.sym 18042 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 18045 i_button_SB_LUT4_I0_I3[3]
.sym 18046 i_button$SB_IO_IN
.sym 18047 io_ctrl_ins.pmod_dir_state[7]
.sym 18048 i_button_SB_LUT4_I0_I3[2]
.sym 18051 w_cs[2]
.sym 18052 w_cs[3]
.sym 18053 w_cs[1]
.sym 18054 w_cs[0]
.sym 18057 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 18058 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
.sym 18059 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 18060 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
.sym 18063 w_cs[1]
.sym 18064 w_cs[3]
.sym 18065 w_cs[2]
.sym 18066 w_cs[0]
.sym 18067 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 18068 i_glob_clock$SB_IO_IN
.sym 18070 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
.sym 18071 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2]
.sym 18072 i_button_SB_LUT4_I0_I3[1]
.sym 18073 io_ctrl_ins.pmod_dir_state[3]
.sym 18074 o_led1_SB_LUT4_I1_I2[1]
.sym 18075 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2]
.sym 18076 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 18077 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 18083 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
.sym 18085 w_rx_data[2]
.sym 18088 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
.sym 18089 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
.sym 18092 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0]
.sym 18093 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3]
.sym 18094 o_led1$SB_IO_OUT
.sym 18095 w_rx_data[4]
.sym 18096 o_led0_SB_LUT4_I1_O[1]
.sym 18097 w_cs[1]
.sym 18099 o_led1_SB_LUT4_I1_O[0]
.sym 18101 i_button_SB_LUT4_I0_O[1]
.sym 18105 o_led0_SB_LUT4_I1_O[0]
.sym 18112 o_led0_SB_LUT4_I1_O[0]
.sym 18113 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
.sym 18114 io_pmod_out[1]$SB_IO_OUT
.sym 18115 o_led0_SB_LUT4_I1_O[1]
.sym 18116 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
.sym 18117 w_tx_data_smi[1]
.sym 18118 o_led0_SB_LUT4_I1_O[3]
.sym 18119 o_led1_SB_LUT4_I1_O[3]
.sym 18120 io_pmod_out[0]$SB_IO_OUT
.sym 18121 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 18123 o_led1_SB_LUT4_I1_O[0]
.sym 18124 o_shdn_rx_lna$SB_IO_OUT
.sym 18125 io_ctrl_ins.mixer_en_state
.sym 18126 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 18127 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 18128 w_tx_data_io[0]
.sym 18129 o_led1_SB_LUT4_I1_O[2]
.sym 18131 o_led0_SB_LUT4_I1_O[2]
.sym 18132 w_tx_data_io[1]
.sym 18134 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 18135 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[2]
.sym 18136 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0]
.sym 18137 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1]
.sym 18139 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 18140 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
.sym 18145 w_tx_data_io[0]
.sym 18146 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 18147 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
.sym 18150 o_led0_SB_LUT4_I1_O[0]
.sym 18151 o_led0_SB_LUT4_I1_O[2]
.sym 18152 o_led0_SB_LUT4_I1_O[3]
.sym 18153 o_led0_SB_LUT4_I1_O[1]
.sym 18156 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 18157 io_pmod_out[1]$SB_IO_OUT
.sym 18158 o_shdn_rx_lna$SB_IO_OUT
.sym 18159 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 18162 w_tx_data_io[1]
.sym 18163 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 18164 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1]
.sym 18165 w_tx_data_smi[1]
.sym 18168 io_pmod_out[0]$SB_IO_OUT
.sym 18169 io_ctrl_ins.mixer_en_state
.sym 18170 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 18171 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 18174 o_led1_SB_LUT4_I1_O[0]
.sym 18175 o_led1_SB_LUT4_I1_O[2]
.sym 18176 o_led1_SB_LUT4_I1_O[3]
.sym 18177 o_led0_SB_LUT4_I1_O[1]
.sym 18180 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0]
.sym 18181 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1]
.sym 18183 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[2]
.sym 18186 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 18187 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 18188 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 18190 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
.sym 18191 r_counter_$glb_clk
.sym 18192 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
.sym 18193 io_ctrl_ins.rf_pin_state[3]
.sym 18194 io_ctrl_ins.rf_pin_state[5]
.sym 18195 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E
.sym 18196 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
.sym 18197 io_ctrl_ins.rf_pin_state[6]
.sym 18198 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
.sym 18199 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2]
.sym 18200 io_ctrl_ins.rf_pin_state[7]
.sym 18206 io_pmod_out[0]$SB_IO_OUT
.sym 18208 io_pmod_out[3]$SB_IO_OUT
.sym 18209 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 18210 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 18213 i_button_SB_LUT4_I0_I3[3]
.sym 18216 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 18217 o_rx_h_tx_l_b$SB_IO_OUT
.sym 18218 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
.sym 18219 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
.sym 18223 w_rx_data[0]
.sym 18226 w_rx_data[1]
.sym 18234 io_ctrl_ins.rf_pin_state[4]
.sym 18236 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
.sym 18238 io_ctrl_ins.rf_pin_state[1]
.sym 18243 io_ctrl_ins.rf_pin_state[2]
.sym 18247 io_ctrl_ins.rf_pin_state[0]
.sym 18249 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 18250 io_ctrl_ins.rf_pin_state[3]
.sym 18251 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 18254 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
.sym 18256 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2]
.sym 18257 io_ctrl_ins.rf_pin_state[7]
.sym 18258 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 18259 io_ctrl_ins.rf_pin_state[5]
.sym 18262 io_ctrl_ins.rf_pin_state[6]
.sym 18267 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
.sym 18268 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 18269 io_ctrl_ins.rf_pin_state[3]
.sym 18270 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 18273 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 18274 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
.sym 18275 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 18276 io_ctrl_ins.rf_pin_state[2]
.sym 18280 io_ctrl_ins.rf_pin_state[7]
.sym 18281 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 18282 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 18285 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 18286 io_ctrl_ins.rf_pin_state[4]
.sym 18287 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 18288 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2]
.sym 18291 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 18292 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 18294 io_ctrl_ins.rf_pin_state[6]
.sym 18297 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 18299 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 18300 io_ctrl_ins.rf_pin_state[1]
.sym 18303 io_ctrl_ins.rf_pin_state[0]
.sym 18304 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 18305 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
.sym 18306 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 18309 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 18310 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2]
.sym 18311 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 18312 io_ctrl_ins.rf_pin_state[5]
.sym 18313 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
.sym 18314 r_counter_$glb_clk
.sym 18316 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 18317 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 18318 o_led1_SB_LUT4_I1_O[0]
.sym 18319 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3[2]
.sym 18320 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
.sym 18321 o_led0_SB_LUT4_I1_O[0]
.sym 18323 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
.sym 18328 o_tr_vc2$SB_IO_OUT
.sym 18332 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
.sym 18334 o_rx_h_tx_l$SB_IO_OUT
.sym 18335 o_led0_SB_LUT4_I1_O[3]
.sym 18338 w_fetch
.sym 18340 w_rx_data[4]
.sym 18344 w_rx_data[0]
.sym 18345 i_config[2]$SB_IO_IN
.sym 18346 w_rx_data[5]
.sym 18357 i_rst_b$SB_IO_IN
.sym 18359 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1]
.sym 18365 w_rx_data[4]
.sym 18367 w_rx_data[2]
.sym 18370 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
.sym 18374 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 18375 o_led1_SB_LUT4_I1_O[0]
.sym 18377 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
.sym 18378 o_led0_SB_LUT4_I1_O[0]
.sym 18381 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 18383 w_rx_data[0]
.sym 18384 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
.sym 18386 w_rx_data[1]
.sym 18388 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
.sym 18393 w_rx_data[4]
.sym 18398 w_rx_data[2]
.sym 18402 i_rst_b$SB_IO_IN
.sym 18403 o_led0_SB_LUT4_I1_O[0]
.sym 18404 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
.sym 18405 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 18409 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
.sym 18414 w_rx_data[1]
.sym 18420 w_rx_data[0]
.sym 18426 o_led1_SB_LUT4_I1_O[0]
.sym 18428 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1]
.sym 18432 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 18433 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
.sym 18434 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 18435 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
.sym 18436 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
.sym 18437 r_counter_$glb_clk
.sym 18439 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
.sym 18454 o_tr_vc1_b$SB_IO_OUT
.sym 18460 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
.sym 18482 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 18487 w_rx_data[2]
.sym 18488 w_rx_data[6]
.sym 18496 w_rx_data[1]
.sym 18500 w_rx_data[4]
.sym 18504 w_rx_data[0]
.sym 18506 w_rx_data[5]
.sym 18514 w_rx_data[5]
.sym 18521 w_rx_data[2]
.sym 18528 w_rx_data[0]
.sym 18537 w_rx_data[1]
.sym 18551 w_rx_data[4]
.sym 18555 w_rx_data[6]
.sym 18559 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 18560 r_counter_$glb_clk
.sym 18561 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 18562 i_config[1]$SB_IO_IN
.sym 18564 i_config[2]$SB_IO_IN
.sym 18636 w_smi_data_output[4]
.sym 18638 w_smi_data_direction
.sym 18639 o_smi_write_req$SB_IO_OUT
.sym 18642 $PACKER_VCC_NET
.sym 18648 w_smi_data_direction
.sym 18656 w_smi_data_output[4]
.sym 18657 o_smi_write_req$SB_IO_OUT
.sym 18658 $PACKER_VCC_NET
.sym 18694 $PACKER_VCC_NET
.sym 18696 w_smi_data_direction
.sym 18704 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
.sym 18705 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
.sym 18709 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
.sym 18714 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 18728 tx_fifo.wr_addr[0]
.sym 18743 tx_fifo.wr_addr[0]
.sym 18750 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
.sym 18757 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
.sym 18780 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
.sym 18782 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 18783 r_counter_$glb_clk
.sym 18784 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 18785 i_smi_soe_se$SB_IO_IN
.sym 18800 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
.sym 18804 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 18818 w_smi_data_input[7]
.sym 18842 w_smi_data_output[5]
.sym 18843 $PACKER_VCC_NET
.sym 18844 tx_fifo.wr_addr[2]
.sym 18845 tx_fifo.rd_addr_gray_wr_r[8]
.sym 18846 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 18848 i_smi_soe_se$SB_IO_IN
.sym 18868 tx_fifo.wr_addr[2]
.sym 18869 tx_fifo.wr_addr[6]
.sym 18871 tx_fifo.wr_addr[3]
.sym 18872 tx_fifo.wr_addr[4]
.sym 18873 tx_fifo.wr_addr[7]
.sym 18878 tx_fifo.wr_addr[5]
.sym 18880 tx_fifo.wr_addr[8]
.sym 18881 tx_fifo.wr_addr[1]
.sym 18898 $nextpnr_ICESTORM_LC_2$O
.sym 18901 tx_fifo.wr_addr[1]
.sym 18904 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 18906 tx_fifo.wr_addr[2]
.sym 18908 tx_fifo.wr_addr[1]
.sym 18910 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 18912 tx_fifo.wr_addr[3]
.sym 18914 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 18916 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 18918 tx_fifo.wr_addr[4]
.sym 18920 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 18922 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 18924 tx_fifo.wr_addr[5]
.sym 18926 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 18928 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 18931 tx_fifo.wr_addr[6]
.sym 18932 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 18934 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 18936 tx_fifo.wr_addr[7]
.sym 18938 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 18940 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3
.sym 18943 tx_fifo.wr_addr[8]
.sym 18944 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 18949 w_rx_fifo_pulled_data[12]
.sym 18953 w_rx_fifo_pulled_data[14]
.sym 18960 i_ss$SB_IO_IN
.sym 18978 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 18979 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 18981 rx_fifo.wr_addr[6]
.sym 18983 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
.sym 18984 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3
.sym 18990 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1]
.sym 18991 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 18993 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
.sym 18994 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 18995 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
.sym 18996 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
.sym 18998 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 18999 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 19000 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 19001 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 19003 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 19005 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 19006 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 19007 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
.sym 19009 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3]
.sym 19011 tx_fifo.rd_addr_gray_wr_r[8]
.sym 19014 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3]
.sym 19015 tx_fifo.wr_addr[9]
.sym 19019 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
.sym 19020 i_rst_b$SB_IO_IN
.sym 19023 tx_fifo.wr_addr[9]
.sym 19025 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3
.sym 19028 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 19029 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
.sym 19030 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1]
.sym 19034 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 19035 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
.sym 19036 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3]
.sym 19037 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 19040 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 19041 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
.sym 19042 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
.sym 19043 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3]
.sym 19047 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 19048 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 19049 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 19053 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 19054 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 19055 tx_fifo.rd_addr_gray_wr_r[8]
.sym 19060 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 19065 i_rst_b$SB_IO_IN
.sym 19067 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
.sym 19068 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 19069 r_counter_$glb_clk
.sym 19070 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 19072 w_rx_fifo_pulled_data[13]
.sym 19076 w_rx_fifo_pulled_data[15]
.sym 19081 w_rx_data[3]
.sym 19086 rx_fifo.wr_addr[3]
.sym 19096 rx_fifo.mem_q.0.3_WDATA_2
.sym 19099 w_smi_read_req
.sym 19101 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 19106 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 19112 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
.sym 19113 smi_ctrl_ins.r_fifo_push_1
.sym 19114 w_tx_fifo_full
.sym 19115 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0]
.sym 19117 smi_ctrl_ins.r_fifo_push
.sym 19118 tx_fifo.rd_addr_gray_wr_r[8]
.sym 19119 tx_fifo.rd_addr_gray_wr_r[1]
.sym 19120 tx_fifo.wr_addr[2]
.sym 19122 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0]
.sym 19123 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1]
.sym 19125 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
.sym 19126 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 19128 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3]
.sym 19131 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 19132 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
.sym 19133 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 19135 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 19136 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2]
.sym 19137 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
.sym 19141 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
.sym 19142 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
.sym 19143 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
.sym 19145 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
.sym 19146 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 19147 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
.sym 19148 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 19151 smi_ctrl_ins.r_fifo_push
.sym 19157 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
.sym 19158 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 19159 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
.sym 19160 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
.sym 19163 tx_fifo.wr_addr[2]
.sym 19164 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
.sym 19165 tx_fifo.rd_addr_gray_wr_r[1]
.sym 19169 w_tx_fifo_full
.sym 19170 smi_ctrl_ins.r_fifo_push_1
.sym 19172 smi_ctrl_ins.r_fifo_push
.sym 19175 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 19176 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
.sym 19177 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 19178 tx_fifo.rd_addr_gray_wr_r[8]
.sym 19181 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
.sym 19182 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0]
.sym 19183 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3]
.sym 19184 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2]
.sym 19187 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0]
.sym 19190 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1]
.sym 19192 r_counter_$glb_clk
.sym 19193 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 19195 w_rx_fifo_pulled_data[16]
.sym 19199 w_rx_fifo_pulled_data[18]
.sym 19205 w_rx_data[0]
.sym 19213 rx_fifo.rd_addr[0]
.sym 19214 tx_fifo.rd_addr_gray_wr_r[8]
.sym 19215 rx_fifo.mem_q.0.3_WDATA_1
.sym 19217 $PACKER_VCC_NET
.sym 19219 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 19220 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 19221 w_rx_fifo_pulled_data[18]
.sym 19223 smi_ctrl_ins.r_fifo_pulled_data[28]
.sym 19224 o_smi_read_req$SB_IO_OUT
.sym 19225 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 19227 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 19229 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 19237 w_tx_fifo_full
.sym 19244 i_sck$SB_IO_IN
.sym 19245 spi_if_ins.spi.r_rx_bit_count[2]
.sym 19246 spi_if_ins.spi.r_rx_bit_count[0]
.sym 19248 i_ss$SB_IO_IN
.sym 19254 w_smi_data_direction
.sym 19259 w_smi_read_req
.sym 19260 spi_if_ins.spi.r_rx_bit_count[1]
.sym 19267 $nextpnr_ICESTORM_LC_4$O
.sym 19270 spi_if_ins.spi.r_rx_bit_count[0]
.sym 19273 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3
.sym 19275 spi_if_ins.spi.r_rx_bit_count[1]
.sym 19277 spi_if_ins.spi.r_rx_bit_count[0]
.sym 19281 spi_if_ins.spi.r_rx_bit_count[2]
.sym 19283 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3
.sym 19289 spi_if_ins.spi.r_rx_bit_count[0]
.sym 19310 w_smi_read_req
.sym 19312 w_smi_data_direction
.sym 19313 w_tx_fifo_full
.sym 19315 i_sck$SB_IO_IN
.sym 19316 i_ss$SB_IO_IN
.sym 19318 w_rx_fifo_pulled_data[17]
.sym 19322 w_rx_fifo_pulled_data[19]
.sym 19327 w_rx_data[5]
.sym 19335 rx_fifo.wr_addr[5]
.sym 19338 rx_fifo.wr_addr[9]
.sym 19339 rx_fifo.wr_addr[0]
.sym 19340 rx_fifo.wr_addr[3]
.sym 19341 $PACKER_VCC_NET
.sym 19344 w_rx_fifo_pulled_data[29]
.sym 19347 $PACKER_VCC_NET
.sym 19350 i_smi_soe_se$SB_IO_IN
.sym 19352 w_rx_fifo_pulled_data[31]
.sym 19359 w_rx_fifo_pulled_data[31]
.sym 19368 w_rx_fifo_pulled_data[29]
.sym 19375 w_rx_fifo_pulled_data[28]
.sym 19379 w_rx_fifo_pulled_data[19]
.sym 19383 w_rx_fifo_pulled_data[17]
.sym 19387 w_rx_fifo_pulled_data[30]
.sym 19394 w_rx_fifo_pulled_data[28]
.sym 19398 w_rx_fifo_pulled_data[17]
.sym 19409 w_rx_fifo_pulled_data[29]
.sym 19415 w_rx_fifo_pulled_data[30]
.sym 19421 w_rx_fifo_pulled_data[19]
.sym 19435 w_rx_fifo_pulled_data[31]
.sym 19437 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
.sym 19438 smi_ctrl_ins.soe_and_reset_$glb_clk
.sym 19439 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 19441 w_rx_fifo_pulled_data[28]
.sym 19445 w_rx_fifo_pulled_data[30]
.sym 19450 o_led1_SB_LUT4_I1_I3[3]
.sym 19464 rx_fifo.mem_i.0.3_WDATA_1
.sym 19473 rx_fifo.wr_addr[6]
.sym 19475 rx_fifo.mem_i.0.0_WDATA_1
.sym 19481 i_mosi$SB_IO_IN
.sym 19483 spi_if_ins.spi.r_temp_rx_byte[4]
.sym 19485 spi_if_ins.spi.r_temp_rx_byte[3]
.sym 19487 spi_if_ins.spi.r_temp_rx_byte[5]
.sym 19489 spi_if_ins.spi.r_temp_rx_byte[2]
.sym 19490 i_sck$SB_IO_IN
.sym 19491 spi_if_ins.spi.r_temp_rx_byte[6]
.sym 19492 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 19493 spi_if_ins.spi.r_temp_rx_byte[0]
.sym 19495 spi_if_ins.spi.r_temp_rx_byte[1]
.sym 19516 i_mosi$SB_IO_IN
.sym 19520 spi_if_ins.spi.r_temp_rx_byte[6]
.sym 19527 spi_if_ins.spi.r_temp_rx_byte[1]
.sym 19533 spi_if_ins.spi.r_temp_rx_byte[3]
.sym 19540 spi_if_ins.spi.r_temp_rx_byte[4]
.sym 19546 spi_if_ins.spi.r_temp_rx_byte[2]
.sym 19551 spi_if_ins.spi.r_temp_rx_byte[0]
.sym 19557 spi_if_ins.spi.r_temp_rx_byte[5]
.sym 19560 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 19561 i_sck$SB_IO_IN
.sym 19564 w_rx_fifo_pulled_data[29]
.sym 19568 w_rx_fifo_pulled_data[31]
.sym 19575 i_mosi$SB_IO_IN
.sym 19577 spi_if_ins.spi.r_temp_rx_byte[4]
.sym 19585 spi_if_ins.spi.r_temp_rx_byte[2]
.sym 19587 rx_fifo.rd_addr[9]
.sym 19589 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 19591 spi_if_ins.w_rx_data[1]
.sym 19592 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 19593 spi_if_ins.w_rx_data[3]
.sym 19595 spi_if_ins.w_rx_data[2]
.sym 19597 spi_if_ins.w_rx_data[6]
.sym 19598 rx_fifo.mem_i.0.3_WDATA
.sym 19604 spi_if_ins.spi.r_rx_byte[0]
.sym 19607 spi_if_ins.spi.r_rx_byte[4]
.sym 19608 spi_if_ins.spi.r_rx_byte[5]
.sym 19610 spi_if_ins.spi.r_rx_byte[1]
.sym 19613 spi_if_ins.spi.r_rx_byte[7]
.sym 19614 spi_if_ins.spi.r_rx_byte[2]
.sym 19615 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 19617 spi_if_ins.spi.r_rx_byte[3]
.sym 19619 spi_if_ins.spi.r_rx_byte[6]
.sym 19640 spi_if_ins.spi.r_rx_byte[2]
.sym 19646 spi_if_ins.spi.r_rx_byte[6]
.sym 19649 spi_if_ins.spi.r_rx_byte[0]
.sym 19655 spi_if_ins.spi.r_rx_byte[4]
.sym 19663 spi_if_ins.spi.r_rx_byte[5]
.sym 19668 spi_if_ins.spi.r_rx_byte[7]
.sym 19673 spi_if_ins.spi.r_rx_byte[1]
.sym 19682 spi_if_ins.spi.r_rx_byte[3]
.sym 19683 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 19684 r_counter_$glb_clk
.sym 19697 w_rx_data[4]
.sym 19699 i_glob_clock$SB_IO_IN
.sym 19709 rx_fifo.rd_addr[0]
.sym 19710 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 19711 w_rx_data[0]
.sym 19713 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 19714 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 19717 o_led0_SB_LUT4_I1_O[1]
.sym 19720 rx_fifo.rd_addr[2]
.sym 19721 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 19740 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
.sym 19742 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 19745 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
.sym 19746 spi_if_ins.r_tx_byte[5]
.sym 19747 spi_if_ins.spi.r_tx_byte[5]
.sym 19748 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
.sym 19751 spi_if_ins.spi.r_tx_bit_count[0]
.sym 19753 spi_if_ins.spi.r_tx_byte[7]
.sym 19758 spi_if_ins.r_tx_byte[7]
.sym 19774 spi_if_ins.r_tx_byte[7]
.sym 19780 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
.sym 19787 spi_if_ins.r_tx_byte[5]
.sym 19790 spi_if_ins.spi.r_tx_byte[7]
.sym 19791 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 19792 spi_if_ins.spi.r_tx_bit_count[0]
.sym 19793 spi_if_ins.spi.r_tx_byte[5]
.sym 19806 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
.sym 19807 r_counter_$glb_clk
.sym 19808 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
.sym 19825 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 19829 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 19834 w_cs[2]
.sym 19835 w_rx_data[3]
.sym 19837 w_rx_data[0]
.sym 19840 w_cs[1]
.sym 19843 o_led0_SB_LUT4_I1_O[1]
.sym 19850 spi_if_ins.w_rx_data[5]
.sym 19851 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 19854 spi_if_ins.w_rx_data[0]
.sym 19856 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 19859 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 19860 spi_if_ins.w_rx_data[6]
.sym 19861 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 19863 spi_if_ins.w_rx_data[1]
.sym 19864 spi_if_ins.w_rx_data[4]
.sym 19865 spi_if_ins.w_rx_data[3]
.sym 19868 spi_if_ins.o_data_in_SB_DFFE_Q_E
.sym 19885 spi_if_ins.w_rx_data[1]
.sym 19889 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 19890 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 19892 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 19898 spi_if_ins.w_rx_data[4]
.sym 19902 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 19909 spi_if_ins.w_rx_data[5]
.sym 19910 spi_if_ins.w_rx_data[6]
.sym 19916 spi_if_ins.w_rx_data[3]
.sym 19919 spi_if_ins.w_rx_data[0]
.sym 19926 spi_if_ins.w_rx_data[5]
.sym 19929 spi_if_ins.o_data_in_SB_DFFE_Q_E
.sym 19930 r_counter_$glb_clk
.sym 19949 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
.sym 19950 w_load
.sym 19952 w_rx_data[7]
.sym 19955 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 19957 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
.sym 19959 w_rx_data[7]
.sym 19963 w_fetch
.sym 19964 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2]
.sym 19977 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
.sym 19982 w_cs[1]
.sym 19984 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 19985 w_cs[3]
.sym 19986 spi_if_ins.w_rx_data[5]
.sym 19987 w_cs[2]
.sym 19988 spi_if_ins.w_rx_data[6]
.sym 19989 w_ioc[2]
.sym 19993 w_cs[0]
.sym 19995 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 19998 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 20000 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 20001 w_ioc[4]
.sym 20003 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 20004 w_ioc[3]
.sym 20006 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 20007 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 20008 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 20013 spi_if_ins.w_rx_data[5]
.sym 20015 spi_if_ins.w_rx_data[6]
.sym 20024 w_cs[3]
.sym 20025 w_cs[1]
.sym 20026 w_cs[2]
.sym 20027 w_cs[0]
.sym 20030 spi_if_ins.w_rx_data[5]
.sym 20032 spi_if_ins.w_rx_data[6]
.sym 20037 w_ioc[3]
.sym 20038 w_ioc[4]
.sym 20039 w_ioc[2]
.sym 20042 spi_if_ins.w_rx_data[6]
.sym 20044 spi_if_ins.w_rx_data[5]
.sym 20049 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 20050 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 20051 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 20052 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 20053 r_counter_$glb_clk
.sym 20054 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
.sym 20071 w_cs[1]
.sym 20075 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 20076 o_led1$SB_IO_OUT
.sym 20079 w_rx_data[6]
.sym 20082 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 20086 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 20089 o_led1_SB_LUT4_I1_I3[0]
.sym 20090 o_led1_SB_LUT4_I1_I3[3]
.sym 20096 w_rx_data[1]
.sym 20099 io_ctrl_ins.pmod_dir_state[3]
.sym 20100 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3]
.sym 20102 w_rx_data[5]
.sym 20104 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2]
.sym 20107 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 20108 w_rx_data[0]
.sym 20109 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2]
.sym 20110 w_rx_data[2]
.sym 20111 o_led1_SB_LUT4_I1_I3[3]
.sym 20116 io_ctrl_ins.pmod_dir_state[1]
.sym 20119 w_rx_data[7]
.sym 20121 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 20123 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
.sym 20124 o_led1$SB_IO_OUT
.sym 20126 i_button_SB_LUT4_I0_I3[2]
.sym 20129 o_led1_SB_LUT4_I1_I3[3]
.sym 20130 o_led1$SB_IO_OUT
.sym 20131 io_ctrl_ins.pmod_dir_state[1]
.sym 20132 i_button_SB_LUT4_I0_I3[2]
.sym 20135 w_rx_data[0]
.sym 20142 w_rx_data[2]
.sym 20147 i_button_SB_LUT4_I0_I3[2]
.sym 20148 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3]
.sym 20149 io_ctrl_ins.pmod_dir_state[3]
.sym 20150 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2]
.sym 20155 w_rx_data[1]
.sym 20160 w_rx_data[5]
.sym 20165 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 20166 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2]
.sym 20167 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 20173 w_rx_data[7]
.sym 20175 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
.sym 20176 r_counter_$glb_clk
.sym 20196 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[0]
.sym 20198 o_rx_h_tx_l_b$SB_IO_OUT
.sym 20201 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
.sym 20205 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2]
.sym 20206 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
.sym 20209 o_led0_SB_LUT4_I1_O[1]
.sym 20210 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
.sym 20211 o_led1$SB_IO_OUT
.sym 20220 w_rx_data[4]
.sym 20221 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
.sym 20222 i_button_SB_LUT4_I0_I3[3]
.sym 20223 i_config[2]$SB_IO_IN
.sym 20224 io_ctrl_ins.pmod_dir_state[5]
.sym 20225 io_pmod_out[3]$SB_IO_OUT
.sym 20227 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 20228 w_load
.sym 20229 w_cs[1]
.sym 20231 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 20232 i_button_SB_LUT4_I0_I3[2]
.sym 20233 w_fetch
.sym 20234 w_rx_data[3]
.sym 20235 i_rst_b$SB_IO_IN
.sym 20239 w_rx_data[6]
.sym 20241 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 20246 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 20250 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 20252 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 20254 i_button_SB_LUT4_I0_I3[2]
.sym 20258 i_button_SB_LUT4_I0_I3[3]
.sym 20259 i_config[2]$SB_IO_IN
.sym 20260 io_ctrl_ins.pmod_dir_state[5]
.sym 20261 i_button_SB_LUT4_I0_I3[2]
.sym 20266 w_rx_data[6]
.sym 20273 w_rx_data[3]
.sym 20277 w_rx_data[4]
.sym 20283 io_pmod_out[3]$SB_IO_OUT
.sym 20284 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 20285 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 20288 w_load
.sym 20289 w_cs[1]
.sym 20290 i_rst_b$SB_IO_IN
.sym 20291 w_fetch
.sym 20296 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 20297 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 20298 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
.sym 20299 r_counter_$glb_clk
.sym 20319 i_config[2]$SB_IO_IN
.sym 20322 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0]
.sym 20342 w_rx_data[7]
.sym 20344 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
.sym 20345 o_tr_vc1_b$SB_IO_OUT
.sym 20346 o_led1_SB_LUT4_I1_I2[1]
.sym 20348 o_led0_SB_LUT4_I1_O[1]
.sym 20349 w_cs[1]
.sym 20350 i_button_SB_LUT4_I0_I3[2]
.sym 20351 w_rx_data[6]
.sym 20352 w_load
.sym 20353 i_button_SB_LUT4_I0_O[1]
.sym 20354 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
.sym 20355 w_fetch
.sym 20356 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 20357 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
.sym 20368 w_rx_data[3]
.sym 20372 w_rx_data[5]
.sym 20378 w_rx_data[3]
.sym 20383 w_rx_data[5]
.sym 20387 w_fetch
.sym 20388 w_cs[1]
.sym 20389 o_led0_SB_LUT4_I1_O[1]
.sym 20390 w_load
.sym 20393 i_button_SB_LUT4_I0_I3[2]
.sym 20394 i_button_SB_LUT4_I0_O[1]
.sym 20395 o_tr_vc1_b$SB_IO_OUT
.sym 20396 o_led1_SB_LUT4_I1_I2[1]
.sym 20399 w_rx_data[6]
.sym 20406 i_button_SB_LUT4_I0_O[1]
.sym 20407 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 20413 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
.sym 20414 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
.sym 20418 w_rx_data[7]
.sym 20421 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
.sym 20422 r_counter_$glb_clk
.sym 20438 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
.sym 20440 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 20454 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
.sym 20467 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E
.sym 20470 w_rx_data[1]
.sym 20476 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
.sym 20477 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
.sym 20478 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
.sym 20482 w_rx_data[3]
.sym 20483 o_led1_SB_LUT4_I1_O[0]
.sym 20484 w_rx_data[0]
.sym 20491 w_rx_data[2]
.sym 20492 w_rx_data[4]
.sym 20494 o_led0_SB_LUT4_I1_O[0]
.sym 20498 o_led1_SB_LUT4_I1_O[0]
.sym 20500 o_led0_SB_LUT4_I1_O[0]
.sym 20506 w_rx_data[3]
.sym 20513 w_rx_data[1]
.sym 20517 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
.sym 20518 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
.sym 20519 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
.sym 20522 w_rx_data[4]
.sym 20530 w_rx_data[0]
.sym 20540 w_rx_data[2]
.sym 20544 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E
.sym 20545 r_counter_$glb_clk
.sym 20546 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 20563 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 20579 i_config[0]$SB_IO_IN
.sym 20591 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3[2]
.sym 20592 i_config[1]$SB_IO_IN
.sym 20599 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
.sym 20609 o_led1_SB_LUT4_I1_I3[3]
.sym 20621 i_config[1]$SB_IO_IN
.sym 20622 o_led1_SB_LUT4_I1_I3[3]
.sym 20624 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3[2]
.sym 20667 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
.sym 20668 r_counter_$glb_clk
.sym 20672 i_config[0]$SB_IO_IN
.sym 20700 o_led1$SB_IO_OUT
.sym 20748 w_smi_data_output[5]
.sym 20750 w_smi_data_direction
.sym 20751 $PACKER_VCC_NET
.sym 20757 w_smi_data_output[5]
.sym 20759 $PACKER_VCC_NET
.sym 20769 w_smi_data_direction
.sym 20770 smi_ctrl_ins.swe_and_reset
.sym 20786 rx_fifo.wr_addr[7]
.sym 20804 i_mosi$SB_IO_IN
.sym 20844 i_mosi$SB_IO_IN
.sym 20846 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
.sym 20847 smi_ctrl_ins.tx_reg_state[1]
.sym 20848 smi_ctrl_ins.tx_reg_state[2]
.sym 20849 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
.sym 20850 smi_ctrl_ins.tx_reg_state[3]
.sym 20851 smi_ctrl_ins.tx_reg_state[0]
.sym 20852 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
.sym 20900 o_miso_$_TBUF__Y_E
.sym 20925 i_rst_b$SB_IO_IN
.sym 20936 rx_fifo.wr_addr[1]
.sym 20937 rx_fifo.wr_addr[5]
.sym 20938 w_rx_fifo_pulled_data[12]
.sym 20947 int_miso
.sym 20986 smi_ctrl_ins.r_fifo_push
.sym 21034 w_smi_data_input[7]
.sym 21038 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 21039 o_miso_$_TBUF__Y_E
.sym 21042 i_rst_b$SB_IO_IN
.sym 21046 int_miso
.sym 21048 rx_fifo.wr_addr[2]
.sym 21054 rx_fifo.wr_addr[2]
.sym 21058 $PACKER_VCC_NET
.sym 21068 rx_fifo.wr_addr[3]
.sym 21070 rx_fifo.wr_addr[6]
.sym 21071 rx_fifo.wr_addr[9]
.sym 21072 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 21076 rx_fifo.wr_addr[4]
.sym 21077 rx_fifo.wr_addr[0]
.sym 21079 rx_fifo.wr_addr[1]
.sym 21080 rx_fifo.wr_addr[5]
.sym 21081 rx_fifo.wr_addr[8]
.sym 21082 rx_fifo.wr_addr[7]
.sym 21083 rx_fifo.mem_q.0.3_WDATA_2
.sym 21085 rx_fifo.mem_q.0.3_WDATA_3
.sym 21088 tx_fifo.rd_addr_gray_wr[8]
.sym 21093 tx_fifo.rd_addr_gray_wr_r[8]
.sym 21102 rx_fifo.wr_addr[2]
.sym 21103 rx_fifo.wr_addr[3]
.sym 21105 rx_fifo.wr_addr[4]
.sym 21106 rx_fifo.wr_addr[5]
.sym 21107 rx_fifo.wr_addr[6]
.sym 21108 rx_fifo.wr_addr[7]
.sym 21109 rx_fifo.wr_addr[8]
.sym 21110 rx_fifo.wr_addr[9]
.sym 21111 rx_fifo.wr_addr[1]
.sym 21112 rx_fifo.wr_addr[0]
.sym 21113 lvds_clock_$glb_clk
.sym 21114 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 21116 rx_fifo.mem_q.0.3_WDATA_3
.sym 21120 rx_fifo.mem_q.0.3_WDATA_2
.sym 21123 $PACKER_VCC_NET
.sym 21137 o_smi_read_req$SB_IO_OUT
.sym 21142 w_rx_fifo_pulled_data[15]
.sym 21150 w_rx_fifo_pulled_data[13]
.sym 21158 rx_fifo.mem_q.0.3_WDATA_1
.sym 21160 $PACKER_VCC_NET
.sym 21164 rx_fifo.rd_addr[0]
.sym 21167 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 21168 rx_fifo.rd_addr[9]
.sym 21169 rx_fifo.mem_q.0.3_WDATA
.sym 21172 rx_fifo.rd_addr[1]
.sym 21175 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 21176 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 21177 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 21178 rx_fifo.rd_addr[2]
.sym 21182 rx_fifo.rd_addr[5]
.sym 21183 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 21187 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 21188 o_miso_$_TBUF__Y_E
.sym 21204 rx_fifo.rd_addr[2]
.sym 21205 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 21207 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 21208 rx_fifo.rd_addr[5]
.sym 21209 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 21210 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 21211 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 21212 rx_fifo.rd_addr[9]
.sym 21213 rx_fifo.rd_addr[1]
.sym 21214 rx_fifo.rd_addr[0]
.sym 21215 r_counter_$glb_clk
.sym 21216 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 21217 $PACKER_VCC_NET
.sym 21221 rx_fifo.mem_q.0.3_WDATA
.sym 21225 rx_fifo.mem_q.0.3_WDATA_1
.sym 21235 tx_fifo.rd_addr_gray_wr_r[8]
.sym 21236 tx_fifo.rd_addr_gray[8]
.sym 21237 rx_fifo.mem_q.0.3_WDATA
.sym 21239 $PACKER_VCC_NET
.sym 21245 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 21252 rx_fifo.wr_addr[4]
.sym 21258 rx_fifo.wr_addr[4]
.sym 21259 rx_fifo.wr_addr[5]
.sym 21260 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 21263 rx_fifo.wr_addr[0]
.sym 21268 rx_fifo.wr_addr[9]
.sym 21270 rx_fifo.wr_addr[3]
.sym 21271 rx_fifo.wr_addr[6]
.sym 21278 $PACKER_VCC_NET
.sym 21280 rx_fifo.wr_addr[2]
.sym 21282 rx_fifo.wr_addr[7]
.sym 21283 rx_fifo.wr_addr[8]
.sym 21285 rx_fifo.mem_i.0.0_WDATA_2
.sym 21287 rx_fifo.mem_i.0.0_WDATA_3
.sym 21289 rx_fifo.wr_addr[1]
.sym 21306 rx_fifo.wr_addr[2]
.sym 21307 rx_fifo.wr_addr[3]
.sym 21309 rx_fifo.wr_addr[4]
.sym 21310 rx_fifo.wr_addr[5]
.sym 21311 rx_fifo.wr_addr[6]
.sym 21312 rx_fifo.wr_addr[7]
.sym 21313 rx_fifo.wr_addr[8]
.sym 21314 rx_fifo.wr_addr[9]
.sym 21315 rx_fifo.wr_addr[1]
.sym 21316 rx_fifo.wr_addr[0]
.sym 21317 lvds_clock_$glb_clk
.sym 21318 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 21320 rx_fifo.mem_i.0.0_WDATA_3
.sym 21324 rx_fifo.mem_i.0.0_WDATA_2
.sym 21327 $PACKER_VCC_NET
.sym 21339 rx_fifo.wr_addr[6]
.sym 21344 rx_fifo.wr_addr[1]
.sym 21346 rx_fifo.wr_addr[2]
.sym 21362 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 21363 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 21373 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 21374 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 21375 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 21378 rx_fifo.rd_addr[2]
.sym 21380 rx_fifo.rd_addr[1]
.sym 21381 rx_fifo.rd_addr[9]
.sym 21382 rx_fifo.mem_i.0.0_WDATA
.sym 21384 rx_fifo.rd_addr[0]
.sym 21386 rx_fifo.rd_addr[5]
.sym 21387 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 21389 $PACKER_VCC_NET
.sym 21391 rx_fifo.mem_i.0.0_WDATA_1
.sym 21392 spi_if_ins.spi.r_temp_rx_byte[2]
.sym 21393 spi_if_ins.spi.r_temp_rx_byte[4]
.sym 21394 spi_if_ins.spi.r_temp_rx_byte[3]
.sym 21395 spi_if_ins.spi.r_temp_rx_byte[5]
.sym 21397 spi_if_ins.spi.r_temp_rx_byte[6]
.sym 21398 spi_if_ins.spi.r_temp_rx_byte[0]
.sym 21399 spi_if_ins.spi.r_temp_rx_byte[1]
.sym 21408 rx_fifo.rd_addr[2]
.sym 21409 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 21411 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 21412 rx_fifo.rd_addr[5]
.sym 21413 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 21414 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 21415 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 21416 rx_fifo.rd_addr[9]
.sym 21417 rx_fifo.rd_addr[1]
.sym 21418 rx_fifo.rd_addr[0]
.sym 21419 r_counter_$glb_clk
.sym 21420 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 21421 $PACKER_VCC_NET
.sym 21425 rx_fifo.mem_i.0.0_WDATA
.sym 21429 rx_fifo.mem_i.0.0_WDATA_1
.sym 21446 int_miso
.sym 21448 o_miso_$_TBUF__Y_E
.sym 21450 i_rst_b$SB_IO_IN
.sym 21457 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 21462 rx_fifo.wr_addr[8]
.sym 21466 $PACKER_VCC_NET
.sym 21468 rx_fifo.mem_i.0.3_WDATA_2
.sym 21471 rx_fifo.mem_i.0.3_WDATA_3
.sym 21474 rx_fifo.wr_addr[3]
.sym 21478 rx_fifo.wr_addr[6]
.sym 21480 rx_fifo.wr_addr[4]
.sym 21482 rx_fifo.wr_addr[1]
.sym 21483 rx_fifo.wr_addr[5]
.sym 21484 rx_fifo.wr_addr[2]
.sym 21488 rx_fifo.wr_addr[9]
.sym 21489 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 21490 rx_fifo.wr_addr[7]
.sym 21492 rx_fifo.wr_addr[0]
.sym 21498 smi_ctrl_ins.soe_and_reset
.sym 21500 int_miso
.sym 21510 rx_fifo.wr_addr[2]
.sym 21511 rx_fifo.wr_addr[3]
.sym 21513 rx_fifo.wr_addr[4]
.sym 21514 rx_fifo.wr_addr[5]
.sym 21515 rx_fifo.wr_addr[6]
.sym 21516 rx_fifo.wr_addr[7]
.sym 21517 rx_fifo.wr_addr[8]
.sym 21518 rx_fifo.wr_addr[9]
.sym 21519 rx_fifo.wr_addr[1]
.sym 21520 rx_fifo.wr_addr[0]
.sym 21521 lvds_clock_$glb_clk
.sym 21522 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 21524 rx_fifo.mem_i.0.3_WDATA_3
.sym 21528 rx_fifo.mem_i.0.3_WDATA_2
.sym 21531 $PACKER_VCC_NET
.sym 21538 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 21547 rx_fifo.mem_i.0.3_WDATA_3
.sym 21554 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
.sym 21568 rx_fifo.mem_i.0.3_WDATA_1
.sym 21575 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 21576 rx_fifo.rd_addr[0]
.sym 21581 rx_fifo.rd_addr[9]
.sym 21582 rx_fifo.mem_i.0.3_WDATA
.sym 21583 rx_fifo.rd_addr[5]
.sym 21584 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 21586 rx_fifo.rd_addr[2]
.sym 21587 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 21588 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 21589 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 21591 rx_fifo.rd_addr[1]
.sym 21593 $PACKER_VCC_NET
.sym 21595 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 21601 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 21612 rx_fifo.rd_addr[2]
.sym 21613 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 21615 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 21616 rx_fifo.rd_addr[5]
.sym 21617 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 21618 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 21619 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 21620 rx_fifo.rd_addr[9]
.sym 21621 rx_fifo.rd_addr[1]
.sym 21622 rx_fifo.rd_addr[0]
.sym 21623 r_counter_$glb_clk
.sym 21624 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 21625 $PACKER_VCC_NET
.sym 21629 rx_fifo.mem_i.0.3_WDATA
.sym 21633 rx_fifo.mem_i.0.3_WDATA_1
.sym 21641 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 21642 i_smi_soe_se$SB_IO_IN
.sym 21644 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 21650 w_load
.sym 21653 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 21661 w_cs[2]
.sym 21699 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
.sym 21704 w_load
.sym 21754 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 21757 w_load
.sym 21760 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
.sym 21800 o_led1_SB_DFFER_Q_E
.sym 21805 r_tx_data[3]
.sym 21848 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 21849 spi_if_ins.w_rx_data[1]
.sym 21852 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 21855 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
.sym 21861 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 21865 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 21903 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
.sym 21904 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2]
.sym 21905 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2]
.sym 21908 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
.sym 21909 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
.sym 21948 o_led1$SB_IO_OUT
.sym 21952 w_rx_data[0]
.sym 21953 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 21956 o_shdn_tx_lna$SB_IO_OUT
.sym 21957 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
.sym 21963 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 21965 w_rx_fifo_full
.sym 21967 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
.sym 22009 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
.sym 22011 w_tx_data_io[2]
.sym 22049 w_rx_data[0]
.sym 22051 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
.sym 22057 w_rx_data[3]
.sym 22065 i_button_SB_LUT4_I0_I3[2]
.sym 22066 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
.sym 22068 o_led0$SB_IO_OUT
.sym 22106 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
.sym 22107 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
.sym 22110 o_led0_SB_LUT4_I1_O[3]
.sym 22111 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3]
.sym 22148 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
.sym 22150 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
.sym 22153 w_tx_data_io[2]
.sym 22154 w_rx_fifo_full
.sym 22159 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2]
.sym 22160 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
.sym 22171 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E
.sym 22214 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
.sym 22251 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 22252 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
.sym 22254 i_config[0]$SB_IO_IN
.sym 22256 o_led1_SB_LUT4_I1_I3[3]
.sym 22257 o_led1_SB_LUT4_I1_I3[0]
.sym 22258 o_tr_vc1$SB_IO_OUT
.sym 22356 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2]
.sym 22360 o_led0_SB_LUT4_I1_O[1]
.sym 22465 o_led0$SB_IO_OUT
.sym 22487 o_led1$SB_IO_OUT
.sym 22507 o_led1$SB_IO_OUT
.sym 22517 int_miso
.sym 22519 o_miso_$_TBUF__Y_E
.sym 22534 o_miso_$_TBUF__Y_E
.sym 22535 int_miso
.sym 22554 i_mosi$SB_IO_IN
.sym 22559 rx_fifo.wr_addr[5]
.sym 22576 i_ss$SB_IO_IN
.sym 22589 i_rst_b$SB_IO_IN
.sym 22593 o_smi_write_req$SB_IO_OUT
.sym 22617 o_smi_write_req$SB_IO_OUT
.sym 22620 i_rst_b$SB_IO_IN
.sym 22666 i_sck$SB_IO_IN
.sym 22668 i_ss$SB_IO_IN
.sym 22677 smi_ctrl_ins.w_fifo_push_trigger
.sym 22689 i_rst_b$SB_IO_IN
.sym 22695 o_smi_write_req$SB_IO_OUT
.sym 22707 i_ss$SB_IO_IN
.sym 22711 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
.sym 22720 i_sck$SB_IO_IN
.sym 22733 i_ss$SB_IO_IN
.sym 22734 smi_ctrl_ins.r_fifo_push
.sym 22740 i_sck$SB_IO_IN
.sym 22747 smi_ctrl_ins.swe_and_reset
.sym 22748 smi_ctrl_ins.tx_reg_state[1]
.sym 22749 i_rst_b$SB_IO_IN
.sym 22750 w_smi_data_input[7]
.sym 22759 smi_ctrl_ins.tx_reg_state[3]
.sym 22763 i_rst_b$SB_IO_IN
.sym 22765 smi_ctrl_ins.tx_reg_state[2]
.sym 22771 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
.sym 22774 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
.sym 22776 smi_ctrl_ins.tx_reg_state[0]
.sym 22781 smi_ctrl_ins.tx_reg_state[1]
.sym 22782 smi_ctrl_ins.tx_reg_state[2]
.sym 22783 w_smi_data_input[7]
.sym 22786 w_smi_data_input[7]
.sym 22787 smi_ctrl_ins.tx_reg_state[2]
.sym 22789 i_rst_b$SB_IO_IN
.sym 22792 smi_ctrl_ins.tx_reg_state[0]
.sym 22793 w_smi_data_input[7]
.sym 22794 i_rst_b$SB_IO_IN
.sym 22798 w_smi_data_input[7]
.sym 22799 i_rst_b$SB_IO_IN
.sym 22800 smi_ctrl_ins.tx_reg_state[3]
.sym 22801 smi_ctrl_ins.tx_reg_state[0]
.sym 22804 i_rst_b$SB_IO_IN
.sym 22805 smi_ctrl_ins.tx_reg_state[1]
.sym 22807 w_smi_data_input[7]
.sym 22811 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
.sym 22812 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
.sym 22816 i_rst_b$SB_IO_IN
.sym 22817 smi_ctrl_ins.tx_reg_state[3]
.sym 22818 smi_ctrl_ins.tx_reg_state[0]
.sym 22827 smi_ctrl_ins.swe_and_reset
.sym 22858 i_sck$SB_IO_IN
.sym 22885 smi_ctrl_ins.w_fifo_push_trigger
.sym 22917 smi_ctrl_ins.w_fifo_push_trigger
.sym 22950 r_counter_$glb_clk
.sym 22951 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 22977 i_ss$SB_IO_IN
.sym 23002 tx_fifo.rd_addr_gray[8]
.sym 23019 tx_fifo.rd_addr_gray_wr[8]
.sym 23038 tx_fifo.rd_addr_gray[8]
.sym 23070 tx_fifo.rd_addr_gray_wr[8]
.sym 23073 r_counter_$glb_clk
.sym 23104 i_sck$SB_IO_IN
.sym 23108 i_sck$SB_IO_IN
.sym 23137 i_ss$SB_IO_IN
.sym 23150 i_ss$SB_IO_IN
.sym 23362 spi_if_ins.spi.r_temp_rx_byte[2]
.sym 23364 spi_if_ins.spi.r_temp_rx_byte[3]
.sym 23368 spi_if_ins.spi.r_temp_rx_byte[0]
.sym 23373 spi_if_ins.spi.r_temp_rx_byte[5]
.sym 23377 spi_if_ins.spi.r_temp_rx_byte[1]
.sym 23378 i_sck$SB_IO_IN
.sym 23386 i_mosi$SB_IO_IN
.sym 23387 spi_if_ins.spi.r_temp_rx_byte[4]
.sym 23389 o_miso_$_TBUF__Y_E
.sym 23395 spi_if_ins.spi.r_temp_rx_byte[1]
.sym 23402 spi_if_ins.spi.r_temp_rx_byte[3]
.sym 23409 spi_if_ins.spi.r_temp_rx_byte[2]
.sym 23414 spi_if_ins.spi.r_temp_rx_byte[4]
.sym 23428 spi_if_ins.spi.r_temp_rx_byte[5]
.sym 23432 i_mosi$SB_IO_IN
.sym 23440 spi_if_ins.spi.r_temp_rx_byte[0]
.sym 23441 o_miso_$_TBUF__Y_E
.sym 23442 i_sck$SB_IO_IN
.sym 23474 w_rx_data[0]
.sym 23486 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 23493 i_rst_b$SB_IO_IN
.sym 23496 spi_if_ins.r_tx_byte[7]
.sym 23500 i_smi_soe_se$SB_IO_IN
.sym 23503 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 23514 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 23542 i_smi_soe_se$SB_IO_IN
.sym 23543 i_rst_b$SB_IO_IN
.sym 23554 spi_if_ins.r_tx_byte[7]
.sym 23555 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 23556 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 23564 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 23565 r_counter_$glb_clk
.sym 23568 r_counter
.sym 23582 spi_if_ins.r_tx_byte[7]
.sym 23589 smi_ctrl_ins.soe_and_reset
.sym 23591 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 23593 o_led1_SB_LUT4_I1_I3[3]
.sym 23601 io_pmod_out[3]$SB_IO_OUT
.sym 23610 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
.sym 23634 w_rx_data[0]
.sym 23671 w_rx_data[0]
.sym 23687 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
.sym 23688 r_counter_$glb_clk
.sym 23689 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 23696 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 23719 i_glob_clock$SB_IO_IN
.sym 23736 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 23737 w_load
.sym 23738 w_cs[2]
.sym 23752 w_fetch
.sym 23753 o_led1_SB_LUT4_I1_I3[3]
.sym 23758 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
.sym 23760 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
.sym 23770 w_fetch
.sym 23771 w_load
.sym 23772 w_cs[2]
.sym 23773 o_led1_SB_LUT4_I1_I3[3]
.sym 23801 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 23810 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
.sym 23811 r_counter_$glb_clk
.sym 23812 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
.sym 23816 o_led0$SB_IO_OUT
.sym 23818 o_led1$SB_IO_OUT
.sym 23829 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q_SB_DFFER_Q_E
.sym 23834 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 23837 io_pmod_out[0]$SB_IO_OUT
.sym 23839 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 23841 io_pmod_out[1]$SB_IO_OUT
.sym 23845 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 23847 io_pmod_out[3]$SB_IO_OUT
.sym 23856 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 23858 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
.sym 23860 w_load
.sym 23868 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 23872 w_cs[1]
.sym 23875 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
.sym 23876 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 23878 w_fetch
.sym 23879 i_glob_clock$SB_IO_IN
.sym 23884 o_led1_SB_LUT4_I1_I3[3]
.sym 23887 w_load
.sym 23888 o_led1_SB_LUT4_I1_I3[3]
.sym 23889 w_cs[1]
.sym 23890 w_fetch
.sym 23917 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 23918 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
.sym 23919 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
.sym 23920 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 23933 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
.sym 23934 i_glob_clock$SB_IO_IN
.sym 23936 io_pmod_out[1]$SB_IO_OUT
.sym 23939 io_pmod_out[3]$SB_IO_OUT
.sym 23941 io_pmod_out[2]$SB_IO_OUT
.sym 23942 io_pmod_out[0]$SB_IO_OUT
.sym 23951 o_led0$SB_IO_OUT
.sym 23961 o_led0_SB_LUT4_I1_O[1]
.sym 23962 o_led0$SB_IO_OUT
.sym 23964 w_rx_data[1]
.sym 23967 i_button_SB_LUT4_I0_O[1]
.sym 23970 w_rx_data[7]
.sym 23977 w_rx_data[7]
.sym 23981 w_rx_data[3]
.sym 23984 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 23988 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 23994 o_shdn_tx_lna$SB_IO_OUT
.sym 23995 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2]
.sym 23996 i_button_SB_LUT4_I0_I3[2]
.sym 23999 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 24005 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[0]
.sym 24006 io_pmod_out[2]$SB_IO_OUT
.sym 24007 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 24017 w_rx_data[7]
.sym 24022 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 24023 o_shdn_tx_lna$SB_IO_OUT
.sym 24024 io_pmod_out[2]$SB_IO_OUT
.sym 24025 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 24028 i_button_SB_LUT4_I0_I3[2]
.sym 24030 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[0]
.sym 24031 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2]
.sym 24048 w_rx_data[3]
.sym 24052 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 24054 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 24055 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 24056 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O
.sym 24057 r_counter_$glb_clk
.sym 24058 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 24065 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2]
.sym 24085 io_pmod_out[3]$SB_IO_OUT
.sym 24102 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
.sym 24103 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 24104 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2]
.sym 24105 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
.sym 24111 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2]
.sym 24117 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 24121 o_led0_SB_LUT4_I1_O[1]
.sym 24125 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
.sym 24163 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 24164 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
.sym 24165 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 24175 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
.sym 24177 o_led0_SB_LUT4_I1_O[1]
.sym 24178 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2]
.sym 24179 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
.sym 24180 r_counter_$glb_clk
.sym 24181 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2]
.sym 24182 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 24196 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
.sym 24206 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
.sym 24208 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3]
.sym 24211 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
.sym 24225 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
.sym 24226 i_button_SB_LUT4_I0_I3[2]
.sym 24227 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
.sym 24231 o_led1_SB_LUT4_I1_I3[0]
.sym 24232 o_led1_SB_LUT4_I1_I3[3]
.sym 24234 o_led0$SB_IO_OUT
.sym 24237 i_button_SB_LUT4_I0_O[1]
.sym 24238 i_config[0]$SB_IO_IN
.sym 24241 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E
.sym 24244 o_tr_vc2$SB_IO_OUT
.sym 24249 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 24258 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
.sym 24259 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 24263 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
.sym 24264 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 24280 o_led0$SB_IO_OUT
.sym 24281 o_led1_SB_LUT4_I1_I3[0]
.sym 24282 o_led1_SB_LUT4_I1_I3[3]
.sym 24283 i_button_SB_LUT4_I0_I3[2]
.sym 24286 i_button_SB_LUT4_I0_O[1]
.sym 24287 i_config[0]$SB_IO_IN
.sym 24288 o_tr_vc2$SB_IO_OUT
.sym 24289 o_led1_SB_LUT4_I1_I3[3]
.sym 24302 spi_if_ins.o_cs_SB_LUT4_I0_3_O_SB_DFFER_Q_E
.sym 24303 r_counter_$glb_clk
.sym 24304 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 24313 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
.sym 24317 i_glob_clock$SB_IO_IN
.sym 24321 w_rx_fifo_full
.sym 24349 o_led0_SB_LUT4_I1_O[1]
.sym 24361 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2]
.sym 24364 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
.sym 24366 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
.sym 24372 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 24415 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2]
.sym 24416 o_led0_SB_LUT4_I1_O[1]
.sym 24418 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 24425 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
.sym 24426 r_counter_$glb_clk
.sym 24427 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
.sym 24596 o_led0$SB_IO_OUT
.sym 24607 o_led0$SB_IO_OUT
.sym 24659 i_sck$SB_IO_IN
.sym 24865 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
.sym 24868 smi_ctrl_ins.swe_and_reset
.sym 24882 w_smi_data_input[7]
.sym 24927 w_smi_data_input[7]
.sym 24932 smi_ctrl_ins.swe_and_reset
.sym 24933 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
.sym 25100 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_O
.sym 25401 io_pmod_in[3]$SB_IO_IN
.sym 25556 io_pmod_in[2]$SB_IO_IN
.sym 25711 i_glob_clock$SB_IO_IN
.sym 25720 io_pmod_out[3]$SB_IO_OUT
.sym 25878 i_glob_clock$SB_IO_IN
.sym 25954 r_counter
.sym 25962 i_glob_clock$SB_IO_IN
.sym 25978 r_counter
.sym 26017 i_glob_clock$SB_IO_IN
.sym 26018 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 26094 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 26113 spi_if_ins.w_rx_data[1]
.sym 26164 spi_if_ins.w_rx_data[1]
.sym 26171 spi_if_ins.o_ioc_SB_DFFE_Q_E
.sym 26172 r_counter_$glb_clk
.sym 26181 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 26258 o_led1_SB_DFFER_Q_E
.sym 26263 w_rx_data[1]
.sym 26269 w_rx_data[0]
.sym 26301 w_rx_data[0]
.sym 26313 w_rx_data[1]
.sym 26326 o_led1_SB_DFFER_Q_E
.sym 26327 r_counter_$glb_clk
.sym 26328 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 26405 w_rx_data[2]
.sym 26419 w_rx_data[3]
.sym 26421 w_rx_data[0]
.sym 26429 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
.sym 26431 w_rx_data[1]
.sym 26435 w_rx_data[1]
.sym 26453 w_rx_data[3]
.sym 26467 w_rx_data[2]
.sym 26474 w_rx_data[0]
.sym 26481 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
.sym 26482 r_counter_$glb_clk
.sym 26495 w_rx_data[2]
.sym 26575 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0]
.sym 26577 w_rx_fifo_full
.sym 26583 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
.sym 26626 w_rx_fifo_full
.sym 26627 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
.sym 26636 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0]
.sym 26637 lvds_clock_$glb_clk
.sym 26638 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 26719 w_rx_fifo_full
.sym 26723 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
.sym 26729 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 26730 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
.sym 26745 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
.sym 26746 w_rx_fifo_full
.sym 26748 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 26791 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
.sym 26792 lvds_clock_$glb_clk
.sym 26793 i_rst_b_SB_LUT4_I3_O_$glb_sr
.sym 26807 o_tr_vc2$SB_IO_OUT
.sym 26811 o_rx_h_tx_l$SB_IO_OUT
.sym 26960 o_tr_vc1_b$SB_IO_OUT
.sym 27283 o_smi_read_req$SB_IO_OUT
.sym 27296 o_smi_read_req$SB_IO_OUT
.sym 27307 i_mosi$SB_IO_IN
.sym 27397 i_glob_clock$SB_IO_IN
.sym 27400 io_pmod_out[3]$SB_IO_OUT
.sym 27420 io_pmod_out[3]$SB_IO_OUT
.sym 27429 smi_ctrl_ins.soe_and_reset
.sym 27444 smi_ctrl_ins.soe_and_reset
.sym 27459 r_counter
.sym 27470 r_counter
.sym 27515 o_rx_h_tx_l$SB_IO_OUT
.sym 27516 i_glob_clock$SB_IO_IN
.sym 27519 io_pmod_out[2]$SB_IO_OUT
.sym 27522 io_pmod_out[1]$SB_IO_OUT
.sym 27536 io_pmod_out[1]$SB_IO_OUT
.sym 27541 io_pmod_out[2]$SB_IO_OUT
.sym 27549 io_pmod_out[0]$SB_IO_OUT
.sym 27564 io_pmod_out[0]$SB_IO_OUT
.sym 27577 o_rx_h_tx_l_b$SB_IO_OUT
.sym 27582 o_rx_h_tx_l$SB_IO_OUT
.sym 27593 o_rx_h_tx_l$SB_IO_OUT
.sym 27605 o_tr_vc1$SB_IO_OUT
.sym 27608 o_tr_vc2$SB_IO_OUT
.sym 27617 o_tr_vc2$SB_IO_OUT
.sym 27620 o_tr_vc1$SB_IO_OUT
.sym 27631 o_rx_h_tx_l_b$SB_IO_OUT
.sym 27634 o_tr_vc1_b$SB_IO_OUT
.sym 27643 o_tr_vc1_b$SB_IO_OUT
.sym 27655 o_rx_h_tx_l_b$SB_IO_OUT
.sym 27720 w_rx_09_fifo_data[12]
.sym 27721 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27724 w_rx_09_fifo_data[10]
.sym 27725 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27748 w_rx_09_fifo_data[21]
.sym 27749 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27752 w_rx_09_fifo_data[23]
.sym 27753 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27759 w_rx_24_fifo_data[25]
.sym 27760 w_rx_09_fifo_data[25]
.sym 27761 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 27763 w_rx_24_fifo_data[27]
.sym 27764 w_rx_09_fifo_data[27]
.sym 27765 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 27768 w_rx_09_fifo_data[25]
.sym 27769 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27771 w_rx_09_fifo_data[23]
.sym 27772 w_rx_24_fifo_data[23]
.sym 27773 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 27780 w_rx_09_fifo_data[13]
.sym 27781 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27784 w_rx_09_fifo_data[17]
.sym 27785 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27787 w_rx_24_fifo_data[13]
.sym 27788 w_rx_09_fifo_data[13]
.sym 27789 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 27796 w_rx_09_fifo_data[19]
.sym 27797 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27800 w_rx_09_fifo_data[27]
.sym 27801 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27804 w_rx_09_fifo_data[15]
.sym 27805 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27808 w_rx_09_fifo_data[8]
.sym 27809 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27812 w_rx_09_fifo_data[4]
.sym 27813 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27816 w_rx_09_fifo_data[7]
.sym 27817 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27820 w_rx_09_fifo_data[9]
.sym 27821 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27824 w_rx_09_fifo_data[29]
.sym 27825 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27828 w_rx_09_fifo_data[5]
.sym 27829 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27832 w_rx_09_fifo_data[6]
.sym 27833 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27836 w_rx_09_fifo_data[11]
.sym 27837 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27839 w_rx_24_fifo_data[7]
.sym 27840 w_rx_09_fifo_data[7]
.sym 27841 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 27843 w_rx_09_fifo_data[4]
.sym 27844 w_rx_24_fifo_data[4]
.sym 27845 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 27847 w_rx_09_fifo_data[9]
.sym 27848 w_rx_24_fifo_data[9]
.sym 27849 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 27852 w_rx_24_fifo_data[13]
.sym 27853 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 27856 w_rx_24_fifo_data[9]
.sym 27857 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 27859 w_rx_24_fifo_data[11]
.sym 27860 w_rx_09_fifo_data[11]
.sym 27861 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 27864 w_rx_24_fifo_data[4]
.sym 27865 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 27868 w_rx_24_fifo_data[11]
.sym 27869 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 27872 w_rx_24_fifo_data[7]
.sym 27873 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 27876 w_rx_24_fifo_data[5]
.sym 27877 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 27880 w_rx_24_fifo_data[0]
.sym 27881 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 27889 lvds_clock
.sym 27892 w_rx_24_fifo_data[3]
.sym 27893 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 27895 w_rx_24_fifo_data[5]
.sym 27896 w_rx_09_fifo_data[5]
.sym 27897 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 27900 w_rx_24_fifo_data[1]
.sym 27901 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 27904 w_rx_24_fifo_data[2]
.sym 27905 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 27908 w_rx_09_fifo_data[3]
.sym 27909 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27912 w_rx_09_fifo_data[28]
.sym 27913 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27916 w_rx_09_fifo_data[2]
.sym 27917 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27919 w_rx_09_fifo_data[3]
.sym 27920 w_rx_24_fifo_data[3]
.sym 27921 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 27924 w_rx_09_fifo_data[0]
.sym 27925 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27927 w_rx_24_fifo_data[2]
.sym 27928 w_rx_09_fifo_data[2]
.sym 27929 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 27932 w_rx_09_fifo_data[1]
.sym 27933 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 27937 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 27939 rx_fifo.wr_addr[1]
.sym 27944 rx_fifo.wr_addr[2]
.sym 27945 rx_fifo.wr_addr[1]
.sym 27948 rx_fifo.wr_addr[3]
.sym 27949 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1_SB_LUT4_O_1_I3
.sym 27952 rx_fifo.wr_addr[4]
.sym 27953 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2_SB_LUT4_O_I3
.sym 27956 rx_fifo.wr_addr[5]
.sym 27957 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_O_I3
.sym 27960 rx_fifo.wr_addr[6]
.sym 27961 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 27964 rx_fifo.wr_addr[7]
.sym 27965 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 27968 rx_fifo.wr_addr[8]
.sym 27969 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 27972 rx_fifo.wr_addr[9]
.sym 27973 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I3
.sym 27977 w_lvds_rx_24_d0
.sym 27978 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 27979 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
.sym 27980 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 27981 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[3]
.sym 27983 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0]
.sym 27984 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1]
.sym 27985 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2]
.sym 27987 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 27988 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[1]
.sym 27989 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 27991 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
.sym 27992 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1]
.sym 27993 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2]
.sym 27995 rx_fifo.rd_addr_gray_wr_r[7]
.sym 27996 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[2]
.sym 27997 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1]
.sym 27998 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
.sym 27999 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2]
.sym 28000 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2]
.sym 28001 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[3]
.sym 28002 w_lvds_rx_09_d0
.sym 28012 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
.sym 28013 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1]
.sym 28016 i_rst_b$SB_IO_IN
.sym 28017 w_lvds_rx_09_d1_SB_LUT4_I0_O[1]
.sym 28035 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3
.sym 28038 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28039 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q_SB_LUT4_I3_O[1]
.sym 28040 $PACKER_VCC_NET
.sym 28041 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_D_SB_LUT4_O_I3
.sym 28042 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28043 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
.sym 28044 $PACKER_VCC_NET
.sym 28045 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28048 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
.sym 28049 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
.sym 28061 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[0]
.sym 28062 w_lvds_rx_09_d1
.sym 28063 w_lvds_rx_09_d0
.sym 28064 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 28065 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 28066 w_lvds_rx_24_d1
.sym 28067 w_lvds_rx_24_d0
.sym 28068 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 28069 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28073 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0]
.sym 28075 w_lvds_rx_24_d1
.sym 28076 w_lvds_rx_24_d0
.sym 28077 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 28084 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[0]
.sym 28085 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E[1]
.sym 28086 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0]
.sym 28087 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 28088 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28089 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2]
.sym 28090 w_lvds_rx_24_d1
.sym 28091 w_lvds_rx_24_d0
.sym 28092 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 28093 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 28095 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[0]
.sym 28096 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28097 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_2_Q[2]
.sym 28099 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[3]
.sym 28102 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 28103 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[1]
.sym 28104 $PACKER_VCC_NET
.sym 28105 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O[3]
.sym 28106 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 28107 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[2]
.sym 28108 $PACKER_VCC_NET
.sym 28109 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I1_I3
.sym 28110 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1
.sym 28111 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 28112 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 28113 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
.sym 28117 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0
.sym 28118 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 28119 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 28120 w_lvds_rx_09_d1_SB_LUT4_I2_O[2]
.sym 28121 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
.sym 28122 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I0
.sym 28123 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1
.sym 28124 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I2[2]
.sym 28125 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 28129 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_O_I1
.sym 28130 w_lvds_rx_09_d1
.sym 28131 w_lvds_rx_09_d0
.sym 28132 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 28133 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 28136 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 28137 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
.sym 28144 w_lvds_rx_09_d1
.sym 28145 w_lvds_rx_09_d0
.sym 28151 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 28152 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 28153 w_lvds_rx_09_d1_SB_LUT4_I2_O[2]
.sym 28158 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
.sym 28195 w_rx_24_fifo_data[20]
.sym 28196 w_rx_09_fifo_data[20]
.sym 28197 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28200 w_rx_09_fifo_data[18]
.sym 28201 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 28204 w_rx_09_fifo_data[22]
.sym 28205 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 28211 w_rx_24_fifo_data[22]
.sym 28212 w_rx_09_fifo_data[22]
.sym 28213 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28220 w_rx_09_fifo_data[20]
.sym 28221 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 28224 w_rx_09_fifo_data[24]
.sym 28225 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 28228 w_rx_24_fifo_data[20]
.sym 28229 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28231 w_rx_24_fifo_data[24]
.sym 28232 w_rx_09_fifo_data[24]
.sym 28233 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28235 w_rx_24_fifo_data[14]
.sym 28236 w_rx_09_fifo_data[14]
.sym 28237 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28240 w_rx_24_fifo_data[22]
.sym 28241 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28244 w_rx_24_fifo_data[12]
.sym 28245 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28248 w_rx_24_fifo_data[14]
.sym 28249 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28252 w_rx_24_fifo_data[18]
.sym 28253 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28255 w_rx_09_fifo_data[12]
.sym 28256 w_rx_24_fifo_data[12]
.sym 28257 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28260 w_rx_24_fifo_data[16]
.sym 28261 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28264 w_rx_24_fifo_data[27]
.sym 28265 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28268 w_rx_24_fifo_data[23]
.sym 28269 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28272 w_rx_24_fifo_data[24]
.sym 28273 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28276 w_rx_24_fifo_data[8]
.sym 28277 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28280 w_rx_24_fifo_data[25]
.sym 28281 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28284 w_rx_24_fifo_data[10]
.sym 28285 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28288 w_rx_24_fifo_data[26]
.sym 28289 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28292 w_rx_09_fifo_data[14]
.sym 28293 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 28295 w_rx_09_fifo_data[16]
.sym 28296 w_rx_24_fifo_data[16]
.sym 28297 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28299 w_rx_24_fifo_data[21]
.sym 28300 w_rx_09_fifo_data[21]
.sym 28301 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28303 w_rx_24_fifo_data[15]
.sym 28304 w_rx_09_fifo_data[15]
.sym 28305 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28308 w_rx_09_fifo_data[26]
.sym 28309 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 28311 w_rx_24_fifo_data[10]
.sym 28312 w_rx_09_fifo_data[10]
.sym 28313 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28315 w_rx_09_fifo_data[18]
.sym 28316 w_rx_24_fifo_data[18]
.sym 28317 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28320 w_rx_09_fifo_data[16]
.sym 28321 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 28322 w_rx_fifo_pulled_data[5]
.sym 28335 w_rx_24_fifo_data[8]
.sym 28336 w_rx_09_fifo_data[8]
.sym 28337 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28339 w_rx_24_fifo_data[29]
.sym 28340 w_rx_09_fifo_data[29]
.sym 28341 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28343 w_rx_09_fifo_data[17]
.sym 28344 w_rx_24_fifo_data[17]
.sym 28345 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28347 w_rx_09_fifo_data[6]
.sym 28348 w_rx_24_fifo_data[6]
.sym 28349 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28351 w_rx_24_fifo_data[19]
.sym 28352 w_rx_09_fifo_data[19]
.sym 28353 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28356 w_rx_24_fifo_data[6]
.sym 28357 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28360 w_rx_24_fifo_data[19]
.sym 28361 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28364 w_rx_24_fifo_data[28]
.sym 28365 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28368 w_rx_24_fifo_data[17]
.sym 28369 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28372 w_rx_24_fifo_data[21]
.sym 28373 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28375 w_rx_09_fifo_data[31]
.sym 28376 w_rx_24_fifo_data[31]
.sym 28377 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28380 w_rx_24_fifo_data[29]
.sym 28381 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28384 w_rx_24_fifo_data[15]
.sym 28385 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28391 i_rst_b$SB_IO_IN
.sym 28392 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28393 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1]
.sym 28394 w_rx_fifo_pulled_data[11]
.sym 28399 w_rx_09_fifo_data[28]
.sym 28400 w_rx_24_fifo_data[28]
.sym 28401 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28402 w_rx_fifo_pulled_data[10]
.sym 28406 w_rx_fifo_pulled_data[18]
.sym 28410 w_rx_fifo_pulled_data[9]
.sym 28415 w_rx_09_fifo_data[30]
.sym 28416 w_rx_24_fifo_data[30]
.sym 28417 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28418 w_rx_fifo_pulled_data[0]
.sym 28426 w_rx_fifo_pulled_data[3]
.sym 28438 w_rx_fifo_pulled_data[1]
.sym 28442 w_rx_fifo_pulled_data[2]
.sym 28450 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 28455 w_rx_24_fifo_data[0]
.sym 28456 w_rx_09_fifo_data[0]
.sym 28457 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28460 rx_fifo.wr_addr[1]
.sym 28461 rx_fifo.wr_addr[0]
.sym 28462 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 28466 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2]
.sym 28470 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 28475 w_rx_24_fifo_data[1]
.sym 28476 w_rx_09_fifo_data[1]
.sym 28477 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28478 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 28483 rx_fifo.rd_addr_gray_wr_r[4]
.sym 28484 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[2]
.sym 28485 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[1]
.sym 28487 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28488 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[1]
.sym 28489 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[2]
.sym 28492 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2]
.sym 28493 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 28496 i_rst_b$SB_IO_IN
.sym 28497 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 28498 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
.sym 28499 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3]
.sym 28500 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2]
.sym 28501 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3]
.sym 28504 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
.sym 28505 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[1]
.sym 28506 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0]
.sym 28507 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1]
.sym 28508 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2]
.sym 28509 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3]
.sym 28510 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
.sym 28511 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1]
.sym 28512 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[2]
.sym 28513 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[3]
.sym 28514 w_rx_fifo_full
.sym 28515 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
.sym 28516 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 28517 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 28519 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
.sym 28520 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 28521 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 28522 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
.sym 28523 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
.sym 28524 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 28525 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 28526 rx_fifo.rd_addr_gray_wr[0]
.sym 28530 rx_fifo.rd_addr_gray[0]
.sym 28535 rx_fifo.full_o_SB_LUT4_I0_O[0]
.sym 28536 rx_fifo.full_o_SB_LUT4_I0_O[1]
.sym 28537 rx_fifo.full_o_SB_LUT4_I0_O[2]
.sym 28538 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[0]
.sym 28539 rx_fifo.wr_addr[1]
.sym 28540 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I1[1]
.sym 28541 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 28542 rx_fifo.wr_addr[2]
.sym 28543 rx_fifo.rd_addr_gray_wr_r[1]
.sym 28544 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[2]
.sym 28545 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_1_O[3]
.sym 28546 rx_fifo.rd_addr[9]
.sym 28554 rx_fifo.rd_addr_gray_wr[9]
.sym 28562 rx_fifo.rd_addr_gray[5]
.sym 28566 rx_fifo.rd_addr_gray_wr[5]
.sym 28584 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 28585 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 28587 w_lvds_rx_24_d1
.sym 28588 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 28589 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
.sym 28604 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
.sym 28605 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28620 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 28621 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
.sym 28624 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28625 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_O_I3[1]
.sym 28636 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[3]
.sym 28637 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
.sym 28638 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
.sym 28664 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E[0]
.sym 28665 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
.sym 28670 w_lvds_rx_09_d1
.sym 28671 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
.sym 28672 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 28673 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]
.sym 28706 tx_fifo.rd_addr_gray[3]
.sym 28710 tx_fifo.rd_addr_gray[2]
.sym 28714 tx_fifo.rd_addr_gray_wr[5]
.sym 28718 tx_fifo.rd_addr_gray[5]
.sym 28722 tx_fifo.rd_addr_gray_wr[6]
.sym 28726 tx_fifo.rd_addr_gray_wr[3]
.sym 28730 tx_fifo.rd_addr_gray[6]
.sym 28738 smi_ctrl_ins.r_fifo_pulled_data[26]
.sym 28739 smi_ctrl_ins.r_fifo_pulled_data[18]
.sym 28740 smi_ctrl_ins.int_cnt_rx[4]
.sym 28741 smi_ctrl_ins.int_cnt_rx[3]
.sym 28742 w_rx_fifo_pulled_data[13]
.sym 28746 w_rx_fifo_pulled_data[26]
.sym 28750 w_rx_fifo_pulled_data[15]
.sym 28754 w_rx_fifo_pulled_data[23]
.sym 28758 w_rx_fifo_pulled_data[21]
.sym 28762 w_rx_fifo_pulled_data[20]
.sym 28766 w_rx_fifo_pulled_data[22]
.sym 28782 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1]
.sym 28786 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 28791 tx_fifo.rd_addr[2]
.sym 28792 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 28793 tx_fifo.rd_addr[1]
.sym 28794 smi_ctrl_ins.r_fifo_pulled_data[15]
.sym 28795 smi_ctrl_ins.r_fifo_pulled_data[7]
.sym 28796 smi_ctrl_ins.int_cnt_rx[4]
.sym 28797 smi_ctrl_ins.int_cnt_rx[3]
.sym 28799 w_rx_09_fifo_data[26]
.sym 28800 w_rx_24_fifo_data[26]
.sym 28801 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 28802 w_rx_fifo_pulled_data[24]
.sym 28806 w_rx_fifo_pulled_data[25]
.sym 28810 w_rx_fifo_pulled_data[27]
.sym 28814 w_rx_fifo_pulled_data[12]
.sym 28818 w_rx_fifo_pulled_data[6]
.sym 28822 w_rx_fifo_pulled_data[14]
.sym 28826 smi_ctrl_ins.r_fifo_pulled_data[13]
.sym 28827 smi_ctrl_ins.r_fifo_pulled_data[5]
.sym 28828 smi_ctrl_ins.int_cnt_rx[4]
.sym 28829 smi_ctrl_ins.int_cnt_rx[3]
.sym 28830 smi_ctrl_ins.r_fifo_pulled_data[14]
.sym 28831 smi_ctrl_ins.r_fifo_pulled_data[6]
.sym 28832 smi_ctrl_ins.int_cnt_rx[4]
.sym 28833 smi_ctrl_ins.int_cnt_rx[3]
.sym 28834 w_rx_fifo_pulled_data[8]
.sym 28842 w_rx_fifo_pulled_data[16]
.sym 28846 w_rx_fifo_pulled_data[7]
.sym 28850 smi_ctrl_ins.r_fifo_pulled_data[24]
.sym 28851 smi_ctrl_ins.r_fifo_pulled_data[16]
.sym 28852 smi_ctrl_ins.int_cnt_rx[4]
.sym 28853 smi_ctrl_ins.int_cnt_rx[3]
.sym 28854 smi_ctrl_ins.r_fifo_pulled_data[10]
.sym 28855 smi_ctrl_ins.int_cnt_rx[4]
.sym 28856 smi_ctrl_ins.int_cnt_rx[3]
.sym 28857 smi_ctrl_ins.r_fifo_pulled_data[2]
.sym 28862 w_rx_fifo_pulled_data[4]
.sym 28869 rx_fifo.rd_addr[0]
.sym 28877 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 28878 smi_ctrl_ins.r_fifo_pulled_data[8]
.sym 28879 smi_ctrl_ins.int_cnt_rx[4]
.sym 28880 smi_ctrl_ins.int_cnt_rx[3]
.sym 28881 smi_ctrl_ins.r_fifo_pulled_data[0]
.sym 28882 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 28886 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
.sym 28897 rx_fifo.wr_addr[4]
.sym 28899 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 28900 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 28901 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 28907 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 28908 rx_fifo.wr_addr_gray_rd_r[5]
.sym 28909 rx_fifo.rd_addr[5]
.sym 28910 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 28914 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 28922 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 28929 rx_fifo.wr_addr[0]
.sym 28931 rx_fifo.wr_addr[0]
.sym 28936 rx_fifo.wr_addr[1]
.sym 28940 rx_fifo.wr_addr[2]
.sym 28941 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 28944 rx_fifo.wr_addr[3]
.sym 28945 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 28948 rx_fifo.wr_addr[4]
.sym 28949 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 28952 rx_fifo.wr_addr[5]
.sym 28953 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 28956 rx_fifo.wr_addr[6]
.sym 28957 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 28960 rx_fifo.wr_addr[7]
.sym 28961 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 28964 rx_fifo.wr_addr[8]
.sym 28965 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
.sym 28968 rx_fifo.wr_addr[9]
.sym 28969 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 28972 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 28973 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 28974 rx_fifo.rd_addr_gray_wr_r[1]
.sym 28975 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 28976 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[2]
.sym 28977 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3]
.sym 28980 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
.sym 28981 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 28983 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
.sym 28984 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 28985 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 28988 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 28989 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 28992 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 28993 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 28997 rx_fifo.rd_addr[1]
.sym 28998 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
.sym 28999 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
.sym 29000 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
.sym 29001 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
.sym 29002 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I3[0]
.sym 29003 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 29004 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 29005 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
.sym 29006 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3_SB_LUT4_I3_O[0]
.sym 29007 rx_fifo.rd_addr_gray_wr_r[4]
.sym 29008 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 29009 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
.sym 29014 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 29015 rx_fifo.wr_addr_gray_rd_r[5]
.sym 29016 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 29017 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 29018 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29024 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I3[0]
.sym 29025 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
.sym 29026 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 29031 rx_fifo.rd_addr[5]
.sym 29032 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 29033 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 29036 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 29037 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 29038 rx_fifo.wr_addr_gray_rd_r[9]
.sym 29039 rx_fifo.rd_addr[9]
.sym 29040 rx_fifo.wr_addr_gray_rd_r[8]
.sym 29041 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 29042 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
.sym 29046 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
.sym 29057 rx_fifo.wr_addr[1]
.sym 29062 rx_fifo.wr_addr_gray_rd[4]
.sym 29066 rx_fifo.wr_addr_gray_rd[5]
.sym 29070 rx_fifo.wr_addr_gray_rd[8]
.sym 29074 rx_fifo.wr_addr_gray[5]
.sym 29082 rx_fifo.wr_addr_gray[8]
.sym 29086 rx_fifo.wr_addr_gray[1]
.sym 29090 rx_fifo.wr_addr_gray[4]
.sym 29098 rx_fifo.wr_addr_gray[2]
.sym 29102 rx_fifo.wr_addr_gray[6]
.sym 29108 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 29109 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 29110 rx_fifo.wr_addr_gray_rd[2]
.sym 29118 rx_fifo.wr_addr_gray[3]
.sym 29124 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 29125 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 29126 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 29130 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
.sym 29134 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
.sym 29150 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 29221 tx_fifo.rd_addr[0]
.sym 29222 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
.sym 29226 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
.sym 29230 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
.sym 29236 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
.sym 29237 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 29238 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 29242 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2]
.sym 29246 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29250 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
.sym 29251 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 29252 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
.sym 29253 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[3]
.sym 29255 tx_fifo.wr_addr_gray_rd_r[2]
.sym 29256 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
.sym 29257 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 29260 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 29261 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29264 i_rst_b$SB_IO_IN
.sym 29265 w_tx_fifo_pull
.sym 29268 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 29269 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
.sym 29270 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3]
.sym 29275 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
.sym 29276 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[1]
.sym 29277 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_6_D[2]
.sym 29279 tx_fifo.wr_addr_gray_rd_r[2]
.sym 29280 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
.sym 29281 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 29283 tx_fifo.rd_addr[3]
.sym 29284 tx_fifo.rd_addr[2]
.sym 29285 tx_fifo.wr_addr_gray_rd_r[2]
.sym 29286 tx_fifo.rd_addr[4]
.sym 29287 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[1]
.sym 29288 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[2]
.sym 29289 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_1_I1[3]
.sym 29290 smi_ctrl_ins.r_fifo_pulled_data[11]
.sym 29291 smi_ctrl_ins.int_cnt_rx[4]
.sym 29292 smi_ctrl_ins.r_fifo_pulled_data[3]
.sym 29293 smi_ctrl_ins.int_cnt_rx[3]
.sym 29294 tx_fifo.rd_addr[7]
.sym 29295 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[1]
.sym 29296 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[2]
.sym 29297 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1[3]
.sym 29298 smi_ctrl_ins.r_fifo_pulled_data[31]
.sym 29299 smi_ctrl_ins.r_fifo_pulled_data[23]
.sym 29300 smi_ctrl_ins.int_cnt_rx[4]
.sym 29301 smi_ctrl_ins.int_cnt_rx[3]
.sym 29302 tx_fifo.rd_addr[7]
.sym 29303 tx_fifo.rd_addr[6]
.sym 29304 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 29305 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[3]
.sym 29307 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O_SB_LUT4_O_2_I1_SB_LUT4_O_2_I3[2]
.sym 29308 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[1]
.sym 29309 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D[2]
.sym 29310 tx_fifo.wr_addr_gray_rd[1]
.sym 29316 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
.sym 29317 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
.sym 29320 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
.sym 29321 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
.sym 29324 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
.sym 29325 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
.sym 29328 smi_ctrl_ins.int_cnt_rx[4]
.sym 29329 smi_ctrl_ins.int_cnt_rx[3]
.sym 29330 smi_ctrl_ins.r_fifo_pulled_data[30]
.sym 29331 smi_ctrl_ins.r_fifo_pulled_data[22]
.sym 29332 smi_ctrl_ins.int_cnt_rx[4]
.sym 29333 smi_ctrl_ins.int_cnt_rx[3]
.sym 29336 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
.sym 29337 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
.sym 29338 smi_ctrl_ins.r_fifo_pulled_data[12]
.sym 29339 smi_ctrl_ins.r_fifo_pulled_data[4]
.sym 29340 smi_ctrl_ins.int_cnt_rx[4]
.sym 29341 smi_ctrl_ins.int_cnt_rx[3]
.sym 29346 smi_ctrl_ins.w_fifo_pull_trigger
.sym 29359 smi_ctrl_ins.r_fifo_pull_1
.sym 29360 w_smi_read_req
.sym 29361 smi_ctrl_ins.r_fifo_pull
.sym 29370 smi_ctrl_ins.r_fifo_pulled_data[29]
.sym 29371 smi_ctrl_ins.r_fifo_pulled_data[21]
.sym 29372 smi_ctrl_ins.int_cnt_rx[4]
.sym 29373 smi_ctrl_ins.int_cnt_rx[3]
.sym 29374 smi_ctrl_ins.r_fifo_pull
.sym 29378 smi_ctrl_ins.r_fifo_pulled_data[9]
.sym 29379 smi_ctrl_ins.int_cnt_rx[4]
.sym 29380 smi_ctrl_ins.int_cnt_rx[3]
.sym 29381 smi_ctrl_ins.r_fifo_pulled_data[1]
.sym 29384 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
.sym 29385 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
.sym 29388 i_rst_b$SB_IO_IN
.sym 29389 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 29392 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
.sym 29393 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
.sym 29402 smi_ctrl_ins.r_fifo_pulled_data[25]
.sym 29403 smi_ctrl_ins.r_fifo_pulled_data[17]
.sym 29404 smi_ctrl_ins.int_cnt_rx[4]
.sym 29405 smi_ctrl_ins.int_cnt_rx[3]
.sym 29411 rx_fifo.rd_addr[0]
.sym 29416 rx_fifo.rd_addr[1]
.sym 29417 rx_fifo.rd_addr[0]
.sym 29420 rx_fifo.rd_addr[2]
.sym 29421 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 29424 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 29425 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3
.sym 29428 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 29429 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
.sym 29432 rx_fifo.rd_addr[5]
.sym 29433 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 29436 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 29437 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 29440 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 29441 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 29444 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 29445 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 29448 rx_fifo.rd_addr[9]
.sym 29449 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 29452 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29453 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 29454 w_rx_data[0]
.sym 29459 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
.sym 29460 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 29461 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 29464 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 29465 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29466 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 29467 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
.sym 29468 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 29469 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[3]
.sym 29471 rx_fifo.wr_addr_gray_rd_r[5]
.sym 29472 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
.sym 29473 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 29476 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
.sym 29477 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
.sym 29478 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[0]
.sym 29479 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
.sym 29480 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[2]
.sym 29481 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O_I3[3]
.sym 29482 i_sck$SB_IO_IN
.sym 29486 rx_fifo.wr_addr_gray_rd[3]
.sym 29490 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
.sym 29494 spi_if_ins.spi.SCKr[0]
.sym 29499 w_smi_read_req_SB_LUT4_I1_O[2]
.sym 29500 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1]
.sym 29501 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
.sym 29502 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
.sym 29506 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 29507 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
.sym 29508 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
.sym 29509 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
.sym 29512 rx_fifo.rd_addr[2]
.sym 29513 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 29514 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0]
.sym 29515 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1]
.sym 29516 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
.sym 29517 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3]
.sym 29518 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
.sym 29519 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[1]
.sym 29520 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
.sym 29521 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
.sym 29522 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
.sym 29523 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
.sym 29524 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
.sym 29525 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
.sym 29527 rx_fifo.rd_addr[2]
.sym 29528 rx_fifo.rd_addr[1]
.sym 29529 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0]
.sym 29531 rx_fifo.wr_addr_gray_rd_r[8]
.sym 29532 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 29533 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29534 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 29535 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1]
.sym 29536 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[2]
.sym 29537 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[3]
.sym 29538 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
.sym 29539 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[1]
.sym 29540 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[2]
.sym 29541 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3]
.sym 29543 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
.sym 29544 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[1]
.sym 29545 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O[2]
.sym 29546 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 29550 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[3]
.sym 29554 rx_fifo.rd_addr_SB_DFFESR_Q_5_D_SB_LUT4_I3_O[1]
.sym 29558 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
.sym 29562 rx_fifo.wr_addr_gray_rd_r[9]
.sym 29563 rx_fifo.rd_addr[1]
.sym 29564 w_smi_read_req_SB_LUT4_I1_I3[0]
.sym 29565 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29568 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 29569 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29570 rx_fifo.wr_addr_gray_rd[9]
.sym 29574 rx_fifo.wr_addr_gray_rd[0]
.sym 29578 rx_fifo.wr_addr_gray_rd[6]
.sym 29582 rx_fifo.wr_addr[9]
.sym 29586 w_smi_read_req_SB_LUT4_I1_I3[0]
.sym 29587 w_smi_read_req
.sym 29588 w_smi_read_req_SB_LUT4_I1_I3[2]
.sym 29589 w_smi_read_req_SB_LUT4_I1_I3[3]
.sym 29590 rx_fifo.wr_addr_gray[0]
.sym 29594 rx_fifo.wr_addr_gray_rd[1]
.sym 29598 w_smi_read_req_SB_LUT4_I1_O[0]
.sym 29599 w_smi_read_req_SB_LUT4_I1_O[1]
.sym 29600 w_smi_read_req_SB_LUT4_I1_O[2]
.sym 29601 w_smi_read_req_SB_LUT4_I1_O[3]
.sym 29608 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_I2[0]
.sym 29609 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 29610 rx_fifo.rd_addr_gray_wr_r[7]
.sym 29611 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
.sym 29612 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
.sym 29613 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
.sym 29620 rx_fifo.rd_addr_gray_wr_r[4]
.sym 29621 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
.sym 29622 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O[2]
.sym 29626 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 29634 rx_fifo.rd_addr_gray[7]
.sym 29638 rx_fifo.rd_addr_gray_wr[8]
.sym 29642 rx_fifo.rd_addr_gray_wr[4]
.sym 29646 rx_fifo.rd_addr_gray_wr[7]
.sym 29650 rx_fifo.rd_addr_gray[8]
.sym 29654 rx_fifo.rd_addr_gray[4]
.sym 29658 rx_fifo.rd_addr_gray[3]
.sym 29662 rx_fifo.rd_addr_gray_wr[3]
.sym 29666 rx_fifo.wr_addr_gray_rd[7]
.sym 29678 rx_fifo.wr_addr_gray[7]
.sym 29731 tx_fifo.rd_addr[0]
.sym 29736 tx_fifo.rd_addr[1]
.sym 29737 tx_fifo.rd_addr[0]
.sym 29740 tx_fifo.rd_addr[2]
.sym 29741 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D_SB_LUT4_O_I3
.sym 29744 tx_fifo.rd_addr[3]
.sym 29745 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 29748 tx_fifo.rd_addr[4]
.sym 29749 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 29752 tx_fifo.rd_addr[5]
.sym 29753 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3
.sym 29756 tx_fifo.rd_addr[6]
.sym 29757 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 29760 tx_fifo.rd_addr[7]
.sym 29761 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 29764 tx_fifo.rd_addr[8]
.sym 29765 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 29768 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
.sym 29769 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 29770 w_tx_fifo_pull
.sym 29771 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
.sym 29772 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
.sym 29773 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[3]
.sym 29777 smi_ctrl_ins.int_cnt_rx[3]
.sym 29780 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29781 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 29782 tx_fifo.rd_addr[4]
.sym 29783 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
.sym 29784 tx_fifo.rd_addr[2]
.sym 29785 tx_fifo.wr_addr_gray_rd_r[2]
.sym 29788 smi_ctrl_ins.int_cnt_rx[4]
.sym 29789 smi_ctrl_ins.int_cnt_rx[3]
.sym 29791 tx_fifo.rd_addr[4]
.sym 29792 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_3_D_SB_LUT4_O_1_I3[0]
.sym 29793 tx_fifo.rd_addr[3]
.sym 29794 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[0]
.sym 29795 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[1]
.sym 29796 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[2]
.sym 29797 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I1_O[3]
.sym 29800 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0]
.sym 29801 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
.sym 29803 w_tx_fifo_pull
.sym 29804 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
.sym 29805 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29806 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 29807 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
.sym 29808 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
.sym 29809 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
.sym 29812 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 29813 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29814 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 29815 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1]
.sym 29816 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
.sym 29817 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
.sym 29818 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0]
.sym 29819 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
.sym 29820 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[2]
.sym 29821 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[3]
.sym 29823 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
.sym 29824 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
.sym 29825 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
.sym 29828 tx_fifo.rd_addr[5]
.sym 29829 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[0]
.sym 29834 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
.sym 29842 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 29846 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
.sym 29847 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
.sym 29848 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[0]
.sym 29849 tx_fifo.rd_addr[8]
.sym 29850 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
.sym 29856 tx_fifo.rd_addr[8]
.sym 29857 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
.sym 29858 tx_fifo.wr_addr_gray[6]
.sym 29862 tx_fifo.wr_addr_gray[8]
.sym 29866 tx_fifo.wr_addr_gray_rd[3]
.sym 29870 tx_fifo.wr_addr_gray_rd[2]
.sym 29874 tx_fifo.wr_addr_gray[4]
.sym 29878 tx_fifo.wr_addr_gray_rd[7]
.sym 29882 tx_fifo.wr_addr_gray_rd[8]
.sym 29886 tx_fifo.wr_addr_gray_rd[4]
.sym 29898 tx_fifo.wr_addr_gray_rd[6]
.sym 29906 tx_fifo.wr_addr_gray_rd[0]
.sym 29914 tx_fifo.wr_addr_gray[1]
.sym 29922 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
.sym 29926 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 29934 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
.sym 29938 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
.sym 29942 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 29946 w_smi_read_req_SB_LUT4_I1_I3[2]
.sym 29960 w_smi_read_req_SB_LUT4_I1_I3[2]
.sym 29961 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
.sym 29964 i_ss$SB_IO_IN
.sym 29965 spi_if_ins.r_tx_data_valid
.sym 29968 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
.sym 29969 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
.sym 29972 rx_fifo.rd_addr_SB_DFFESR_Q_5_D[0]
.sym 29973 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
.sym 29974 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
.sym 29979 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
.sym 29980 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
.sym 29981 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 29984 rx_fifo.rd_addr_SB_DFFESR_Q_4_D[0]
.sym 29985 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
.sym 29986 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
.sym 29992 w_smi_read_req_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0_SB_LUT4_O_3_I3[1]
.sym 29993 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
.sym 29995 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
.sym 29996 spi_if_ins.state_if[1]
.sym 29997 spi_if_ins.state_if[0]
.sym 29998 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 29999 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
.sym 30000 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 30001 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
.sym 30003 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 30004 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 30005 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
.sym 30006 i_rst_b$SB_IO_IN
.sym 30007 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
.sym 30008 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
.sym 30009 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3]
.sym 30012 i_rst_b$SB_IO_IN
.sym 30013 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 30014 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
.sym 30018 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
.sym 30019 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
.sym 30020 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
.sym 30021 rx_fifo.rd_addr_SB_DFFESR_Q_4_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
.sym 30023 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
.sym 30024 spi_if_ins.state_if[1]
.sym 30025 spi_if_ins.state_if[0]
.sym 30028 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 30029 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 30033 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 30036 spi_if_ins.state_if[1]
.sym 30037 spi_if_ins.state_if[0]
.sym 30039 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
.sym 30040 spi_if_ins.state_if[1]
.sym 30041 spi_if_ins.state_if[0]
.sym 30043 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 30044 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 30045 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
.sym 30047 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
.sym 30048 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
.sym 30049 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[3]
.sym 30050 rx_fifo.rd_addr_gray[2]
.sym 30054 rx_fifo.rd_addr_gray[6]
.sym 30066 rx_fifo.rd_addr_gray_wr[2]
.sym 30070 rx_fifo.rd_addr_gray_wr[1]
.sym 30078 rx_fifo.rd_addr_gray_wr[6]
.sym 30082 w_rx_data[2]
.sym 30093 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
.sym 30098 w_rx_data[0]
.sym 30108 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[0]
.sym 30109 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
.sym 30126 rx_fifo.rd_addr_gray[1]
.sym 30152 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 30153 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 30167 io_pmod_in[2]$SB_IO_IN
.sym 30168 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 30169 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 30195 io_pmod_in[3]$SB_IO_IN
.sym 30196 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 30197 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 30217 w_lvds_rx_09_d1_SB_LUT4_I2_O[1]
.sym 30244 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
.sym 30245 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 30246 tx_fifo.wr_addr[9]
.sym 30250 tx_fifo.wr_addr_gray_rd[9]
.sym 30256 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 30257 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
.sym 30258 tx_fifo.wr_addr_gray[3]
.sym 30265 i_rst_b$SB_IO_IN
.sym 30268 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
.sym 30269 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
.sym 30271 i_rst_b$SB_IO_IN
.sym 30272 smi_ctrl_ins.int_cnt_rx[4]
.sym 30273 smi_ctrl_ins.int_cnt_rx[3]
.sym 30275 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
.sym 30276 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
.sym 30277 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
.sym 30280 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
.sym 30281 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
.sym 30284 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[1]
.sym 30285 tx_fifo.rd_addr_SB_DFFNESR_Q_6_D[0]
.sym 30288 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
.sym 30289 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 30292 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
.sym 30293 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
.sym 30294 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 30298 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
.sym 30303 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
.sym 30304 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
.sym 30305 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 30306 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0]
.sym 30307 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 30308 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 30309 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 30310 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[2]
.sym 30311 tx_fifo.rd_addr[1]
.sym 30312 lvds_tx_inst.r_pulled_SB_LUT4_I0_O[0]
.sym 30313 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 30314 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 30319 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
.sym 30320 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
.sym 30321 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
.sym 30322 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1]
.sym 30326 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 30330 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 30331 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
.sym 30332 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
.sym 30333 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
.sym 30334 smi_ctrl_ins.r_fifo_pulled_data[28]
.sym 30335 smi_ctrl_ins.r_fifo_pulled_data[20]
.sym 30336 smi_ctrl_ins.int_cnt_rx[4]
.sym 30337 smi_ctrl_ins.int_cnt_rx[3]
.sym 30338 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 30339 tx_fifo.rd_addr_gray_wr_r[1]
.sym 30340 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 30341 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 30342 smi_ctrl_ins.r_fifo_pulled_data[27]
.sym 30343 smi_ctrl_ins.r_fifo_pulled_data[19]
.sym 30344 smi_ctrl_ins.int_cnt_rx[4]
.sym 30345 smi_ctrl_ins.int_cnt_rx[3]
.sym 30348 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
.sym 30349 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 30351 tx_fifo.rd_addr[6]
.sym 30352 tx_fifo.rd_addr[5]
.sym 30353 tx_fifo.rd_addr_SB_DFFNESR_Q_7_D_SB_LUT4_I2_O[0]
.sym 30360 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 30361 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 30370 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 30377 tx_fifo.wr_addr[1]
.sym 30380 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 30381 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 30382 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
.sym 30386 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 30400 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 30401 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 30402 tx_fifo.wr_addr_gray[0]
.sym 30410 tx_fifo.wr_addr_gray[5]
.sym 30422 tx_fifo.wr_addr_gray_rd[5]
.sym 30426 tx_fifo.wr_addr_gray[7]
.sym 30430 tx_fifo.wr_addr_gray[2]
.sym 30445 tx_fifo.rd_addr[1]
.sym 30467 spi_if_ins.spi.r_tx_bit_count[0]
.sym 30471 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 30472 $PACKER_VCC_NET
.sym 30475 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
.sym 30476 $PACKER_VCC_NET
.sym 30477 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3
.sym 30479 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 30480 $PACKER_VCC_NET
.sym 30481 spi_if_ins.spi.r_tx_bit_count[0]
.sym 30485 spi_if_ins.spi.r_tx_bit_count[0]
.sym 30487 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
.sym 30488 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 30489 spi_if_ins.spi.r_tx_bit_count[0]
.sym 30496 i_ss$SB_IO_IN
.sym 30497 spi_if_ins.r_tx_data_valid
.sym 30501 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 30505 w_smi_read_req
.sym 30512 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
.sym 30513 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 30514 i_rst_b$SB_IO_IN
.sym 30515 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 30516 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
.sym 30517 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
.sym 30522 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
.sym 30527 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 30528 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
.sym 30529 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 30531 i_rst_b$SB_IO_IN
.sym 30532 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[1]
.sym 30533 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
.sym 30534 spi_if_ins.w_rx_data[2]
.sym 30538 i_rst_b$SB_IO_IN
.sym 30539 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 30540 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
.sym 30541 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 30543 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 30544 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
.sym 30545 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
.sym 30551 i_rst_b$SB_IO_IN
.sym 30552 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
.sym 30553 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
.sym 30554 spi_if_ins.w_rx_data[6]
.sym 30558 i_rst_b$SB_IO_IN
.sym 30559 w_cs[2]
.sym 30560 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 30561 w_fetch
.sym 30562 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 30563 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 30564 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 30565 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 30566 w_load
.sym 30567 w_fetch
.sym 30568 w_cs[0]
.sym 30569 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 30570 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
.sym 30583 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 30584 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 30585 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
.sym 30588 i_rst_b$SB_IO_IN
.sym 30589 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
.sym 30591 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 30592 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 30593 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3[2]
.sym 30595 o_rx_h_tx_l$SB_IO_OUT
.sym 30596 i_button_SB_LUT4_I0_O[1]
.sym 30597 i_button_SB_LUT4_I0_O[2]
.sym 30600 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 30601 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
.sym 30602 w_cs[3]
.sym 30603 w_cs[2]
.sym 30604 w_cs[1]
.sym 30605 w_cs[0]
.sym 30606 w_cs[2]
.sym 30607 w_load
.sym 30608 w_fetch
.sym 30609 i_button_SB_LUT4_I0_I3[2]
.sym 30611 i_rst_b$SB_IO_IN
.sym 30612 w_cs[1]
.sym 30613 w_fetch
.sym 30618 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 30619 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 30620 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 30621 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 30623 w_tx_data_io[5]
.sym 30624 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
.sym 30625 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 30627 w_tx_data_io[7]
.sym 30628 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
.sym 30629 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 30631 o_tr_vc1$SB_IO_OUT
.sym 30632 i_button_SB_LUT4_I0_O[1]
.sym 30633 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2]
.sym 30634 i_button_SB_LUT4_I0_I3[0]
.sym 30635 i_button_SB_LUT4_I0_I3[1]
.sym 30636 i_button_SB_LUT4_I0_I3[2]
.sym 30637 i_button_SB_LUT4_I0_I3[3]
.sym 30643 w_fetch
.sym 30644 w_cs[0]
.sym 30645 sys_ctrl_ins.i_cs_SB_LUT4_I2_I3[2]
.sym 30646 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 30647 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 30648 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 30649 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 30650 w_tx_data_io[2]
.sym 30651 w_tx_data_smi[2]
.sym 30652 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1]
.sym 30653 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 30655 o_rx_h_tx_l_b$SB_IO_OUT
.sym 30656 i_button_SB_LUT4_I0_O[1]
.sym 30657 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
.sym 30658 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0]
.sym 30659 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
.sym 30660 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 30661 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3]
.sym 30679 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[0]
.sym 30680 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 30681 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1[2]
.sym 30687 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
.sym 30688 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 30689 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
.sym 30690 r_tx_data[2]
.sym 30705 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 30706 r_tx_data[0]
.sym 30718 r_tx_data[7]
.sym 30728 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
.sym 30729 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 30732 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
.sym 30733 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 30736 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_3_Q[0]
.sym 30737 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 30740 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3[0]
.sym 30741 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 30744 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
.sym 30745 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 30748 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_2_Q[0]
.sym 30749 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 30755 tx_fifo.wr_addr[0]
.sym 30760 tx_fifo.wr_addr[1]
.sym 30761 tx_fifo.wr_addr[0]
.sym 30764 tx_fifo.wr_addr[2]
.sym 30765 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3
.sym 30768 tx_fifo.wr_addr[3]
.sym 30769 tx_fifo.wr_addr_SB_DFFESR_Q_5_D_SB_LUT4_O_I3
.sym 30772 tx_fifo.wr_addr[4]
.sym 30773 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
.sym 30776 tx_fifo.wr_addr[5]
.sym 30777 tx_fifo.wr_addr_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 30780 tx_fifo.wr_addr[6]
.sym 30781 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 30784 tx_fifo.wr_addr[7]
.sym 30785 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3
.sym 30788 tx_fifo.wr_addr[8]
.sym 30789 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
.sym 30792 tx_fifo.wr_addr[9]
.sym 30793 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
.sym 30794 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 30798 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
.sym 30802 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 30806 tx_fifo.wr_addr_SB_DFFESR_Q_5_D[0]
.sym 30810 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 30814 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 30818 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 30819 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
.sym 30820 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 30821 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3]
.sym 30822 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
.sym 30823 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
.sym 30824 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
.sym 30825 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
.sym 30826 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 30827 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[1]
.sym 30828 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[2]
.sym 30829 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_I3_O[3]
.sym 30831 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 30832 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 30833 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 30834 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 30835 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[1]
.sym 30836 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 30837 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
.sym 30840 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
.sym 30841 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
.sym 30844 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
.sym 30845 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
.sym 30847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
.sym 30848 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 30849 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 30850 tx_fifo.rd_addr_gray_wr[7]
.sym 30854 lvds_tx_inst.r_pulled_SB_DFFESR_Q_D[1]
.sym 30858 tx_fifo.rd_addr_gray_wr[2]
.sym 30862 tx_fifo.rd_addr_gray[7]
.sym 30866 tx_fifo.rd_addr_gray[4]
.sym 30870 tx_fifo.rd_addr_gray[1]
.sym 30874 tx_fifo.rd_addr_gray_wr[4]
.sym 30878 tx_fifo.rd_addr_gray_wr[1]
.sym 30882 i_ss$SB_IO_IN
.sym 30883 spi_if_ins.spi.r_rx_bit_count[2]
.sym 30884 spi_if_ins.spi.r_rx_bit_count[1]
.sym 30885 spi_if_ins.spi.r_rx_bit_count[0]
.sym 30890 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
.sym 30895 w_tx_fifo_full
.sym 30896 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 30897 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 30898 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 30899 tx_fifo.wr_addr[1]
.sym 30900 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 30901 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 30903 tx_fifo.full_o_SB_LUT4_I1_O[0]
.sym 30904 tx_fifo.full_o_SB_LUT4_I1_O[1]
.sym 30905 tx_fifo.full_o_SB_LUT4_I1_O[2]
.sym 30907 spi_if_ins.spi.r_rx_bit_count[2]
.sym 30908 spi_if_ins.spi.r_rx_bit_count[1]
.sym 30909 spi_if_ins.spi.r_rx_bit_count[0]
.sym 30913 smi_ctrl_ins.r_fifo_pulled_data[19]
.sym 30914 spi_if_ins.spi.r2_rx_done
.sym 30924 spi_if_ins.spi.r3_rx_done
.sym 30925 spi_if_ins.spi.r2_rx_done
.sym 30932 i_ss$SB_IO_IN
.sym 30933 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
.sym 30934 tx_fifo.rd_addr_gray_wr[9]
.sym 30938 tx_fifo.rd_addr_gray_wr[0]
.sym 30942 spi_if_ins.spi.r_rx_done
.sym 30954 tx_fifo.rd_addr_gray[0]
.sym 30961 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
.sym 30978 w_tx_fifo_full
.sym 30985 w_smi_read_req
.sym 30986 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_Q[0]
.sym 30991 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 30992 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
.sym 30993 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
.sym 30994 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
.sym 30995 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
.sym 30996 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
.sym 30997 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
.sym 30999 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 31000 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
.sym 31001 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
.sym 31007 spi_if_ins.spi.r_tx_byte[3]
.sym 31008 spi_if_ins.spi.r_tx_byte[2]
.sym 31009 spi_if_ins.spi.r_tx_bit_count[0]
.sym 31010 spi_if_ins.spi.r_tx_byte[6]
.sym 31011 spi_if_ins.spi.r_tx_byte[4]
.sym 31012 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 31013 spi_if_ins.spi.r_tx_bit_count[0]
.sym 31014 spi_if_ins.r_tx_byte[4]
.sym 31018 spi_if_ins.r_tx_byte[2]
.sym 31022 spi_if_ins.r_tx_byte[3]
.sym 31026 spi_if_ins.r_tx_byte[6]
.sym 31031 spi_if_ins.spi.r_tx_byte[1]
.sym 31032 spi_if_ins.spi.r_tx_byte[0]
.sym 31033 spi_if_ins.spi.r_tx_bit_count[0]
.sym 31034 spi_if_ins.r_tx_byte[1]
.sym 31038 spi_if_ins.r_tx_byte[0]
.sym 31042 spi_if_ins.w_rx_data[2]
.sym 31047 w_ioc[4]
.sym 31048 w_ioc[3]
.sym 31049 w_ioc[2]
.sym 31056 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 31057 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 31058 spi_if_ins.w_rx_data[4]
.sym 31064 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 31065 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E_SB_LUT4_O_I3[1]
.sym 31066 spi_if_ins.w_rx_data[0]
.sym 31070 spi_if_ins.w_rx_data[3]
.sym 31074 w_cs[3]
.sym 31075 w_cs[2]
.sym 31076 w_cs[1]
.sym 31077 w_cs[0]
.sym 31078 r_tx_data[5]
.sym 31082 r_tx_data[4]
.sym 31086 r_tx_data[3]
.sym 31090 r_tx_data[1]
.sym 31099 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 31100 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 31101 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 31102 r_tx_data[6]
.sym 31107 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0]
.sym 31108 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 31109 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2]
.sym 31111 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
.sym 31112 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 31113 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
.sym 31115 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 31116 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 31117 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 31118 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
.sym 31119 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
.sym 31120 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 31121 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 31122 i_button$SB_IO_IN
.sym 31123 io_ctrl_ins.pmod_dir_state[7]
.sym 31124 i_button_SB_LUT4_I0_I3[2]
.sym 31125 i_button_SB_LUT4_I0_I3[3]
.sym 31126 w_cs[3]
.sym 31127 w_cs[2]
.sym 31128 w_cs[1]
.sym 31129 w_cs[0]
.sym 31130 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
.sym 31131 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
.sym 31132 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 31133 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 31134 w_cs[3]
.sym 31135 w_cs[2]
.sym 31136 w_cs[1]
.sym 31137 w_cs[0]
.sym 31139 w_tx_data_io[0]
.sym 31140 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1]
.sym 31141 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 31142 o_led0_SB_LUT4_I1_O[0]
.sym 31143 o_led0_SB_LUT4_I1_O[1]
.sym 31144 o_led0_SB_LUT4_I1_O[2]
.sym 31145 o_led0_SB_LUT4_I1_O[3]
.sym 31146 io_pmod_out[1]$SB_IO_OUT
.sym 31147 o_shdn_rx_lna$SB_IO_OUT
.sym 31148 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 31149 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 31150 w_tx_data_smi[1]
.sym 31151 w_tx_data_io[1]
.sym 31152 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1]
.sym 31153 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 31154 io_pmod_out[0]$SB_IO_OUT
.sym 31155 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 31156 io_ctrl_ins.mixer_en_state
.sym 31157 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 31158 o_led1_SB_LUT4_I1_O[0]
.sym 31159 o_led0_SB_LUT4_I1_O[1]
.sym 31160 o_led1_SB_LUT4_I1_O[2]
.sym 31161 o_led1_SB_LUT4_I1_O[3]
.sym 31163 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[0]
.sym 31164 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1]
.sym 31165 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O_I3[2]
.sym 31167 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 31168 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 31169 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 31170 io_ctrl_ins.rf_pin_state[3]
.sym 31171 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 31172 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
.sym 31173 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 31174 io_ctrl_ins.rf_pin_state[2]
.sym 31175 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 31176 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
.sym 31177 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 31179 io_ctrl_ins.rf_pin_state[7]
.sym 31180 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 31181 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 31182 io_ctrl_ins.rf_pin_state[4]
.sym 31183 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 31184 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2]
.sym 31185 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 31187 io_ctrl_ins.rf_pin_state[6]
.sym 31188 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 31189 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 31191 io_ctrl_ins.rf_pin_state[1]
.sym 31192 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 31193 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 31194 io_ctrl_ins.rf_pin_state[0]
.sym 31195 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 31196 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
.sym 31197 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 31198 io_ctrl_ins.rf_pin_state[5]
.sym 31199 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 31200 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2]
.sym 31201 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 31202 w_rx_data[4]
.sym 31206 w_rx_data[2]
.sym 31210 i_rst_b$SB_IO_IN
.sym 31211 o_led0_SB_LUT4_I1_O[0]
.sym 31212 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 31213 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
.sym 31217 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
.sym 31218 w_rx_data[1]
.sym 31222 w_rx_data[0]
.sym 31228 o_led1_SB_LUT4_I1_O[0]
.sym 31229 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1]
.sym 31230 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 31231 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
.sym 31232 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
.sym 31233 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
.sym 31234 w_rx_data[5]
.sym 31238 w_rx_data[2]
.sym 31242 w_rx_data[0]
.sym 31250 w_rx_data[1]
.sym 31258 w_rx_data[4]
.sym 31262 w_rx_data[6]
.sym 31273 tx_fifo.wr_addr[0]
.sym 31274 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
.sym 31278 tx_fifo.wr_addr_SB_DFFESR_Q_1_D[0]
.sym 31294 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
.sym 31299 tx_fifo.wr_addr[1]
.sym 31304 tx_fifo.wr_addr[2]
.sym 31305 tx_fifo.wr_addr[1]
.sym 31308 tx_fifo.wr_addr[3]
.sym 31309 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 31312 tx_fifo.wr_addr[4]
.sym 31313 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 31316 tx_fifo.wr_addr[5]
.sym 31317 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 31320 tx_fifo.wr_addr[6]
.sym 31321 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 31324 tx_fifo.wr_addr[7]
.sym 31325 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
.sym 31328 tx_fifo.wr_addr[8]
.sym 31329 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI
.sym 31332 tx_fifo.wr_addr[9]
.sym 31333 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3
.sym 31335 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
.sym 31336 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1]
.sym 31337 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 31338 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
.sym 31339 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 31340 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 31341 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3]
.sym 31342 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
.sym 31343 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 31344 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
.sym 31345 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3]
.sym 31347 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
.sym 31348 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
.sym 31349 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 31351 tx_fifo.rd_addr_gray_wr_r[8]
.sym 31352 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
.sym 31353 tx_fifo.wr_addr_SB_DFFESR_Q_1_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
.sym 31354 tx_fifo.wr_addr_SB_DFFESR_Q_4_D[0]
.sym 31360 i_rst_b$SB_IO_IN
.sym 31361 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
.sym 31362 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 31363 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
.sym 31364 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
.sym 31365 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
.sym 31366 smi_ctrl_ins.r_fifo_push
.sym 31370 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
.sym 31371 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
.sym 31372 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
.sym 31373 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
.sym 31375 tx_fifo.wr_addr[2]
.sym 31376 tx_fifo.rd_addr_gray_wr_r[1]
.sym 31377 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O[1]
.sym 31379 w_tx_fifo_full
.sym 31380 smi_ctrl_ins.r_fifo_push
.sym 31381 smi_ctrl_ins.r_fifo_push_1
.sym 31382 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
.sym 31383 tx_fifo.rd_addr_gray_wr_r[8]
.sym 31384 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
.sym 31385 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
.sym 31386 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[0]
.sym 31387 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[1]
.sym 31388 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[2]
.sym 31389 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O[3]
.sym 31392 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0]
.sym 31393 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I3_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1]
.sym 31395 spi_if_ins.spi.r_rx_bit_count[0]
.sym 31400 spi_if_ins.spi.r_rx_bit_count[1]
.sym 31401 spi_if_ins.spi.r_rx_bit_count[0]
.sym 31404 spi_if_ins.spi.r_rx_bit_count[2]
.sym 31405 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3
.sym 31409 spi_if_ins.spi.r_rx_bit_count[0]
.sym 31423 w_tx_fifo_full
.sym 31424 w_smi_read_req
.sym 31425 w_smi_data_direction
.sym 31426 w_rx_fifo_pulled_data[28]
.sym 31430 w_rx_fifo_pulled_data[17]
.sym 31438 w_rx_fifo_pulled_data[29]
.sym 31442 w_rx_fifo_pulled_data[30]
.sym 31446 w_rx_fifo_pulled_data[19]
.sym 31454 w_rx_fifo_pulled_data[31]
.sym 31458 i_mosi$SB_IO_IN
.sym 31462 spi_if_ins.spi.r_temp_rx_byte[6]
.sym 31466 spi_if_ins.spi.r_temp_rx_byte[1]
.sym 31470 spi_if_ins.spi.r_temp_rx_byte[3]
.sym 31474 spi_if_ins.spi.r_temp_rx_byte[4]
.sym 31478 spi_if_ins.spi.r_temp_rx_byte[2]
.sym 31482 spi_if_ins.spi.r_temp_rx_byte[0]
.sym 31486 spi_if_ins.spi.r_temp_rx_byte[5]
.sym 31490 spi_if_ins.spi.r_rx_byte[2]
.sym 31494 spi_if_ins.spi.r_rx_byte[6]
.sym 31498 spi_if_ins.spi.r_rx_byte[0]
.sym 31502 spi_if_ins.spi.r_rx_byte[4]
.sym 31506 spi_if_ins.spi.r_rx_byte[5]
.sym 31510 spi_if_ins.spi.r_rx_byte[7]
.sym 31514 spi_if_ins.spi.r_rx_byte[1]
.sym 31518 spi_if_ins.spi.r_rx_byte[3]
.sym 31530 spi_if_ins.r_tx_byte[7]
.sym 31537 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
.sym 31538 spi_if_ins.r_tx_byte[5]
.sym 31542 spi_if_ins.spi.r_tx_byte[7]
.sym 31543 spi_if_ins.spi.r_tx_byte[5]
.sym 31544 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
.sym 31545 spi_if_ins.spi.r_tx_bit_count[0]
.sym 31554 spi_if_ins.w_rx_data[1]
.sym 31559 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 31560 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 31561 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 31562 spi_if_ins.w_rx_data[4]
.sym 31566 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
.sym 31572 spi_if_ins.w_rx_data[6]
.sym 31573 spi_if_ins.w_rx_data[5]
.sym 31574 spi_if_ins.w_rx_data[3]
.sym 31578 spi_if_ins.w_rx_data[0]
.sym 31582 spi_if_ins.w_rx_data[5]
.sym 31587 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 31588 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 31589 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 31592 spi_if_ins.w_rx_data[6]
.sym 31593 spi_if_ins.w_rx_data[5]
.sym 31598 w_cs[3]
.sym 31599 w_cs[2]
.sym 31600 w_cs[1]
.sym 31601 w_cs[0]
.sym 31604 spi_if_ins.w_rx_data[6]
.sym 31605 spi_if_ins.w_rx_data[5]
.sym 31607 w_ioc[4]
.sym 31608 w_ioc[3]
.sym 31609 w_ioc[2]
.sym 31612 spi_if_ins.w_rx_data[6]
.sym 31613 spi_if_ins.w_rx_data[5]
.sym 31615 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 31616 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 31617 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 31618 io_ctrl_ins.pmod_dir_state[1]
.sym 31619 o_led1$SB_IO_OUT
.sym 31620 i_button_SB_LUT4_I0_I3[2]
.sym 31621 o_led1_SB_LUT4_I1_I3[3]
.sym 31622 w_rx_data[0]
.sym 31626 w_rx_data[2]
.sym 31630 io_ctrl_ins.pmod_dir_state[3]
.sym 31631 i_button_SB_LUT4_I0_I3[2]
.sym 31632 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2]
.sym 31633 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3]
.sym 31634 w_rx_data[1]
.sym 31638 w_rx_data[5]
.sym 31643 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 31644 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[3]
.sym 31645 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[2]
.sym 31646 w_rx_data[7]
.sym 31652 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 31653 i_button_SB_LUT4_I0_I3[2]
.sym 31654 i_config[2]$SB_IO_IN
.sym 31655 io_ctrl_ins.pmod_dir_state[5]
.sym 31656 i_button_SB_LUT4_I0_I3[2]
.sym 31657 i_button_SB_LUT4_I0_I3[3]
.sym 31658 w_rx_data[6]
.sym 31662 w_rx_data[3]
.sym 31666 w_rx_data[4]
.sym 31671 io_pmod_out[3]$SB_IO_OUT
.sym 31672 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 31673 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 31674 i_rst_b$SB_IO_IN
.sym 31675 w_cs[1]
.sym 31676 w_load
.sym 31677 w_fetch
.sym 31680 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 31681 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[2]
.sym 31682 w_rx_data[3]
.sym 31686 w_rx_data[5]
.sym 31690 w_cs[1]
.sym 31691 w_load
.sym 31692 w_fetch
.sym 31693 o_led0_SB_LUT4_I1_O[1]
.sym 31694 o_tr_vc1_b$SB_IO_OUT
.sym 31695 o_led1_SB_LUT4_I1_I2[1]
.sym 31696 i_button_SB_LUT4_I0_I3[2]
.sym 31697 i_button_SB_LUT4_I0_O[1]
.sym 31698 w_rx_data[6]
.sym 31704 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 31705 i_button_SB_LUT4_I0_O[1]
.sym 31708 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
.sym 31709 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
.sym 31710 w_rx_data[7]
.sym 31716 o_led1_SB_LUT4_I1_O[0]
.sym 31717 o_led0_SB_LUT4_I1_O[0]
.sym 31718 w_rx_data[3]
.sym 31722 w_rx_data[1]
.sym 31727 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[0]
.sym 31728 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
.sym 31729 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
.sym 31730 w_rx_data[4]
.sym 31734 w_rx_data[0]
.sym 31742 w_rx_data[2]
.sym 31747 i_config[1]$SB_IO_IN
.sym 31748 o_led1_SB_LUT4_I1_I3[3]
.sym 31749 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I3[2]
.sym 31780 o_smi_write_req$SB_IO_OUT
.sym 31781 i_rst_b$SB_IO_IN
.sym 31811 w_smi_data_input[7]
.sym 31812 smi_ctrl_ins.tx_reg_state[2]
.sym 31813 smi_ctrl_ins.tx_reg_state[1]
.sym 31815 i_rst_b$SB_IO_IN
.sym 31816 w_smi_data_input[7]
.sym 31817 smi_ctrl_ins.tx_reg_state[2]
.sym 31819 i_rst_b$SB_IO_IN
.sym 31820 w_smi_data_input[7]
.sym 31821 smi_ctrl_ins.tx_reg_state[0]
.sym 31822 i_rst_b$SB_IO_IN
.sym 31823 w_smi_data_input[7]
.sym 31824 smi_ctrl_ins.tx_reg_state[3]
.sym 31825 smi_ctrl_ins.tx_reg_state[0]
.sym 31827 i_rst_b$SB_IO_IN
.sym 31828 w_smi_data_input[7]
.sym 31829 smi_ctrl_ins.tx_reg_state[1]
.sym 31832 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
.sym 31833 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
.sym 31835 i_rst_b$SB_IO_IN
.sym 31836 smi_ctrl_ins.tx_reg_state[3]
.sym 31837 smi_ctrl_ins.tx_reg_state[0]
.sym 31850 smi_ctrl_ins.w_fifo_push_trigger
.sym 31882 tx_fifo.rd_addr_gray[8]
.sym 31902 tx_fifo.rd_addr_gray_wr[8]
.sym 31909 i_ss$SB_IO_IN
.sym 31970 spi_if_ins.spi.r_temp_rx_byte[1]
.sym 31974 spi_if_ins.spi.r_temp_rx_byte[3]
.sym 31978 spi_if_ins.spi.r_temp_rx_byte[2]
.sym 31982 spi_if_ins.spi.r_temp_rx_byte[4]
.sym 31990 spi_if_ins.spi.r_temp_rx_byte[5]
.sym 31994 i_mosi$SB_IO_IN
.sym 31998 spi_if_ins.spi.r_temp_rx_byte[0]
.sym 32020 i_smi_soe_se$SB_IO_IN
.sym 32021 i_rst_b$SB_IO_IN
.sym 32027 spi_if_ins.r_tx_byte[7]
.sym 32028 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
.sym 32029 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
.sym 32054 w_rx_data[0]
.sym 32070 w_cs[2]
.sym 32071 w_load
.sym 32072 w_fetch
.sym 32073 o_led1_SB_LUT4_I1_I3[3]
.sym 32090 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
.sym 32098 w_cs[1]
.sym 32099 w_load
.sym 32100 w_fetch
.sym 32101 o_led1_SB_LUT4_I1_I3[3]
.sym 32118 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
.sym 32119 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
.sym 32120 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
.sym 32121 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
.sym 32134 w_rx_data[7]
.sym 32138 io_pmod_out[2]$SB_IO_OUT
.sym 32139 o_shdn_tx_lna$SB_IO_OUT
.sym 32140 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 32141 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 32143 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[0]
.sym 32144 i_button_SB_LUT4_I0_I3[2]
.sym 32145 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2]
.sym 32154 w_rx_data[3]
.sym 32159 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 32160 io_ctrl_ins.pmod_state_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
.sym 32161 o_led1_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
.sym 32183 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[0]
.sym 32184 i_button_SB_LUT4_I0_I3_SB_LUT4_O_I2[1]
.sym 32185 io_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O[2]
.sym 32191 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[0]
.sym 32192 o_led0_SB_LUT4_I1_O[1]
.sym 32193 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2]
.sym 32196 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFER_E_Q[0]
.sym 32197 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 32200 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
.sym 32201 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
.sym 32210 o_led1_SB_LUT4_I1_I3[0]
.sym 32211 o_led0$SB_IO_OUT
.sym 32212 i_button_SB_LUT4_I0_I3[2]
.sym 32213 o_led1_SB_LUT4_I1_I3[3]
.sym 32214 i_config[0]$SB_IO_IN
.sym 32215 o_tr_vc2$SB_IO_OUT
.sym 32216 o_led1_SB_LUT4_I1_I3[3]
.sym 32217 i_button_SB_LUT4_I0_O[1]
.sym 32251 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[0]
.sym 32252 o_led0_SB_LUT4_I1_O[1]
.sym 32253 io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D_SB_LUT4_O_I3[2]
.sym 32353 w_smi_data_input[7]
.sym 32553 r_counter
.sym 32602 spi_if_ins.w_rx_data[1]
.sym 32622 w_rx_data[0]
.sym 32630 w_rx_data[1]
.sym 32642 w_rx_data[1]
.sym 32654 w_rx_data[3]
.sym 32662 w_rx_data[2]
.sym 32666 w_rx_data[0]
.sym 32700 w_rx_fifo_full
.sym 32701 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[2]
.sym 32707 w_rx_fifo_full
.sym 32708 w_lvds_rx_09_d1_SB_LUT4_I2_O[0]
.sym 32709 w_lvds_rx_09_d1_SB_LUT4_I2_O[3]