kopia lustrzana https://github.com/cariboulabs/cariboulite
86 wiersze
2.7 KiB
Verilog
86 wiersze
2.7 KiB
Verilog
module spi_slave (
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// Control/Data Signals,
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input i_sys_clk, // FPGA Clock
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output reg o_rx_data_valid, // Data Valid pulse (1 clock cycle)
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output reg [7:0] o_rx_byte, // Byte received on MOSI
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input i_tx_data_valid, // Data Valid pulse to register i_tx_byte
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input [7:0] i_tx_byte, // Byte to serialize to MISO.
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// SPI Interface
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input i_spi_sck,
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output reg o_spi_miso,
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input i_spi_mosi,
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input i_spi_cs_b
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);
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reg [2:0] r_rx_bit_count;
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reg [2:0] r_tx_bit_count;
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reg [7:0] r_temp_rx_byte;
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reg [7:0] r_rx_byte;
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reg r_rx_done;
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reg r2_rx_done;
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reg r3_rx_done;
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reg [7:0] r_tx_byte;
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// Purpose: Recover SPI Byte in SPI Clock Domain
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// Samples line on correct edge of SPI Clock
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always @(posedge i_spi_sck /* or posedge i_spi_cs_b*/) begin
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if (i_spi_cs_b) begin
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r_rx_bit_count <= 0;
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r_rx_done <= 1'b0;
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end else begin
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r_rx_bit_count <= r_rx_bit_count + 1;
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r_temp_rx_byte <= {r_temp_rx_byte[6:0], i_spi_mosi};
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if (r_rx_bit_count == 3'b111) begin
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r_rx_done <= 1'b1;
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r_rx_byte <= {r_temp_rx_byte[6:0], i_spi_mosi};
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end else if (r_rx_bit_count == 3'b010) begin
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r_rx_done <= 1'b0;
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end
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end
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end
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// Purpose: Cross from SPI Clock Domain to main FPGA clock domain
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// Assert o_rx_data_valid for 1 clock cycle when o_rx_byte has valid data.
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always @(posedge i_sys_clk) begin
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// Here is where clock domains are crossed.
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// This will require timing constraint created, can set up long path.
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r2_rx_done <= r_rx_done;
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r3_rx_done <= r2_rx_done;
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if (r3_rx_done == 1'b0 && r2_rx_done == 1'b1) begin // rising edge
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o_rx_data_valid <= 1'b1; // Pulse Data Valid 1 clock cycle
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o_rx_byte <= r_rx_byte;
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end else begin
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o_rx_data_valid <= 1'b0;
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end
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end
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reg [2:0] SCKr;
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always @(posedge i_sys_clk) SCKr <= {SCKr[1:0], i_spi_sck};
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wire SCK_risingedge = (SCKr[2:1] == 2'b01); // now we can detect SCK rising edges
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// Purpose: Transmits 1 SPI Byte whenever SPI clock is toggling
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// Will transmit read data back to SW over MISO line.
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// Want to put data on the line immediately when CS goes low.
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always @(posedge i_sys_clk) begin
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if (i_spi_cs_b || i_tx_data_valid) begin
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r_tx_byte <= i_tx_byte;
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r_tx_bit_count <= 3'b110;
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o_spi_miso <= i_tx_byte[3'b111]; // Reset to MSb
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end else begin
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if (SCK_risingedge) begin
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r_tx_bit_count <= r_tx_bit_count - 1;
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o_spi_miso <= r_tx_byte[r_tx_bit_count];
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if (r_tx_bit_count == 3'b000) begin
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r_tx_byte <= 8'b00000000;
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end
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end
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end
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end
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endmodule // SPI_Slave
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