kopia lustrzana https://github.com/cariboulabs/cariboulite
111 wiersze
2.8 KiB
Verilog
111 wiersze
2.8 KiB
Verilog
`include "spi_slave.v"
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module spi_if (
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input i_rst_b, // FPGA Reset
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input i_sys_clk, // FPGA Clock
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output reg [4:0] o_ioc,
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output reg [7:0] o_data_in, // data that was received over SPI
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input [7:0] i_data_out, // data to be sent over the SPI
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output reg [3:0] o_cs,
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output reg o_fetch_cmd,
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output reg o_load_cmd,
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// SPI Interface
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input i_spi_sck,
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output o_spi_miso,
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input i_spi_mosi,
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input i_spi_cs_b
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);
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localparam
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state_idle = 3'b000,
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state_fetch1 = 3'b001,
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state_fetch2 = 3'b010,
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state_load = 3'b011,
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state_post_op= 3'b100;
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// internal registers / wires
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reg [2:0] state_if;
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wire w_rx_data_valid;
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wire [7:0] w_rx_data;
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reg r_tx_data_valid;
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reg [7:0] r_tx_byte;
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reg [4:0] r_ioc;
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reg [7:0] r_data;
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// Initial conditions
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initial begin
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state_if = state_idle;
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end
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spi_slave spi (
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.i_sys_clk (i_sys_clk),
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.o_rx_data_valid(w_rx_data_valid),
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.o_rx_byte (w_rx_data),
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.i_tx_data_valid(r_tx_data_valid),
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.i_tx_byte (r_tx_byte),
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.i_spi_sck (i_spi_sck),
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.o_spi_miso(o_spi_miso),
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.i_spi_mosi(i_spi_mosi),
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.i_spi_cs_b(i_spi_cs_b)
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);
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always @(posedge i_sys_clk) begin
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if (i_rst_b == 1'b0) begin
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state_if <= state_idle;
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end else if (w_rx_data_valid == 1'b1) begin
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// whenever a new byte arrives
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case (state_if)
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//----------------------------------
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state_idle: begin
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o_ioc = w_rx_data[4:0];
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case (w_rx_data[6:5])
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2'b00: o_cs <= 4'b0001;
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2'b01: o_cs <= 4'b0010;
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2'b10: o_cs <= 4'b0100;
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2'b11: o_cs <= 4'b1000;
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endcase
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if (w_rx_data[7] == 1'b1) begin // write command
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state_if <= state_load;
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end else begin // read command
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o_fetch_cmd <= 1'b1;
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state_if <= state_fetch1;
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end
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o_load_cmd <= 1'b0;
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r_tx_data_valid <= 1'b0;
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end
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//----------------------------------
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state_load: begin
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o_data_in <= w_rx_data;
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o_load_cmd <= 1'b1;
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state_if <= state_idle;
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end
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//----------------------------------
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state_post_op: begin
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o_fetch_cmd <= 1'b0;
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o_load_cmd <= 1'b0;
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state_if <= state_idle;
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end
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endcase
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end else begin
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if (state_if == state_fetch1) begin
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o_fetch_cmd <= 1'b0;
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state_if <= state_fetch2;
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end else if (state_if == state_fetch2) begin
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r_tx_byte <= i_data_out;
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r_tx_data_valid <= 1'b1;
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state_if <= state_post_op;
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end else begin
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o_load_cmd <= 1'b0;
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r_tx_data_valid <= 1'b0;
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end
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end
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end
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endmodule // spi_if
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