kopia lustrzana https://github.com/cariboulabs/cariboulite
104 wiersze
3.4 KiB
Plaintext
104 wiersze
3.4 KiB
Plaintext
## PCF format reference
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#######################
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# PCF files contain physical constraints and are specified using the `--pcf` argument. Each (non blank)
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# line contains a command; lines beginning with `#` are comments.
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#
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# Two commands are supported: `set_io` and `set_frequency`.
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# set_io [-nowarn] [-pullup yes|no] [-pullup_resistor 3P3K|6P8K|10K|100K] port pin
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#
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# - Constrains named port `port` to package pin `pin`.
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# - `-nowarn` disables the warning if `port` does not exist.
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# - `-pullup yes` can be used to enable the built in pullup for all iCE40 devices.
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# - `-pullup_resistor` sets the pullup strength, and is available on iCE40 UltraPlus only.
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# - `port` is the name (logical) of the signal (either in verilog or from datasheet)
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# - `pin` is the physical package PIN location (QFN: 1,2,3,..., QN84: A1,B1,A6..., BGA: A4,B4,C3...)
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#
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# set_frequency net frequency
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#
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# Adds a clock constraint to a named net (any alias for the net can be used).
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# - `frequency` is in MHz.
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#
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# Note: "set_frequency" is a non-standard extension, not supported by the vendor toolchain. It allows
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# specifying clock constraints without needing the Python API.
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# For the iCE40 (iCE40LP1K-QN84)
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#set_frequency i_glob_clock 125
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set_frequency w_clock_sys 64
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set_frequency smi_ctrl_ins.soe_and_reset 16
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set_frequency i_smi_swe_srw 16
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set_frequency lvds_clock_buf 64
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set_frequency i_sck 5
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# CLOCK
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set_io i_glob_clock A29
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set_io i_rst_b A43
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# PMOD
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set_io io_pmod_out[0] B24
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set_io io_pmod_out[1] A31
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set_io io_pmod_out[2] B23
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set_io io_pmod_out[3] B21
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set_io io_pmod_in[0] A25
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set_io io_pmod_in[1] A26
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set_io io_pmod_in[2] A27
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set_io io_pmod_in[3] B20
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# MIXER
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set_io o_mixer_fm A32
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set_io o_mixer_en B22
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# RF FRONT-END PATH
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set_io o_rx_h_tx_l A33
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set_io o_rx_h_tx_l_b A35
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set_io o_tr_vc1 A34
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set_io o_tr_vc1_b B27
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set_io o_tr_vc2 B26
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set_io o_shdn_rx_lna A46
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set_io o_shdn_tx_lna B36
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# LVDS TO MODEM
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set_io o_iq_tx_p B4
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set_io o_iq_tx_n A5
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set_io o_iq_tx_clk_p A10
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set_io o_iq_tx_clk_n B8
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set_io i_iq_rx_09_p A4 # Paired with i_iq_rx_09_n @ B3 - positive logic
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set_io i_iq_rx_24_n A2 # Paired with i_iq_rx_24_p @ B1 - negative logic - needs to be negated
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set_io i_iq_rx_clk_p A3 # Paired with i_iq_rx_clk_n @ B2 - positive logic
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# DIGITAL I/F
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set_io -pullup yes i_config[0] B29
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set_io -pullup yes i_config[1] A40
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set_io -pullup yes i_config[2] B30
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set_io -pullup yes i_config[3] A41
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set_io -pullup yes i_button B31
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set_io o_led0 A38
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set_io o_led1 A39
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# SMI TO RPI
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set_io o_smi_write_req A19
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set_io o_smi_read_req B19
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set_io i_smi_a2 A48
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set_io i_smi_a3 A47
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set_io i_smi_soe_se B15
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set_io i_smi_swe_srw B13
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set_io io_smi_data[0] A16
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set_io io_smi_data[1] B11
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set_io io_smi_data[2] B10
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set_io io_smi_data[3] B12
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set_io io_smi_data[4] B14
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set_io io_smi_data[5] A20
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set_io io_smi_data[6] A13
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set_io io_smi_data[7] A14
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# SPI
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set_io i_mosi A22
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set_io i_sck A23
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set_io i_ss B18
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set_io o_miso B17
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