Wykres commitów

14 Commity (main)

Autor SHA1 Wiadomość Data
David Michaeli 125a843908 update lvds tx verilog 2023-07-03 14:40:33 +03:00
David Michaeli 25851685ea firmware merging
updating of install script - consolidation udev into driver and adding to main install
2023-06-05 06:18:30 +00:00
David Michaeli f97f960be6 added TX channel to the FPGA firmware.
LVDS RX -> FIFO Slacks are borderline - need perform timing analysis on the RX FIFO IO (add pipeline?)
Fixed reference to cariboulite_radio_get_native_mtu_size_samples
2023-05-30 14:47:23 +00:00
David Michaeli 0595990c8d Tx side integration firmware 2023-05-30 14:33:08 +03:00
David Michaeli c78e4b760a firmware 2023-02-22 10:42:41 +02:00
David Michaeli 8ab40c3cdf Merge develop_R1 into main 2023-02-14 10:39:24 -05:00
David Michaeli 6ea75a844e curcular buffer integration,
firmware - update
2022-01-03 16:25:52 +02:00
David Michaeli 880c561a10 updates 2021-12-28 00:58:59 +02:00
meexmachina a2ecf08046 fifo 9 bit length, for 900 and 2.4, half tested 2021-09-05 00:08:57 +03:00
meexmachina 421d7e49c4 fifo structure refinement 2021-09-03 23:17:44 +03:00
meexmachina ef5f3ae6bf smi lvds check 2021-09-03 11:19:28 +03:00
meexmachina c3532243a6 modem time synchronization 2021-09-02 00:50:13 +03:00
meexmachina d61828c894 added fifos - work in progress 2021-07-07 16:04:37 +03:00
meexmachina eb699bc363 added lvds rx code 2021-07-07 15:29:32 +03:00