smi lvds check

firmware/lvds_rx.v

@@ -14,7 +14,7 @@ module lvds_rx
     localparam
         state_idle   = 3'b00,
         state_i_phase = 3'b01,
-        state_q_phase = 3'b10;
+        state_q_phase = 3'b11;
 
     // Modem sync symbols
     localparam
@@ -39,12 +39,11 @@ module lvds_rx
     end
 
     // Global Assignments
-    assign o_fifo_push = r_push;
-    //assign o_fifo_data = r_data;
+    //assign o_fifo_push = r_push;
     assign o_fifo_write_clk = i_ddr_clk;
 
     // Main Process
-    always @(negedge i_ddr_clk)
+    always @(posedge i_ddr_clk)
     begin
         if (i_reset) begin
             r_state_if = state_idle;
@@ -53,9 +52,10 @@ module lvds_rx
             r_data = 0;
             r_cnt = 0;
         end else begin
+            o_fifo_push <= r_push;
             case (r_state_if)
                 state_idle: begin
-                    if (i_ddr_data == 2'b10 ) begin
+                    if (i_ddr_data == modem_i_sync ) begin
                         r_state_if <= state_i_phase;
                         r_data[31:2] <= 0;
                         r_data[1:0] <= r_cnt[3:2];
@@ -71,7 +71,7 @@ module lvds_rx
 
                 state_i_phase: begin
                     if (r_phase_count == 3'b000) begin
-                        if (i_ddr_data == 2'b01 ) begin
+                        if (i_ddr_data == modem_q_sync ) begin
                             r_phase_count <= 3'b110;
                             r_state_if <= state_q_phase;
                             r_data <= {r_data[29:0], r_cnt[1:0]};

firmware/top.v

@@ -199,10 +199,12 @@ module top(
       .PACKAGE_PIN(i_iq_rx_clk_p),  // Physical connection to 'i_iq_rx_clk_p'
       .D_IN_0 ( lvds_clock ));      // Wire out to 'lvds_clock'
 
-   SB_GB lvds_clk_buffer (          // Improve 'lvds_clock' fanout by pushing it into
+   /*SB_GB lvds_clk_buffer (          // Improve 'lvds_clock' fanout by pushing it into
                                     // a global high-fanout buffer
       .USER_SIGNAL_TO_GLOBAL_BUFFER (lvds_clock),
       .GLOBAL_BUFFER_OUTPUT(lvds_clock_buf) );
+*/
+   assign lvds_clock_buf = lvds_clock;
 
    // optional for better fanout: seperate the 09 and the 24 buffers and give them
    // both a semparate constraint in the pcf file.
@@ -212,25 +214,25 @@ module top(
       .PIN_TYPE(6'b000000),         // Input only, DDR mode (sample on both pos edge and
                                     // negedge of the input clock)
       .IO_STANDARD("SB_LVDS_INPUT"),// LVDS standard
-      .NEG_TRIGGER(1'b0)            // The signal is not negated
+      .NEG_TRIGGER(1'b1)            // The signal is not negated
    ) iq_rx_24 (
       .PACKAGE_PIN(i_iq_rx_24_n),   // Attention: this is the 'n' input, thus the actual values
                                     //            will need to be negated (PCB layout constraint)
       .INPUT_CLK (lvds_clock_buf),  // The I/O sampling clock with DDR
-      .D_IN_0 ( w_lvds_rx_24_d1 ),  // the 0 deg data output
-      .D_IN_1 ( w_lvds_rx_24_d0 ) );// the 180 deg data output
+      .D_IN_0 ( w_lvds_rx_24_d0 ),  // the 0 deg data output
+      .D_IN_1 ( w_lvds_rx_24_d1 ) );// the 180 deg data output
 
    // Differential 0.9GHz I/Q DDR signal
    SB_IO #(
       .PIN_TYPE(6'b000000),         // Input only, DDR mode (sample on both pos edge and
                                     // negedge of the input clock)
       .IO_STANDARD("SB_LVDS_INPUT"),// LVDS standard
-      .NEG_TRIGGER(1'b1)            // The signal is negated in hardware
+      .NEG_TRIGGER(1'b0)            // The signal is negated in hardware
    ) iq_rx_09 (
       .PACKAGE_PIN(i_iq_rx_09_p),
       .INPUT_CLK (lvds_clock_buf),  // The I/O sampling clock with DDR
-      .D_IN_0 ( w_lvds_rx_09_d1 ),  // the 0 deg data output
-      .D_IN_1 ( w_lvds_rx_09_d0 ) );// the 180 deg data output
+      .D_IN_0 ( w_lvds_rx_09_d0 ),  // the 0 deg data output
+      .D_IN_1 ( w_lvds_rx_09_d1 ) );// the 180 deg data output
 
 
    //=========================================================================
@@ -359,7 +361,8 @@ module top(
 
    // Testing - output the clock signal (positive and negative) to the PMOD
    assign io_pmod[0] = lvds_clock_buf;
-   assign io_pmod[2:1] = {w_lvds_rx_09_d1, w_lvds_rx_09_d0};
+   assign io_pmod[1] = w_lvds_rx_09_d1;
+   assign io_pmod[2] = w_lvds_rx_09_d0;
    assign io_pmod[3] = w_rx_09_fifo_push;
    assign io_pmod[4] = w_rx_09_fifo_pull;
    assign io_pmod[5] = w_rx_09_fifo_empty;

software/libcariboulite/src/at86rf215/test_at86rf215.c

@@ -112,7 +112,7 @@ void test_at86rf215_sweep_frequencies(at86rf215_st* dev,
 int test_at86rf215_continues_iq_rx (at86rf215_st* dev, at86rf215_rf_channel_en radio,
                                         uint32_t freq_hz, int usec_timeout)
 {
-    at86rf215_setup_iq_radio_receive (dev, radio, freq_hz, 0, at86rf215_iq_clock_data_skew_4_906ns);
+    at86rf215_setup_iq_radio_receive (dev, radio, freq_hz, 0, at86rf215_iq_clock_data_skew_1_906ns);
     printf("Started I/Q RX session for Radio %d, Freq: %d Hz, timeout: %d usec (0=infinity)\n",
         radio, freq_hz, usec_timeout);