kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
33 wiersze
462 B
Verilog
33 wiersze
462 B
Verilog
module vcxo_controller(
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pwm_clk_in,
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VCXO_correction,
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pump
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);
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input pwm_clk_in;
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input unsigned [15:0] VCXO_correction;
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output reg pump = 0;
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reg unsigned [15:0] PWM_counter_MAX = 65500;
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reg unsigned [15:0] PWM_counter = 0;
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always @ (posedge pwm_clk_in)
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begin
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//count PWM
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if(PWM_counter > PWM_counter_MAX)
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PWM_counter = 0;
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else
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PWM_counter = PWM_counter + 1;
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//do PWM
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if(PWM_counter <= VCXO_correction)
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pump = 1;
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else
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pump = 0;
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end
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endmodule
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