kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
314 wiersze
12 KiB
XML
314 wiersze
12 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<deploy date="2021.03.31.22:07:24" outputDirectory="C:/FPGA/tx_nco/">
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<perimeter>
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<parameter
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name="AUTO_GENERATION_ID"
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type="Integer"
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defaultValue="0"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_UNIQUE_ID"
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type="String"
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defaultValue=""
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE_FAMILY"
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type="String"
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defaultValue="Cyclone IV E"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE"
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type="String"
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defaultValue="EP4CE10E22C8"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE_SPEEDGRADE"
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type="String"
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defaultValue="8"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_CLK_CLOCK_RATE"
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type="Long"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_CLK_CLOCK_DOMAIN"
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type="Integer"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_CLK_RESET_DOMAIN"
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type="Integer"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<interface name="clk" kind="clock" start="0">
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<property name="clockRate" value="0" />
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<property name="externallyDriven" value="false" />
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<property name="ptfSchematicName" value="" />
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<port name="clk" direction="input" role="clk" width="1" />
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</interface>
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<interface name="in" kind="conduit" start="0">
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<property name="associatedClock" value="clk" />
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<property name="associatedReset" value="rst" />
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<port name="clken" direction="input" role="clken" width="1" />
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<port name="phi_inc_i" direction="input" role="phi_inc_i" width="22" />
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</interface>
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<interface name="out" kind="conduit" start="0">
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<property name="associatedClock" value="clk" />
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<property name="associatedReset" value="rst" />
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<port name="fsin_o" direction="output" role="fsin_o" width="16" />
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<port name="fcos_o" direction="output" role="fcos_o" width="16" />
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<port name="out_valid" direction="output" role="out_valid" width="1" />
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</interface>
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<interface name="rst" kind="reset" start="0">
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<property name="associatedClock" value="clk" />
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<property name="synchronousEdges" value="DEASSERT" />
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<port name="reset_n" direction="input" role="reset_n" width="1" />
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</interface>
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</perimeter>
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<entity
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path=""
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parameterizationKey="tx_nco:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=EP4CE10E22C8,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1617214043,AUTO_UNIQUE_ID=(altera_nco_ii:18.1:apr=22,aprf=32,apri=22,aprp=16,arch=trig,cordic_arch=parallel,cycles_per_output=1,design_env=NATIVE,dpri=4,fmod_pipe=1,freq_out=7.1,fsamp=153.6,hyper_opt=false,hyper_opt_select=false,mpr=16,numba=1,numch=1,phi_inc=193877,pmod_pipe=1,real_freq_out=7.1,selected_device_family=Cyclone IV E,trig_cycles_per_output=1,use_dedicated_multipliers=true,want_dither=false,want_freq_mod=false,want_phase_mod=false,want_sin_and_cos=dual_output)"
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instancePathKey="tx_nco"
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kind="tx_nco"
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version="1.0"
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name="tx_nco">
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<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
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<parameter name="AUTO_GENERATION_ID" value="1617214043" />
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<parameter name="AUTO_DEVICE" value="EP4CE10E22C8" />
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<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
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<parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
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<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
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<parameter name="AUTO_UNIQUE_ID" value="" />
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
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<generatedFiles>
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<file path="C:/FPGA/tx_nco/synthesis/tx_nco.v" type="VERILOG" />
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</generatedFiles>
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<childGeneratedFiles>
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_nco_madx_cen.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_nco_mady_cen.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_nco_isdr.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_nco_mob_w.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_nco_as_m_dp_cen.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_nco_as_m_cen.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_altqmcpipe.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_gam_dp.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_nco_derot.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/tx_nco_nco_ii_0_sin_c.hex"
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type="HEX"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/tx_nco_nco_ii_0_cos_c.hex"
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type="HEX"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/tx_nco_nco_ii_0_sin_f.hex"
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type="HEX"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/tx_nco_nco_ii_0_cos_f.hex"
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type="HEX"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/tx_nco_nco_ii_0.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_altq.ocp"
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type="OTHER"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_altqmcash.ocp"
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type="OTHER"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_altqmcpipe.ocp"
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type="OTHER"
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attributes="" />
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</childGeneratedFiles>
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<sourceFiles>
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<file path="C:/FPGA/tx_nco.qsys" />
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</sourceFiles>
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<childSourceFiles>
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<file
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path="C:/intelfpga/18.1/ip/altera/dsp/altera_nco_ii/altera_nco_ii_hw.tcl" />
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<file path="C:/intelFPGA/18.1/ip/altera/dsp/altera_nco_ii/nco_helper.jar" />
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<file
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path="C:/intelFPGA/18.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
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</childSourceFiles>
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<messages>
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<message level="Debug" culprit="tx_nco">queue size: 0 starting:tx_nco "tx_nco"</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Debug">Transform: CustomInstructionTransform</message>
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<message level="Debug">No custom instruction connections, skipping transform </message>
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<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
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<message level="Debug">Transform: MMTransform</message>
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<message level="Debug">Transform: InterruptMapperTransform</message>
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<message level="Debug">Transform: InterruptSyncTransform</message>
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<message level="Debug">Transform: InterruptFanoutTransform</message>
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<message level="Debug">Transform: AvalonStreamingTransform</message>
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<message level="Debug">Transform: ResetAdaptation</message>
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<message level="Debug" culprit="tx_nco"><![CDATA["<b>tx_nco</b>" reuses <b>altera_nco_ii</b> "<b>submodules/tx_nco_nco_ii_0</b>"]]></message>
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<message level="Debug" culprit="tx_nco">queue size: 0 starting:altera_nco_ii "submodules/tx_nco_nco_ii_0"</message>
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<message level="Info" culprit="nco_ii_0"><![CDATA["<b>tx_nco</b>" instantiated <b>altera_nco_ii</b> "<b>nco_ii_0</b>"]]></message>
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</messages>
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</entity>
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<entity
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path="submodules/"
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parameterizationKey="altera_nco_ii:18.1:apr=22,aprf=32,apri=22,aprp=16,arch=trig,cordic_arch=parallel,cycles_per_output=1,design_env=NATIVE,dpri=4,fmod_pipe=1,freq_out=7.1,fsamp=153.6,hyper_opt=false,hyper_opt_select=false,mpr=16,numba=1,numch=1,phi_inc=193877,pmod_pipe=1,real_freq_out=7.1,selected_device_family=Cyclone IV E,trig_cycles_per_output=1,use_dedicated_multipliers=true,want_dither=false,want_freq_mod=false,want_phase_mod=false,want_sin_and_cos=dual_output"
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instancePathKey="tx_nco:.:nco_ii_0"
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kind="altera_nco_ii"
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version="18.1"
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name="tx_nco_nco_ii_0">
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<parameter name="aprp" value="16" />
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<parameter name="numba" value="1" />
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<parameter name="cordic_arch" value="parallel" />
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<parameter name="pmod_pipe" value="1" />
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<parameter name="fsamp" value="153.6" />
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<parameter name="cycles_per_output" value="1" />
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<parameter name="selected_device_family" value="Cyclone IV E" />
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<parameter name="apri" value="22" />
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<parameter name="aprf" value="32" />
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<parameter name="want_dither" value="false" />
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<parameter name="hyper_opt_select" value="false" />
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<parameter name="want_phase_mod" value="false" />
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<parameter name="apr" value="22" />
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<parameter name="hyper_opt" value="false" />
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<parameter name="trig_cycles_per_output" value="1" />
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<parameter name="dpri" value="4" />
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<parameter name="mpr" value="16" />
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<parameter name="design_env" value="NATIVE" />
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<parameter name="numch" value="1" />
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<parameter name="want_freq_mod" value="false" />
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<parameter name="use_dedicated_multipliers" value="true" />
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<parameter name="want_sin_and_cos" value="dual_output" />
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<parameter name="phi_inc" value="193877" />
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<parameter name="fmod_pipe" value="1" />
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<parameter name="arch" value="trig" />
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<parameter name="freq_out" value="7.1" />
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<parameter name="real_freq_out" value="7.1" />
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<generatedFiles>
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_nco_madx_cen.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_nco_mady_cen.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_nco_isdr.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_nco_mob_w.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_nco_as_m_dp_cen.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_nco_as_m_cen.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_altqmcpipe.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_gam_dp.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_nco_derot.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/tx_nco_nco_ii_0_sin_c.hex"
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type="HEX"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/tx_nco_nco_ii_0_cos_c.hex"
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type="HEX"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/tx_nco_nco_ii_0_sin_f.hex"
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type="HEX"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/tx_nco_nco_ii_0_cos_f.hex"
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type="HEX"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/tx_nco_nco_ii_0.v"
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type="VERILOG"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_altq.ocp"
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type="OTHER"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_altqmcash.ocp"
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type="OTHER"
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attributes="" />
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<file
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path="C:/FPGA/tx_nco/synthesis/submodules/asj_altqmcpipe.ocp"
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type="OTHER"
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attributes="" />
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</generatedFiles>
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<childGeneratedFiles/>
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<sourceFiles>
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<file
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path="C:/intelfpga/18.1/ip/altera/dsp/altera_nco_ii/altera_nco_ii_hw.tcl" />
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<file path="C:/intelFPGA/18.1/ip/altera/dsp/altera_nco_ii/nco_helper.jar" />
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<file
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path="C:/intelFPGA/18.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
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</sourceFiles>
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<childSourceFiles/>
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<instantiator instantiator="tx_nco" as="nco_ii_0" />
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<messages>
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<message level="Debug" culprit="tx_nco">queue size: 0 starting:altera_nco_ii "submodules/tx_nco_nco_ii_0"</message>
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<message level="Info" culprit="nco_ii_0"><![CDATA["<b>tx_nco</b>" instantiated <b>altera_nco_ii</b> "<b>nco_ii_0</b>"]]></message>
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</messages>
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</entity>
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</deploy>
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