kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
89 wiersze
3.0 KiB
VHDL
89 wiersze
3.0 KiB
VHDL
-- (C) 2001-2018 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions and other
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-- software and tools, and its AMPP partner logic functions, and any output
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-- files from any of the foregoing (including device programming or simulation
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-- files), and any associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License Subscription
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-- Agreement, Intel FPGA IP License Agreement, or other applicable
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-- license agreement, including, without limitation, that your use is for the
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-- sole purpose of programming logic devices manufactured by Intel and sold by
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-- Intel or its authorized distributors. Please refer to the applicable
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-- agreement for further details.
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-------------------------------------------------------------------------
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-------------------------------------------------------------------------
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--
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-- $Revision: #1 $
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-- $Date: 2009/07/29 $
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-- Author : Boon Hong Oh
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--
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-- Project : Avalon Streaming Wrapper for HP FIR
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--
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-- Description :
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--
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-- This file is the Interface controller for the Avalon Streaming Wrapper.
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-- The control signals between sink, core, and source modules are communicated
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-- via the controller. The stall output is used as the core enable signal in
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-- the wrapper.
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--
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-- ALTERA Confidential and Proprietary
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-- Copyright 2006 (c) Altera Corporation
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-- All rights reserved
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--
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-------------------------------------------------------------------------
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-------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity auk_dspip_avalon_streaming_controller_hpfir is
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port(
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clk : in std_logic;
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--clk_en : in std_logic := '1';
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reset_n : in std_logic;
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--ready : in std_logic;
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sink_packet_error : in std_logic_vector (1 downto 0);
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--sink_stall : in std_logic;
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source_stall : in std_logic;
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valid : in std_logic;
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reset_design : out std_logic;
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sink_ready_ctrl : out std_logic;
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source_packet_error : out std_logic_vector (1 downto 0) := (others => '0');
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source_valid_ctrl : out std_logic;
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stall : out std_logic
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);
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-- Declarations
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end auk_dspip_avalon_streaming_controller_hpfir;
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-- hds interface_end
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architecture struct of auk_dspip_avalon_streaming_controller_hpfir is
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-- signal stall_int : std_logic;
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-- signal stall_reg : std_logic;
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-- attribute maxfan : integer;
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-- attribute maxfan of stall_reg : signal is 500;
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begin
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reset_design <= not reset_n;
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--should not stop sending data to source module when the sink module is stalled
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--should only stop sending when the source module is stalled
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--Disable the FIR core when backpressure
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stall <= source_stall;
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source_valid_ctrl <= valid;
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-- Sink FIFO and FIR core are disabled at the same time
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sink_ready_ctrl <= not(source_stall);
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source_packet_error <= sink_packet_error;
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end struct;
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