kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
30 wiersze
1.4 KiB
VHDL
30 wiersze
1.4 KiB
VHDL
component tx_cic is
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port (
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in_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- error
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in_valid : in std_logic := 'X'; -- valid
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in_ready : out std_logic; -- ready
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in_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- in_data
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out_data : out std_logic_vector(15 downto 0); -- out_data
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out_error : out std_logic_vector(1 downto 0); -- error
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out_valid : out std_logic; -- valid
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out_ready : in std_logic := 'X'; -- ready
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clk : in std_logic := 'X'; -- clk
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reset_n : in std_logic := 'X' -- reset_n
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);
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end component tx_cic;
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u0 : component tx_cic
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port map (
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in_error => CONNECTED_TO_in_error, -- av_st_in.error
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in_valid => CONNECTED_TO_in_valid, -- .valid
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in_ready => CONNECTED_TO_in_ready, -- .ready
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in_data => CONNECTED_TO_in_data, -- .in_data
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out_data => CONNECTED_TO_out_data, -- av_st_out.out_data
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out_error => CONNECTED_TO_out_error, -- .error
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out_valid => CONNECTED_TO_out_valid, -- .valid
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out_ready => CONNECTED_TO_out_ready, -- .ready
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clk => CONNECTED_TO_clk, -- clock.clk
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reset_n => CONNECTED_TO_reset_n -- reset.reset_n
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);
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