kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
15 wiersze
683 B
Verilog
15 wiersze
683 B
Verilog
rx_cic u0 (
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.in_error (<connected-to-in_error>), // av_st_in.error
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.in_valid (<connected-to-in_valid>), // .valid
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.in_ready (<connected-to-in_ready>), // .ready
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.in_data (<connected-to-in_data>), // .in_data
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.out_data (<connected-to-out_data>), // av_st_out.out_data
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.out_error (<connected-to-out_error>), // .error
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.out_valid (<connected-to-out_valid>), // .valid
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.out_ready (<connected-to-out_ready>), // .ready
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.clken (<connected-to-clken>), // clken.clken
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.clk (<connected-to-clk>), // clock.clk
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.reset_n (<connected-to-reset_n>) // reset.reset_n
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);
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