kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
27 wiersze
361 B
Verilog
27 wiersze
361 B
Verilog
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module rx_cic (
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in_error,
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in_valid,
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in_ready,
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in_data,
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out_data,
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out_error,
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out_valid,
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out_ready,
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clken,
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clk,
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reset_n);
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input [1:0] in_error;
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input in_valid;
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output in_ready;
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input [22:0] in_data;
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output [31:0] out_data;
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output [1:0] out_error;
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output out_valid;
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input out_ready;
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input clken;
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input clk;
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input reset_n;
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endmodule
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