Wolf-LITE/FPGA/tx_ciccomp.v

103 wiersze
7.1 KiB
Verilog

// megafunction wizard: %FIR II v18.1%
// GENERATION: XML
// tx_ciccomp.v
// Generated using ACDS version 18.1 625
`timescale 1 ps / 1 ps
module tx_ciccomp (
input wire clk, // clk.clk
input wire reset_n, // rst.reset_n
input wire [15:0] ast_sink_data, // avalon_streaming_sink.data
input wire ast_sink_valid, // .valid
input wire [1:0] ast_sink_error, // .error
output wire [29:0] ast_source_data, // avalon_streaming_source.data
output wire ast_source_valid, // .valid
output wire [1:0] ast_source_error // .error
);
tx_ciccomp_0002 tx_ciccomp_inst (
.clk (clk), // clk.clk
.reset_n (reset_n), // rst.reset_n
.ast_sink_data (ast_sink_data), // avalon_streaming_sink.data
.ast_sink_valid (ast_sink_valid), // .valid
.ast_sink_error (ast_sink_error), // .error
.ast_source_data (ast_source_data), // avalon_streaming_source.data
.ast_source_valid (ast_source_valid), // .valid
.ast_source_error (ast_source_error) // .error
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2021 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_fir_compiler_ii" version="18.1" >
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// Retrieval info: <generic name="decimFactor" value="1" />
// Retrieval info: <generic name="symmetryMode" value="nsym" />
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// Retrieval info: <generic name="inputChannelNum" value="1" />
// Retrieval info: <generic name="clockRate" value="160.8" />
// Retrieval info: <generic name="clockSlack" value="45" />
// Retrieval info: <generic name="inputRate" value="0.048" />
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// Retrieval info: <generic name="channelModes" value="0,1,2,3" />
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// Retrieval info: <generic name="inputFracBitWidth" value="0" />
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// Retrieval info: <generic name="bankDisplay" value="0" />
// Retrieval info: </instance>
// IPFS_FILES : tx_ciccomp.vo
// RELATED_FILES: tx_ciccomp.v, dspba_library_package.vhd, dspba_library.vhd, auk_dspip_math_pkg_hpfir.vhd, auk_dspip_lib_pkg_hpfir.vhd, auk_dspip_avalon_streaming_controller_hpfir.vhd, auk_dspip_avalon_streaming_sink_hpfir.vhd, auk_dspip_avalon_streaming_source_hpfir.vhd, auk_dspip_roundsat_hpfir.vhd, altera_avalon_sc_fifo.v, tx_ciccomp_0002_rtl_core.vhd, tx_ciccomp_0002_ast.vhd, tx_ciccomp_0002.vhd